DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-3, 6-12, and 15-20 in the reply filed on 2/2/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibib et al. (US pub 20060038224).
With respect to claim 1, Shibib et al. teach an integrated circuit device comprising (see figs. 1-6E, particularly figs. 1 and 2 and associated text):
a semiconductor substrate 106,206;
a first conductivity type well 104,204 and a second conductivity type well 112,212 formed in the semiconductor substrate;
a source region 110,210 formed in the second conductivity type well;
a drain region 108,208 formed in the first conductivity type well;
a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit (121 and upper part of 120) and a lower insulating unit (lower part of 120), wherein the upper insulating unit fills an upper substrate recess that extends from an upper surface of the first conductivity type well and into the first conductivity type well, and wherein the lower insulating unit fills a lower substrate recess that extends from a bottom surface of the upper substrate recess and into the first conductivity type well; and
a gate electrode layer (GATE, 216, 316) disposed between the source region and the recess insulating layer, and arranged on the first conductivity type well and the second conductivity type well, and
wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to a center of the upper insulating unit.
With respect to claim 2, Shibib et al. teach in a horizontal direction, the upper insulating unit has a first length, and the lower insulating unit has a second length that is less than the first length. See figs. 1 and 2 and associated text.
With respect to claim 6, Shibib et al. teach the semiconductor substrate comprises a fin-type active region 104,204 protruding in a vertical direction, and the gate electrode layer covers an upper surface and side surfaces of the fin-type active region. See figs. 1 and 2 and associated text.
With respect to claim 9, Shibib et al. teach a thickness of the lower insulating unit is greater than a thickness of the upper insulating unit. See figs. 1 and 2 and associated text.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibib et al. (US pub 20060038224).
With respect to claim 11, Shibib et al. teach an integrated circuit device comprising (see figs. 1-6E, particularly figs. 1 and 2 and associated text):
a semiconductor substrate 106, 206 including a fin-type active region 104 protruding in a vertical direction;
a first conductivity type well 104,204 and a second conductivity type well 112, 212 arranged in a first horizontal direction and in a portion of the semiconductor substrate that includes the fin-type active region;
a source region 110,210 formed in the second conductivity type well; a drain region 108,208 formed in the first conductivity type well;
a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit (121 and upper part of 120) and a lower insulating unit (lower part of 120), wherein the upper insulating unit extends from an upper surface of the first conductivity type well and into the first conductivity type well, and fills an upper substrate recess having a first length in the first horizontal direction, and wherein the lower insulating unit extends from a bottom surface of the upper substrate recess and into the first conductivity type well, and fills a lower substrate recess having a second length that is less than the first length in the first horizontal direction; and
a gate electrode layer (GATE, 216, 316) disposed between the source region and the recess insulating layer, and arranged on the first conductivity type well and the second conductivity type well, wherein the gate electrode layer covers an upper surface and side surfaces of the fin-type active region,
wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to a center of the upper insulating unit.
Allowable Subject Matter
Claims 3, 7-8, 10, and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowed.
Examiner’s Cited References
The cited references generally show the similar or related structure having a substrate having a fin type region having a first well having a drain and a second well having a source, and having an isolation region having an upper portion and a lower portion having different lengths and depths between source and drain, having as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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