DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,2,5,7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al., (Choi) US 2022/0285302 in view of Chen et al., (Chen) US 2021/0305259.
Regarding claim 1, Choi shows in FIG. 2, a semiconductor device, comprising: a first semiconductor structure including a first substrate (101)[0057], circuit devices (130,180,245,250) on the first substrate, a lower interconnection structure (130) electrically connected to the circuit devices, and a lower bonding structure (180)[0028] connected to the lower interconnection structure (130)[0029]; and a second semiconductor structure (CELL area, [0028]) including a second substrate (201) on the first semiconductor structure, a stopper layer (204)[0039](the layer can be an insulating layer) in contact with a lower surface of the second substrate (201) and extending in a first direction parallel to a lower surface of the second substrate (201), gate electrodes (230) stacked and spaced apart from each other in a vertical direction perpendicular to a lower surface of the second substrate (201), channel structures (CH)[0035] penetrating through the gate electrodes (230), extending in the vertical direction, and each including a channel layer, an upper interconnection structure (254) below the gate electrodes and the channel structures, a peripheral contact plug (251) spaced apart from the second substrate, and an upper bonding structure (256) connected to the upper interconnection structure and bonded to the lower bonding structure (180), wherein: the channel structures (CH)penetrate at least a first portion of the stopper layer (204).
Choi differs from the claimed invention because he does not explicitly disclose a device wherein a peripheral contact plug penetrates at least a second portion of the stopper layer.
Chen discloses a device wherein a peripheral contact plug (444) penetrates at least a second portion of the stopper layer (436) (layer under 434).
Chen is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Choi. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Chen in the device of Choi because it will facilitate channel control [0076].
Regarding claim 2, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device, wherein an uppermost end of each of the channel structures (CH) is disposed on a level higher than a level of an upper surface of the stopper layer (204).
Regarding claim 5, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device wherein the stopper layer (204) [0039] includes an insulating material [0039].
Regarding claim 7, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device further comprising: a source contact plug (272)[0076] extending from a level lower than a level of a lowermost gate electrode (230) most adjacent to the first semiconductor structure among the gate electrodes to at least an internal region of the second substrate (201) and electrically connected to the second substrate (201), wherein the source contact plug (272) penetrates the stopper layer (204).
Regarding claim 8, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device, wherein an uppermost end of the channel layer (CH) is in contact with the second substrate (201), and each of the channel structures further includes a gate dielectric layer disposed between the gate electrodes and the channel layer.
Regarding claim 9, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device, wherein the stopper layer (204) is in contact with the gate dielectric layer (of CH).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chen as applied to claims 1,2,5,7-9, and further in view of Kim et al., (Kim) US 2021/0036001.
Regarding claim 6, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device having a second substrate (201).
Choi in view of Chen differs from the claimed invention because he does not explicitly disclose a device wherein the second substrate includes a doped polysilicon layer.
Kim discloses a device wherein the second substrate includes a doped polysilicon layer [0020].
Kim is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Choi in view of Chen. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Kim in the device Choi in view of Chen because it will improve electrical characteristics of the device [0004].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chen as applied to claims 1,2,5,7-9, and further in view of Kim et al., (Kim) US 2019/0221557.
Regarding claim 10, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device, wherein: each of the channel layers (CH) protrudes into the second substrate (201).
Choi in view of Chen differs from the claimed invention because he does not explicitly disclose a device wherein at least a portion of the channel structures, protruding lengths of the channel layers are different.
Kim discloses a device wherein at least a portion of the channel structures, protruding lengths of the channel layers are different (601,602 are different lengths).
Kim is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Choi in view of Chen. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Kim in the device Choi in view of Chen because it reduces the negative effect of the high temperature processing steps [0061].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chen as applied to claims 1,2,5,7-9, and further in view of Choi et al., (Choi) US 2023/0005952.
Regarding claim 11, Choi in view of Chen discloses and shows in FIG. 2, a semiconductor device, wherein the second semiconductor structure includes: a peripheral contact via (265) in contact with the upper surface of the peripheral contact plug (251); a first conductive pad (270) on the peripheral contact via.
Choi in view of Chen differs from the claimed invention because he does not explicitly disclose a second conductive pad electrically connected to the second substrate on the second substrate.
Choi discloses a device having a second conductive pad (263)[0094] electrically connected to the second substrate on the second substrate.
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Choi in view of Chen. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device Choi in view of Chen because it will transmit a source voltage that is discharged during a read operation or a verify operation [0096].
Allowable Subject Matter
Claims 3,4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARC - ANTHONY ARMAND
Examiner
Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813