Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 28-47 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by FUJIKI (Pub. No.: US 2019/0198524).
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Re claim 28, FUJIKI teaches a semiconductor memory device, comprising:
a substrate (10/32) within one memory chip;
a plurality of memory regions ([MR], FIGS. 4, 8 and 12 [as shown above]) on the substrate, the plurality of memory regions being arranged two-dimensionally;
a cutting structure ([FCS]/[SCS]) on the substrate and surrounding each of the plurality of memory regions, the cutting structure being configured to separate the plurality of memory regions [MR] from each other, the cutting structure including a first cutting structure [FCS] and a second cutting structure [SCS] that extend parallel to each other and are between adjacent ones of the plurality of memory regions; and
a through contact (78, ¶ [0042]) between the first and second cutting structures.
Re claim 29, FUJIKI, FIG. 12 teaches the device of claim 28, wherein each of the plurality of memory regions includes a plurality of electrodes (41, ¶ [0049]) that are stacked on the substrate; and
a vertical channel structure (62, [0044]) that penetrates the plurality of electrodes (41) and is connected to the substrate.
Re claim 30, FUJIKI, FIG. 12 teaches the device of wherein the substrate includes a plurality of semiconductor layers (62) that are disposed in the plurality of memory regions [MR], respectively, wherein the cutting structure ([FCS]/[SCS]) is configured to separate the plurality of semiconductor layers from each other.
Re claim 31, FUJIKI, FIG. 12 [as shown above] teaches the device of claim 30, wherein the substrate further includes a dummy semiconductor layer [D] between the first and second cutting structures ([FCS]/[SCS]).
Re claim 32, FUJIKI, FIG. 12 teaches the device of claim 31, wherein the through contact (78) extends further downward than the dummy semiconductor layer [D].
Re claim 33, FUJIKI, FIG. 12 teaches the device of claim 28, further comprising: a peripheral circuit structure (36/37) below the substrate, wherein the through contact (78) is electrically connected to the peripheral circuit structure.
Re claim 34, FUJIKI, FIG. 12 teaches the device of claim 28, further comprising: a through contact region between the first and second cutting structures, and wherein the through contact (78) is disposed in the through contact region (78/79).
Re claim 35, FUJIKI, FIG. 12 teaches the device of wherein the substrate includes a dielectric pattern (79, [0042]) disposed in the through contact region (78/79), and wherein the through contact penetrates the dielectric pattern.
Re claim 36, FUJIKI, FIG. 12 teaches the device of wherein the cutting structure includes a plurality of dummy contacts and a spacer that surrounds the dummy contacts, and wherein the dummy contacts [D] are arranged to surround each of the plurality of memory regions (63, [0036]).
Re claim 37, FUJIKI, FIG. 12 teaches the device of claim 28, wherein the substrate (10/32) further includes a metal pattern (36/37) at a lower portion thereof.
Re claim 29, FUJIKI, FIGS. 8 and 12 [as shown above] teaches semiconductor memory device, comprising:
a substrate (10/32);
a plurality of memory regions (63) on the substrate, the plurality of memory regions being arranged two-dimensionally;
a cutting structure ([FCS]/[SCS]) on the substrate and surrounding each of the plurality of memory regions; and
a through contact (78) between adjacent ones of the plurality of memory regions, wherein the substrate includes a dummy semiconductor layer [D] defined by the cutting structure, and
wherein the through contact (78) is on the dummy semiconductor layer.
Re claim 39, FUJIKI, FIG. 12 teaches the device of claim 38, wherein each of the plurality of memory regions includes:
a plurality of electrodes (41) that are stacked on the substrate; and
a vertical channel structure (62) that penetrates the plurality of electrodes (41) and is connected to the substrate.
Re claim 40, FUJIKI, FIG. 12 teaches the device of claim 38, wherein the through contact (78) extends further downward than the dummy semiconductor layer [D].
Re claim 41, FUJIKI, FIG. 12 teaches the device of claim 38, further comprising: a peripheral circuit structure (36/37) below the substrate (10/32), wherein the through contact (78) is electrically connected to the peripheral circuit structure.
Re claim 42, FUJIKI, FIG. 12 teaches the device of claim 38, further comprising: a through contact region (78/79) on the dummy semiconductor layer [D], wherein the substrate further includes a dielectric pattern (79) disposed in the through contact region (78/79), and wherein the through contact (78) is disposed in the through contact region.
Re claim 43, FUJIKI, FIGS. 8 and 12 [as shown above] teaches a semiconductor memory device, comprising:
a substrate (10/32);
a first memory region (far left 63) and a second memory region (far right 63) on the substrate;
a cutting structure ([FCS]/[SCS]) on the substrate and being configured to separate the first and second memory regions from each other, the cutting structure including a first cutting structure [FCS] and a second cutting structure [SCS] that extend parallel to each other in a first direction (vertical); and
a through contact (78) between the first and second cutting structures.
Re claim 44, FUJIKI, FIG. 12 teaches the device of claim 43, wherein the first and second cutting structures ([FCS]/[SCS]) are between the first (far left 63) and second memory regions (far right 63) that are adjacent to each other in a second direction (horizontal).
Re claim 45, FUJIKI, FIG. 12 teaches the device of claim 43, wherein each of the first and second memory regions includes: a plurality of electrodes (41) that are stacked on the substrate (10/32); and a vertical channel structure (62) that penetrates the plurality of electrodes and is connected to the substrate.
Re claim 46, FUJIKI, FIG. 12 teaches the device of claim 43, further comprising: a through contact region (78/79) between the first and second cutting structures, wherein the through contact (78) is disposed in the through contact region.
Re claim 47, FUJIKI, FIG. 12 teaches the device of wherein the substrate includes a dielectric pattern (79) disposed in the through contact region (78/79), and wherein the through contact (78) penetrates the dielectric pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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