DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23, 39-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 23, 39-40 recites the limitation "the hybrid bonds" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claims 24-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 24-25 do not positively recite any structural feature to further limit the structural recitation in the parent claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dabral (2019/0319626).
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As to claim 21, figure 31C, Dabral discloses:
21. (New) A device package comprising:a high bandwidth memory (HBM) chiplet 104; a system-on-chip (SoC) die 102; and an active bridge die hybrid 150 bonded to the HBM chiplet and the SoC die, the active bridge die comprising an HBM controller layer and a memory cache. See para [0044-0050]; [0063]
As to claim 22, figure 31C, Dabral discloses:
22. (New) The device package of claim 21, wherein the active bridge die 140 (fig 6) has a smaller size than the SoC die 102(fig 31C)/ (104, fig 6).
As to claim 23, figure 31C, Dabral discloses:
23. (New) The device package of claim 21, wherein the hybrid bonds (figure 6) provide an interface greater than 1024 bits.
As to claim 24, figure 31C, Dabral discloses:
24. (New) The device package of claim 23, wherein the interface greater than 1024 bits is a completer interface.
As to claim 25, figure 31C, Dabral discloses:
25. (New) The device package of claim 21, wherein a data path length between the active bridge die and the SoC die is up to one um.
As to claim 26, figure 31C, Dabral discloses:
26. (New) The device package of claim 21, wherein the HBM chiplet 104 is capable of not comprising an HBM controller layer.
As to claim 27, figure 31C, Dabral discloses:
27. (New) The device package of claim 21, wherein the SoC die 102 comprises one or more processing elements. [0044-0050]
As to claim 28, figure 31C, Dabral discloses:
28. (New) The device package of claim 27, wherein the active bridge die is disposed directly over the one or more processing elements.
As to claim 29, figure 31C, Dabral discloses:
29. (New) The device package of claim 27, wherein the one or more processing elements are proximate to the memory cache of the active bridge die 150. [0063]
As to claim 30, figure 31C, Dabral discloses:
30. (New) The device package of claim 21, wherein the active bridge die 150 provides level shifting between the SoC die 102 and the HBM chiplet 104.
As to claim 31, figure 31C, Dabral discloses:
31. (New) The device package of claim 21, wherein the memory cache of the active bridge die 150 buffers data passed between the HBM chiplet 104 and the SoC die 102.
As to claim 32, figure 31C, Dabral discloses:
32. (New) The device package of claim 21, wherein the active bridge die 150 comprises active circuitry capable of actively performing at least one further function.
As to claim 33, figure 31C, Dabral discloses:
33. (New) The device package of claim 32, wherein the at least one further function provides cache.
As to claim 34, figure 31C, Dabral discloses:
34. (New) The device package of claim 32, wherein the at least one further function capably provides re- clocking between the SoC die 102 and the HBM chiplet 104.
As to claim 35, figure 31C, Dabral discloses:
35. (New) The device package of claim 32, wherein the at least one further function capably provides clock gating between the SoC die and the HBM chiplet.
As to claim 36, figure 31C, Dabral discloses:
36. (New) The device package of claim 32, wherein the at least one further function capably provides voltage gating between the SoC die and the HBM chiplet.
As to claim 37, figure 31C, Dabral discloses:
37. (New) The device package of claim 32, wherein the at least one further function capably provides clock distribution between the SoC die and the HBM chiplet.
As to claim 38, figure 31C, Dabral discloses:
38. (New) The device package of claim 32, wherein the at least one further function capably provides physical (PHY) layer and controller functions for the SoC die and the HBM chiplet.
As to claim 39, figure 31C, Dabral discloses:
39. (New) The device package of claim 21, wherein the hybrid bonds are capable to pass native signals between the active bridge die and the SoC die.
As to claim 40, figure 31C, Dabral discloses:
40. (New) The device package of claim 21, wherein the hybrid bonds are capable to pass native signals between the active bridge die and the HBM chiplet.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liff (11335663) discloses a bridge die.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to (Vikki) Hoa B. Trinh whose telephone number is (571) 272-1719 and email is vikki.trinh@uspto.gov. The Examiner can normally be reached from Monday-Friday, 7:00 AM - 3:30 PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, Mr. Steven Gauthier, can be reached at (571) 270-0373. The office fax number is 571-273-8300.
To schedule an Examiner’s Interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
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Vikki Hoa Trinh /HOA B TRINH/Primary Examiner, Art Unit 2813
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