Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claim(s) 21-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
DETAILED ACTION
This action is responsive to application No. 18372947 filed on 09/26/2023.
Information Disclosure Statement
The information disclosure statement filed on 09/26/2023 has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the amended recitation “wherein the chiplet and the SoC die are embedded in an encapsulant that is disposed in a space between the chiplet and the SoC die” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-24, 26-29, 32-34 and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 20190319626 A1) in view of Lai (US 20170053897 A1).
Regarding independent claim 21, Dabral et al. teach a device package (fig. 31C, element 100 [0102]) comprising:
a chaplet (fig. 31C, element 102 [ 0052]);
a system-on-chip (SoC) die (fig. 31C, element 104, [0052]),
and an active bridge die (fig. 31C, element 150, [0102]) hybrid bonded [0045] to the chiplet and the SoC die, the active bridge die comprising a controller layer and a memory cache [0046] [0049] [0088].
Dabral et al. do not explicitly teach the chiplet and the SoC die are embedded in an encapsulant that is disposed in a space between the chiplet and the SoC die;
However, Lai et al. is a pertinent art which teaches a package in which two separate second level die (fig. 10, element 210 [057] [0059]) are hybrid bonded over a fist level die (fig. 10, element 110 [0056] [0059]) and the two second level die are encapsulated in a molding compound (fig. 10, element 240 [0057]) that fills the space between them. Lai et al. additionally teaches that the first level die may a bridging die in communication with two separate second level die [0059], and that the first level die may an active die such as a logic die or SoC die while the second level die may be memory die [0043] [0049].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the device package of Dabral such that the chiplet and SoC die are embedded in an encapsulant disposed in the space between the chiplet and the Soc die as taught by Lai. One of the ordinary skills in the art would have been motivated to do so because Lai et al. teach that the molding compound provide structural support during subsequent processing [0057] and because encapsulating semiconductor dies within a molding or encapsulating material is well known packaging techniques for providing protection to the dies while maintaining the position of the dies within the package to achieve predictable result.
Regarding claim 22, Dabral et al. tech a device package comprising, the active bridge die and SoC die.
Dabral et al. do not explicitly teach the active bridge die has a smaller size than the SoC die.
However, Fig 31C of Dabral et al. is a cross-sectional side view of the device package [0102]. Fig. 31C shows the active bridge die encapsulated below the SoC die, and shows the active bridge die is thinner than SoC die. The claim language does not say which dimension is compared. Under the broadest reasonable interpretation, “size” is not limited to lateral area and covers any dimension of the die, including thickness. Dabral et al. further state that this configuration “can facilitate a low z-height packaging configuration” [0103].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to make this active bridge die thinner and so smaller in size, than the Soc die. One of the ordinary skills in the art would have been motivated to do so because the active bridge die is stacked below the So0c die, so its thickness adds directly to the package height and Dabral et al. expressly seek a low z-height packaging configuration for this arrangement [0103].
Regarding claim 23, Dabral et al. teach a device package, further comprising hybrid bonds [0045] between the active bridge die and the chiplet and between the active bridge die and the SoC die.
Dabral et al. do not explicitly teach the hybrid bonds providing an interface greater than 1024 bits.
However, Dabral et al. teach that the joining technology may be a hybrid bonding as supporting very dense I/O, and CoW integration may use even denser hybrid bonding [0045], and that the die attachment process is selected to allow very large-scale integration (VLSI) and fine pitch I/O [0058]. Dabral et al. also teach that the interfacing bar increases the available periphery for chip-to-chip connection and is used for increase bandwidth of chip-to-chip communication [0044]. Also, number of bits in the interface is result effective variable because a wider interface carries more data per cycle across that connection and it is obvious to optimize result effective variable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to optimize the number of bits in the hybrid bonded interface between the chips of Dabral et al. One of the ordinary skills in the art would have been motivated to do so because Dabral et al. identifies hybrid bonding as the joining technology that supports very dense I/O, and a wider interface delivers the increased chip to chip bandwidth that Dabral et al. seek [0044]. Discovering the optimum values of a result-effective variable is ordinarily within the level of ordinary skill. See MPEP 2144.05(II0(B)
Regarding claim 24, Dabral et al. teach a device package further comprising the interface of hybrid bond between chips.
Dabral et al. do not explicitly teach the interface is a completer interface.
However, the claim limitations does not define “completer interface”. Under the broadest reasonable interpretation, a completer interface is an interface that receive a request from another device and returns the requested data or completion. Dabral et al. teach that the interfacing bar include local controllers compatible to the memory type and the physical interface (PHY) compatible with the memory [0046], and the memory bar may incorporate a PHY and a memory (e.g. DRAM) controller [0049]. A memory controller carried on the bar receives memory requests from the Soc die over the interface and returns the requested data, so the bar is the side that completes the transaction.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to provide the interface of Dabral et al. as a completer interface. One of the ordinary skills in the art would have been motivated to do so because Dabral et al. place the memory controller and PHY on the interfacing bar itself and having the bar receive and complete the memory transaction locally is what produces the increase chip-to-chip bandwidth and mitigated latency that Dabral et al. seek [0044] [0049].
Regarding claim 26, Dabral et al. teach a device package comprising, the chiplet does not comprise a controller layer [0049] [0052] [0087] [0088] [103].
Dabral et al. describe the chiplet only as a memory chip, and state that the term is inclusive of stacked memory dies and memory packages such as HBM and HMC [0052] [0087]. Dabral et al. place the controller on the active bridge die instead, the interfacing bar includes the local controller compatible to the memory type and the PHY [0046], the memory bar may incorporate the PHY and memory controller [0049] and the memory bar supports the “physical interface/controller with the logic die that requires space” [0088]. No controller layer is described on the chiplet.
Regarding claim 27, Dabral et al. teach a device package comprising, the SoC die comprises one or more processing elements [0045] [0046].
Regarding claim 28, Dabral et al. teach a device package comprising, the active bridge die is disposed directly over the one or more processing elements. (Dabral et al. discloses the claimed invention except for the precise location of processing element within the Soc chip. Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to place the processing elements within the portion of the SoC die that is overlapped by the active bride die, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70 C.C.P.A. 1950).
Regarding claim 29, Dabral et al. teach a device package, wherein the one or more processing elements and memory cache of the active bridge die [0046] [0088] [103]).
Dabral et al. do not explicitly teach one or more processing element are proximate to the memory cache of the active bridge die.
However, claim 29 does not state any distance, range of distance or reference point for “proximate”. The examiner therefore reads this broadly to mean near or close to, and under this reading the limitation is met by any two components that sit near one another inside the same device package. No particle spacing is required. Applying this reading fig. 31C of Dabral et al. shows the Soc dies mounted over the encapsulated active bridge die [0103] so the two dies sit one above the other inside the same package and every processing element of SoC die is near the memory cache of the active bridge die. Dabral et al. further teach “placing local processing elements (close to the memory)” on the memory bar [0088] and manage latency according to how far the memory sits from the logic chip [0049], which shows that Dabral et al. keep the processing elements and memory close to one another.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to place one or more processing element of the Soc die proximate to the memory cache of the active bridge die. One of the ordinary skills in the art would have been motivated to do so because Dabral et al. seek increased bandwidth of chip-to-chip communication with mitigated latency [0044] and shorter path between the processing element and the memory cache [0049].
Regarding claim 32, Dabral et al. teach a device package comprising, the active bridge die comprises active circuitry capable of actively performing at least one further function [0084] [0088].
Regarding claim 33, Dabral et al. teach a device package comprising, the at least one further function provides cache [0084] [0088].
Regarding claim 34, Dabral et al. teach a device package, wherein further functions are provided between the SoC die and the chiplet.
Dabral et al. do not explicitly teach re-clocking function between the SoC die and the chiplet.
However, Dabral et al. teach that the active components of the interfacing bar such as a de-serializer, a serializer and lanes couples to active devices such as repeater and flops [0073], and that an active component of the bar may be a simple repeater, a re-timer, or a more complex structure like cross-bar [0082], Dabral et al. state that many of the ideas described for co. A re-timer re-clock the data it forwards, that is its function.
Therefore, to the extent Dabral et al. do not teach re-clocking, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to provide the active bridge die with a re-clocking functions, One of the ordinary skill in the art would have been motivated to do so because Dabral’s bar already contains re-timer circuitry capable of performing it [0082] and because Dabral’s bar already contains the serializer and de serializer structure to achieve higher raw data rates [0074] while seeking increased bandwidth of chip-to-chip communication with mitigated latency. Applying a known technique to a known device ready for improvement to yield a predictable result is obvious. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP 2143(I)(D).
Regarding claim 36, Dabral et al. teach a device package comprising, the SoC die and the chiplet.
Dabral et al. do not explicitly teach voltage gating function between the SoC die and the chiplet.
However, Dabral et al. teach that the interfacing bar provides voltage shifting capability between the chips it couples [0049], and that a memory bar may provide level shifting capabilities as required [0088]. Dabral et al. further teach that short connection lengths achieved by the bar can lower the voltage requirement for power gain [0086]. Dabral therefore places voltage domain circuitry on the bridge die.
Therefore, to the extent Dabral’s voltage shifting is not read as voltage gating, it would have been obvious to one of the ordinary skills in the art before the effective filing date to gate supply voltage to the link circuitry on the active bridge die. One of the ordinary skills in the art would have been motivated to do so because Dabral er al. seek power optimization in these systems [0086], and gating the supply to inactive circuit blocks is well known and predictable means of reducing static and dynamic power in such an interface. Applying a known technique to a known device ready for improvement to yield a predicable result is obvious. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP 2143(I)(D).
Regarding claim 37, Dabral et al. disclose a device package, further functions are provided between the SoC die and the chiplet [0084] [0088].
Dabral et al. do not exclusively teach clock distribution function between the SoC die and the chiplet.
However, Dabral et al. teach that the interfacing bar carries a serializer, de-serializer, and plurality of lanes extending between them, and that the lane are couples to the active devices such as repeater and flops [0073]. Dabral et al use the serializer and de-serializer structure to achieve higher raw data rates [0074], and further states that many of the idea describes for communication bars are equally applicable to memory bars [0084].
Therefore, to the extent Dabral do not expressly recite clock distribution, it would have been obvious to one of the ordinary skills on the art before the effective filing date of the claimed invention to provide the active bridge die with a clock distribution functions between the SoC and the chiplet. One of the ordinary skills in the art would have been motivated to do so because Dabral’s bar already carries the clocked serializer and de-serializer circuitry capable of performing it [0073]., and because distributing the timing reference from the shared element is a predicable way to keep both ends of the links aligned at the higher raw data rates Dabral et al. seek [0074]. Applying a known technique to a known device ready for improvement to yield a predicable result is obvious. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP 2143(I)(D).
Regarding claim 38, Dabral et al. teach a device package comprising, the at least one further function provides physical (PHY) layer and controller functions for the SoC die, and the chiplet [0046] [0049] [0088].
Dabral et al. states that the interfacing bar may include local controllers compatible with the memory type, as well as a physical interface (PHY), including a PHY analog and a PHY digital controller, compatible with the memory [0046], and that the memory bar may incorporate a PHY and memory controller [0049]. And that the memory bar supports a physical interface (PHY)/controller with the logic die [0088]
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 20190319626 A1) in view of Lai et al. (US 20170053897 A1) and further in view of Delacruz (US 20180102251 A1).
Regarding claim 25, Dabral et al. modified by Lai teach a device package further comprising a data path between the active bridge die and the SoC die. (Fig 31C of Dabral shows the memory bar electrically coupled to the logic chip through the redistribution layer [0102].)
Dabral as modified by Lai do not exclusively teach a length of the data path being is up to one μm.
However, Delacruz is a pertinent art which teaches data path between chips or dies, a length of the data path [may be] up to one µm [0079].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the device package of Dabral et al. and Lai et al. so that the length of the data path between the active bridge die and SoC die is up to one µm as taught by Delacruz et al. Delacruz et all. Teaches that a shorter data path lowers power consumptions by reducing parasitic capacitance and by reducing the length of conductor in the circuit [0043] [0044]. And Dabral et al. seek power optimizations in these systems [0086].
Claim 30, 39 & 40 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 20190319626 A1) in view of Lai (US 20170053897 A1) further in view of Delacruz (US 20180102251 A1).
Regarding claim 30, Dabral et al. modified by Lai et al. do not explicitly teach a device package, wherein the active bridge die provides level shifting between the SoC die and the chiplet.
However, Delacruz et al. is a pertinent art which teaches a semiconductor die provides level shifting between dies [0028].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the device package of Dabral and Lai to include circuitry comprising level shifter in a chip or in an active bridge chip as taught by Delacruz. One of the ordinary skills in the art would have been motivated to do so as taught by Delacruz in order to translating digital signals from one voltage domain to another so that chips operating at different voltages able to communicate without errors.
Regarding claim 39, Dabral et al. as modified by Lai et al. teach a device package further comprising hybrid bonds between the active bridge die and the chiplet and the chiplet and between the active bridge die and the SoC die [0045].
Dabral as modified by Lai do not explicitly teach the hybrid bonds pass native signals between the active bridge die and the SoC die.
However, Delacruz et al. is a pertinent art which teaches direct bonding “may be provided by a hybrid bonding technique such as DBI technology [0028] [0040], and teaches that the native signal of the IP core of one die is passed directly to other dies via the directly bonded native interconnects” [0030].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the device package of Dabral et al and Lai et al. so that the hybrid bonds pass native signals between the active bridge die and the Soc die, as taught by Delacruz et al. One of the ordinary skills in the art would have been motivated to do so because Delacruz teaches that passing native signal over directly bonded native interconnects removes the standards interface and its hierarchy of data handling complexity [0030] [0081] and signal propagation speed [0043].
Regarding claim 40, Dabral et al. as modified by Lai et al. teach a device package further comprising hybrid bonds between the active bridge die and the chiplet and between the active bridge die and the SoC die [0045].
Dabral et al. as modified by Lai et al. do not explicitly teach the hybrid bonds pass native signals between the active bridge die and the chiplet.
However, Delacruz et al. is a pertinent art which teaches direct bonding “may be provided by a hybrid bonding technique such as DBI technology” [0028] [0040], and teaches that the native signal of the IP core of one die “is passed directly to other dies via the directly bonded native interconnects” [0030].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the device package of Dabral et al and Lai et al. so that the hybrid bonds pass native signals between the active bridge die and the chiplet as taught by Delacruz et al. One of the ordinary skills in the art would have been motivated to do so because Delacruz teaches that passing native signal over directly bonded native interconnects removes the standards interface and its hierarchy of data handling complexity [0030] [0081] and signal propagation speed [0043].
Claims 31 & 35 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 20190319626 A1) in view of Lai (US 20170053897 A1) further in view of Sato et al. (US 20180151247 A1).
Regarding claim 31, Dabral et al. modified by Lai et al. do not explicitly teach a device package, wherein the memory cache of the active bridge die buffers data passed between the chiplet and the SoC die.
However, Sato is a pertinent art which teaches memory cache of the chip buffers data passed between the chiplet [0036].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the device package of Dabral and Lai et al. include circuitry comprising data buffering functionality in a chip or a bridge die to buffers data passed between the chiplet and the SoC die as taught by Sato. One of the ordinary skills in the art would have been motivated to do so in order to improve temporarily store and manage data traffic, reducing communication latency and improving data transfer efficiency between interconnected chips.
Regarding claim 35, Dabral et al. modified by Lai et al. do not explicitly teach a device package comprising, wherein the at least one further function provides clock gating between the SoC die and the chiplet.
However, Sato is a pertinent art which teaches a function provides clock gating between chips [0036].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the device package of Dabral and Lai et al. to include a chip comprising a clock signal circuitry within a chip or a bridge die as taught by Sato et al. One of the ordinary skills in the art would have been motivated to do so in order to reduce dynamic power consumption by disabling the inactive circuit blocks utilizing the clock signal functionality.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
Prosecution Insights