DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0295924 A1) and further in view of Sakui et al. (US 5,818,75633).
Regarding claim 9, Lee teaches a sub word-line driver circuit, comprising:
a first set of word lines arranged in a vertical stack, each word line of the first set of word lines configured to access memory cells of a first set of memory cells (Fig. 3, wordlines WL1 to WLn in the first block BLK1);
a second set of word lines arranged in the vertical stack, each word line of the second set of word lines configured to access memory cells of a second set of memory cells (Fig. 3, wordlines WL1 to WLn in the second block BLK2);
a first set of digit lines, wherein each word line of the first set of word lines couples a memory cell of the first set of memory cells with a digit line of the first set of digit lines (BL11 to BL1m in the first block BLK1);
a second set of digit lines, wherein each word line of the second set of word lines couples a memory cell of the second set of memory cells with a digit line of the second set of digit lines (BL21 to BL2m in the second block BLK2), wherein the second set of digit lines are above and vertically aligned with the first set of digit lines (Fig. 4, The channel regions CH1 and CH2 are part of the digit lines which are vertically aligned with the each other. In addition, a portion of the first digit lines 16 and a portion of the second digit lines 26 are vertically aligned ), and
wherein the second set of digit lines are electrically disconnected from the first set of digit lines (Fig. 3, BL11 to BL1m and BL21 to BL2m are disconnected from each other).
Lee is silent in teaching a second set of word lines, communicatively coupled to the first set of word lines; and a first phase driver of a plurality of phase drivers associated with the first set of word lines wherein the first phase driver is a single transistor.
Sakui teaches a second set of word lines (Fig. 5,
W
L
0
j
t
o
W
L
31
j
) communicatively coupled to the first set of word lines (Fig. 5,
W
L
0
i
t
o
W
L
0
i
); and a first phase driver of a plurality of phase drivers associated with the first set of word lines wherein the first phase driver is a single transistor (a plurality of phase drivers T1i and T34i, wherein each phase driver is a single transistor).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use Sakui’s invention of using a common driver circuit for two sub arrays or sub blocks in order to reduce the circuitry which would help increase the density of the memory device.
Regarding claim 12, Sakui further teaches the sub word-line driver circuit of claim 11, wherein the first phase driver is disconnected to the second set of word lines (Driver for the signal Ti is disconnected from the second set of word lines Fig. 5,
W
L
0
j
t
o
W
L
31
j
).
Regarding claim 13, Sakui further teaches the sub word-line driver circuit of claim 12, comprising a second phase driver of the plurality of phase drivers associated with the second set of word lines (Fig. 5, driver connected to Tj).
Regarding claim 14, Sakui further teaches the sub word-line driver circuit of claim 13, wherein the second phase driver is disconnected to the first set of word lines (Driver for the signal Tj is disconnected from the first set of word lines).
Regarding claim 15, Sakui further teaches the sub word-line driver circuit of claim 9, further comprising a plurality of word line drivers coupled to the first set of word lines and the second set of word lines (Fig. 5, drivers connected to W0 to W31).
Regarding claim 16, Sakui further teaches the sub word-line driver circuit of claim 15, wherein each word line driver is coupled to a word line in the first set of word lines and a word line in the second set of word lines (W0 is coupled to word line WL0i in the first set and WL0j in the second set of word lines).
Regarding claim 17, Lee and Sakui further teach the sub word-line driver circuit of claim 9, wherein the first set of digit lines is disconnected from the second set of word lines and the second set of digit lines is disconnected from the first set of word lines (Fig. 3, first digit lines BL11 to BL1m in block BLK1 are disconnected from the second set of word lines in block BLK1 and second digit lines BL21 to BL2m in block BLK2 are disconnected from the first set of word lines in block BLK1).
Response to Arguments
Applicant's arguments filed 01/08/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues on page 7 “From Applicant's review, Sakui does not cure the deficiencies of Lee. Sakui appears to disclose a memory cell array with two blocks containing NAND memory cells, EEPROMs of the memory cells having a drain connected to a corresponding bit line and a source connected to a common source line. Sakui discloses the control gates of the EEPROMs are connected to common gate lines via "transfer transistors T2i-Tl 7i" (Sakui Col. 8 Line 62 - Col. 9 Line 14). In contrast, Applicant's claim 9 recites, "wherein the first phase driver is a single transistor."”
After reviewing Sakui, it appears Sakui still teaches the claimed invention. The transfer transistors T1i to T17i in Fig. 2 or the transfer transistor T2i to T33i function as a phase drivers. The transfer transistors will drive the word lines based on a first voltage (high voltage) applied to Ti and voltages applied to the common gate lines W0-W31. When the control line Ti has a low voltage, the word lines will be isolated and will be at a low level. Therefore, the transfer transistors T1i to T33i function as phase drivers which will drive the word lines based on the signal applied to Ti. In addition, the specification for the current invention describes the phase drivers to direct voltages to the word lines, see ¶0034. Sakui transfer transistors function to direct voltages to the word lines. Therefore, Sakui teaches phase drivers as recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824