DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-13 and 17-20 in the reply filed on 12/23/2025 is acknowledged. Furthermore, claim 16 is withdrawn as it is dependent on non-elected claim 14, and claims 21-24 were previously canceled by applicant.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). While KR10-2023-0004291 has support for the instant application; however, KR10-2022-0128055 does not have support for the instant application. As such, the instant application is entitled only to the foreign priority date of KR10-2023-0004291 that is January 11, 2023.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1:
a cell region in which a plurality of cells are arranged; and
a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises:
a plurality of first gate lines over a substrate;
a plurality of first patterns in a first wiring layer above the plurality of first gate lines;
a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate; and
a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction,
wherein each of the plurality of first vias comprises a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns (note bolded portion).
Claim 4:
wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns.
Claim 7:
wherein the peripheral region comprises: a plurality of second gate lines over the substrate; a plurality of fourth patterns extending in the first wiring layer above the plurality of second gate lines; a plurality of fifth patterns extending in the first horizontal direction in the backside wiring layer; and a plurality of second vias passing through the substrate in the vertical direction, wherein each of the plurality of second vias is connected to a respective one of the plurality of fourth patterns and a respective one of the plurality of fifth patterns.
Claim 11:
a cell region in which a plurality of cells are arranged; and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises: a plurality of first gate lines over a substrate; a plurality of first patterns extending in a first wiring layer above the plurality of first gate lines; and a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, wherein each of the plurality of second patterns is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction.
Claim 17:
a cell region in which a plurality of cells are arranged; and a peripheral region adjacent to the cell region and in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises: a plurality of first gate lines over a substrate; a plurality of first patterns extending in a first wiring layer above the plurality of first gate lines; a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, the plurality of second patterns being configured to receive a first supply voltage supplied to the plurality of cells; and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction and connected to a respective one of the plurality of first patterns and a respective one of the plurality of second patterns.
Claim 19:
wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns.
Claim 20:
wherein the cell region further comprises a plurality of fourth patterns extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 & 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a cell region in which a plurality of cells are arranged; and
a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises:
a plurality of first gate lines over a substrate;
a plurality of first patterns in a first wiring layer above the plurality of first gate lines;
a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate; and
a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction ,
wherein each of the plurality of first vias comprises a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns (note bolded portion).
The claim raises ambiguity as it is unclear how the above claim features are interrelated structurally as the limitations are not mappable to a single drawing. The Examiner suggests that applicants provide a single drawing where claim structural features are shown and mappable to the claim.
Claims 2-9 are rejected for being dependent on claim 1.
Claim 4 recites the limitation “wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns”. It is unclear what structural features refer to a plurality of third patterns… To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to a specific drawing.
Claim 7 recites the limitation “wherein the peripheral region comprises: a plurality of second gate lines over the substrate; a plurality of fourth patterns extending in the first wiring layer above the plurality of second gate lines; a plurality of fifth patterns extending in the first horizontal direction in the backside wiring layer; and a plurality of second vias passing through the substrate in the vertical direction, wherein each of the plurality of second vias is connected to a respective one of the plurality of fourth patterns and a respective one of the plurality of fifth patterns.” The claim raises ambiguity as it is unclear how the above claim features are interrelated structurally as the limitations are not mappable to a single drawing. The Examiner suggests that applicants provide a single drawing where claim structural features are shown and mappable to the claim.
Claim 11 recites the limitation “a cell region in which a plurality of cells are arranged; and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises: a plurality of first gate lines over a substrate; a plurality of first patterns extending in a first wiring layer above the plurality of first gate lines; and a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, wherein each of the plurality of second patterns is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction. The claim raises ambiguity as it is unclear how the above claim features are interrelated structurally as the limitations are not mappable to a single drawing. The Examiner suggests that applicants provide a single drawing where claim structural features are shown and mappable to the claim.
Claims 12-13 are rejected for being dependent on claim 11.
Claim 17 recites the limitation “a cell region in which a plurality of cells are arranged; and a peripheral region adjacent to the cell region and in which a circuit configured to control the plurality of cells is arranged, wherein the cell region comprises: a plurality of first gate lines over a substrate; a plurality of first patterns extending in a first wiring layer above the plurality of first gate lines; a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, the plurality of second patterns being configured to receive a first supply voltage supplied to the plurality of cells; and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction and connected to a respective one of the plurality of first patterns and a respective one of the plurality of second patterns”. The claim raises ambiguity as it is unclear how the above claim features are interrelated structurally as the limitations are not mappable to a single drawing. The Examiner suggests that applicants provide a single drawing where claim structural features are shown and mappable to the claim.
Claim 19 recites the limitation “wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns”. It is unclear what structural features refer to a plurality of third patterns… To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to a specific drawing.
Claim 20 recites the limitation “wherein the cell region further comprises a plurality of fourth patterns extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells”. It is unclear what structural features refer to a plurality of fourth patterns… To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to a specific drawing.
Claims 18-20 are also rejected for being dependent on claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
As best understood, claims 1-13 & 17-20 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by AKAMINE et al (JP 2022-148921) (US Pub. 2024/0099032 is provided for translation purposes).
Regarding claim 1, AKAMINE teaches an integrated circuit comprising:
a cell region in which a plurality of cells (note cell array 511) are arranged (Fig. 2-3 and note annotations in Fig. 3 below); and
a peripheral region in which a circuit 531 configured to control the plurality of cells is arranged (Fig. 2-3 and note annotations in Fig. 3 below), wherein the cell region comprises:
a plurality of first gate lines over a substrate (see annotation in Fig. 3 below);
a plurality of first patterns 525 in a first wiring layer above the plurality of first gate lines (see Fig. 3 below);
a plurality of second patterns (SGS and/or WL) extending in a first horizontal direction in a backside wiring layer under the substrate (see Fig. 3 below); and
a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction (see Fig. 3 below),
wherein each of the plurality of first vias comprises a top surface connected to a respective one of the plurality of first patterns 525 and a bottom surface connected to a respective one of the plurality of second patterns (Fig. 1-3, see Fig, 3 below).
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Regarding claim 2, AKAMINE teaches the integrated circuit of claim 1, wherein the plurality of second patterns (SGS and/or WL) comprise at least one second pattern configured to receive a first supply voltage provided to the plurality of cells (Fig. 1-3, the plurality of second patterns is/are capable of receiving a first supply voltage for the plurality of cells 511).
Regarding claim 3, AKAMINE teaches the integrated circuit of claim 2, wherein the at least one second pattern extends to the peripheral region in the first horizontal direction (Fig. 1-3).
Regarding claim 4, as best understood, AKAMINE teaches the integrated circuit of claim 2, wherein the cell region further comprises a plurality of third patterns (e.g. some portions of WL and/or SGS) extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns (Fig. 1-3) .
Regarding claim 5, as best understood, AKAMINE teaches the integrated circuit of claim 2, wherein the plurality of second patterns further comprise at least one second pattern configured to receive a second supply voltage provided to the plurality of cells, the at least one second pattern extending to the peripheral region (Fig. 1-3, the plurality of second patterns is/are capable of said functionality).
Regarding claim 6, as best understood, AKAMINE teaches the integrated circuit of claim 5, wherein the peripheral region further comprises a peripheral circuit (e.g. another transistor 531) configured to generate the second supply voltage from an external supply voltage provided from outside the peripheral region (Fig. 1-3, the peripheral circuit as shown in Fig. 2-3 is capable of said functionality).
Regarding claim 7, as best understood, AKAMINE teaches the integrated circuit of claim 1, wherein the peripheral region comprises: a plurality of second gate lines over the substrate; a plurality of fourth patterns (543 in peripheral circuit, see Fig. 3 above) extending in the first wiring layer above the plurality of second gate lines; a plurality of fifth patterns 545 extending in the first horizontal direction in the backside wiring layer; and a plurality of second vias 544 passing through the substrate in the vertical direction, wherein each of the plurality of second vias is connected to a respective one of the plurality of fourth patterns 543 and a respective one of the plurality of fifth patterns 545 (Fig. 3).
Regarding claim 8, as best understood, AKAMINE teaches the integrated circuit of claim 7, wherein the plurality of fifth patterns comprise at least one fifth pattern configured to receive an external supply voltage provided from outside the peripheral region (the plurality of fifth pattern is capable of said functionality, Fig. 3).
Regarding claim 9, AKAMINE teaches the integrated circuit of claim 1, wherein each of the plurality of second patterns is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction (Fig. 3, the plurality of second pattern is capable of said functionality).
Regarding claim 10, AKAMINE teaches the integrated circuit of claim 9, wherein the plurality of second patterns extend in the peripheral region, and wherein the peripheral region comprises a plurality of third vias passing through the substrate in the vertical direction and connected to the plurality of second patterns (see Fig. 3 above and note the dotted line that illustrates that the components extend into the peripheral region).
Regarding claim 11, AKAMINE teaches an integrated circuit comprising:
a cell region 511 in which a plurality of cells are arranged (Fig. 2-3 and note annotations in Fig. 3 above); and
a peripheral region in which a circuit 531 configured to control the plurality of cells is arranged (Fig. 2-3 and note annotations in Fig. 3 above), wherein the cell region comprises:
a plurality of first gate lines over a substrate (see annotation in Fig. 3 above);
a plurality of first patterns 525 extending in a first wiring layer above the plurality of first gate lines; and
a plurality of second patterns (SGS and/or WL) extending in a first horizontal direction in a backside wiring layer under the substrate (see Fig. 3 above),
wherein each of the plurality of second patterns is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction (the plurality of second cells is capable of receiving a control signal, see annotation in Fig. 3 above).
Regarding claim 12, AKAMINE teaches the integrated circuit of claim 11, wherein the cell region further comprises a plurality of vias, each of the plurality of vias passing through the substrate in a vertical direction and connected to a respective one of the plurality of second patterns (see Fig. 3 above).
Regarding claim 13, AKAMINE teaches the integrated circuit of claim 12, wherein each of the plurality of vias pass through the substrate in the vertical direction in a region of the cell region between the plurality of cells (see Fig. 3 above).
Regarding claim 17, AKAMINE teaches an integrated circuit comprising:
a cell region in which a plurality of cells 511 are arranged (Fig. 2-3 and note annotations in Fig. 3 above); and
a peripheral region adjacent to the cell region and in which a circuit 531 configured to control the plurality of cells is arranged (Fig. 2-3 and note annotations in Fig. 3 above), wherein the cell region comprises:
a plurality of first gate lines over a substrate (see Fig. 3 above);
a plurality of first patterns 525 extending in a first wiring layer above the plurality of first gate lines (see Fig. 3 above);
a plurality of second patterns (SGS and/or WL) extending in a first horizontal direction in a backside wiring layer under the substrate, the plurality of second patterns being configured to receive a first supply voltage supplied to the plurality of cells (the plurality of second patterns are capable of receiving a first power supply, see Fig. 3 above); and
a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction and connected to a respective one of the plurality of first patterns and a respective one of the plurality of second patterns (see Fig. 3 above).
Regarding claim 18, AKAMINE teaches the integrated circuit of claim 17, wherein the plurality of second patterns extend to the peripheral region in the first horizontal direction (Fig. 3).
Regarding claim 19, AKAMINE teaches the integrated circuit of claim 17, wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns.
Regarding claim 20, AKAMINE teaches the integrated circuit of claim 17, wherein the cell region further comprises a plurality of fourth patterns extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818