DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-6, 9-13 and 17-20 in the reply filed on 12/23/2025 is acknowledged. Furthermore, claim 16 is withdrawn as it is dependent on non-elected claim 14, and claims 21-24 were previously canceled by applicant.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). While KR10-2023-0004291 has support for the instant application; however, KR10-2022-0128055 does not have support for the instant application. As such, the instant application is entitled only to the foreign priority date of KR10-2023-0004291 that is January 11, 2023.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 4:
wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns.
Claim 19:
wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns.
Claim 20:
wherein the cell region further comprises a plurality of fourth patterns extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 & 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns”. It is unclear what structural features refer to a plurality of third patterns… and how they are structurally positioned to claim 1 limitations. To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to Fig. 1 to which claim 1 is mappable.
Claim 19 recites the limitation “wherein the cell region further comprises a plurality of third patterns extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns”. It is unclear what structural features refer to a plurality of third patterns… and how they are structurally positioned to claim 1 limitations. To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to Fig. 1 to which claim 1 is mappable.
Claim 20 recites the limitation “wherein the cell region further comprises a plurality of fourth patterns extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells”. It is unclear what structural features refer to a plurality of fourth patterns… and how they are structurally positioned to claim 1 limitations. To help remove the ambiguity, the Examiner suggests that applicants map said claim feature to Fig. 1 to which claim 1 is mappable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-13 & 17-20 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by KIM et al (10-2020-0139181) (US Pub. 2022/0130737 is provided for translation purposes).
Regarding claim 1, AKAMINE teaches an integrated circuit comprising:
a cell region in which a plurality of cells 140 are arranged (Fig. 1-4 and note annotations in Fig. 4 below, KIM teaches the presence of cells in area 140, Para [0030]); and
a peripheral region 122 in which a circuit configured to control the plurality of cells is arranged (Fig. 1-4, it is understood that peripheral regions comprises circuits), wherein the cell region comprises:
a plurality of first gate lines over a substrate 130 (see annotation in Fig. 4 below);
a plurality of first patterns 331 in a first wiring layer above the plurality of first gate lines (see Fig. 4 below);
a plurality of second patterns 235 extending in a first horizontal direction in a backside wiring layer under the substrate (see Fig. 3 below); and
a plurality of first vias 141, each of the plurality of first vias passing through the substrate 130 in a vertical direction (see Fig. 4 below),
wherein each of the plurality of first vias 141 comprises a top surface connected to a respective one of the plurality of first patterns 331 and a bottom surface connected to a respective one of the plurality of second patterns 235 (Fig. 1 & Fig. 4, it is understood that the semiconductor comprises a plurality of first patterns, a plurality of second patterns, a plurality of gate lines and a plurality of first vias).
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Regarding claim 2, KIM teaches the integrated circuit of claim 1, wherein the plurality of second patterns 235 comprise at least one second pattern configured to receive a first supply voltage provided to the plurality of cells (Fig. 1-4, the plurality of second patterns is/are capable of receiving a first supply voltage for the plurality of cells).
Regarding claim 3, KIM teaches the integrated circuit of claim 2, wherein the at least one second pattern 235 extends to the peripheral region in the first horizontal direction (Fig. 1-4).
Regarding claim 4, as best understood, KIM teaches the integrated circuit of claim 2, wherein the cell region further comprises a plurality of third patterns (e.g. 234 and/or 233) extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns 235 (Fig. 1-4) .
Regarding claim 5, KIM teaches the integrated circuit of claim 2, wherein the plurality of second patterns 235 further comprise at least one second pattern 235 configured to receive a second supply voltage provided to the plurality of cells, the at least one second pattern extending to the peripheral region (Fig. 1-4, the plurality of second patterns is/are capable of said functionality).
Regarding claim 6, KIM teaches the integrated circuit of claim 5, wherein the peripheral region further comprises a peripheral circuit (it is understood that the peripheral circuits in the peripheral region) configured to generate the second supply voltage from an external supply voltage provided from outside the peripheral region (Fig. 1-4, the peripheral circuit is capable of said functionality).
Regarding claim 9, KIM teaches the integrated circuit of claim 1, wherein each of the plurality of second patterns 235 is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction (Fig. 1-4, the plurality of second pattern is capable of said functionality).
Regarding claim 10, KIM teaches the integrated circuit of claim 9, wherein the plurality of second patterns 235 extend in the peripheral region, and wherein the peripheral region comprises a plurality of third vias (the other vias 141) passing through the substrate 130 in the vertical direction and connected to the plurality of second patterns (see Fig. 1-4).
Regarding claim 11, KIM teaches an integrated circuit comprising:
a cell region in which a plurality of cells 140 are arranged (Fig. 1-4, KIM teaches the presence of cells in area 140, Para [0030]); and
a peripheral region 122 in which a circuit configured to control the plurality of cells is arranged (Fig. 1-4, it is understood that peripheral regions comprises circuits), wherein the cell region comprises:
a plurality of first gate lines over a substrate 130 (see annotation in Fig. 4 above);
a plurality of first patterns 331 in a first wiring layer above the plurality of first gate lines (see Fig. 4 above); and
a plurality of second patterns 235 extending in a first horizontal direction in a backside wiring layer under the substrate (see Fig. 4 above);
wherein each of the plurality of second patterns 235 is configured to receive a control signal provided commonly to cells, among the plurality of cells, in a row extending in the first horizontal direction (the plurality of second cells is capable of receiving a control signal, see annotation in Fig. 4 above).
Regarding claim 12, KIM teaches the integrated circuit of claim 11, wherein the cell region further comprises a plurality of vias 141, each of the plurality of vias passing through the substrate 130 in a vertical direction and connected to a respective one of the plurality of second patterns 235 (see Fig. 4 above).
Regarding claim 13, KIM teaches the integrated circuit of claim 12, wherein each of the plurality of vias 141 pass through the substrate in the vertical direction in a region of the cell region between the plurality of cells (Fig. 1-4).
Regarding claim 17, AKAMINE teaches an integrated circuit comprising:
a cell region in which a plurality of cells 140 are arranged (Fig. 1-4 and note annotations in Fig. 4 above, KIM teaches the presence of cells in area 140, Para [0030]); and
a peripheral region 122 adjacent to the cell region in which a circuit configured to control the plurality of cells is arranged (Fig. 1-4, it is understood that peripheral regions comprises circuits), wherein the cell region comprises:
a plurality of first gate lines over a substrate 130 (see annotation in Fig. 4 above);
a plurality of first patterns 331 extending in a first wiring layer above the plurality of first gate lines (see Fig. 4 above);
a plurality of second patterns 235 extending in a first horizontal direction in a backside wiring layer under the substrate 130 (see Fig. 3 below); the plurality of second patterns 235 being configured to receive a first supply voltage supplied to the plurality of cells (the plurality of second patterns are capable of receiving a first power supply, see Fig. 4 above); and
a plurality of first vias 141, each of the plurality of first vias 141 passing through the substrate 130 in a vertical direction and connected to a respective one of the plurality of first patterns 331 and a respective one of the plurality of second patterns 235 (Fig. 1 & Fig. 4, it is understood that the semiconductor comprises a plurality of first patterns, a plurality of second patterns, a plurality of gate lines and a plurality of first vias).
Regarding claim 18, KIM teaches the integrated circuit of claim 17, wherein the plurality of second patterns extend to the peripheral region in the first horizontal direction (Fig. 1-4).
Regarding claim 19, as best understood, KIM teaches the integrated circuit of claim 17, wherein the cell region further comprises a plurality of third patterns (234 and/or 233) extending in the backside wiring layer in a second horizontal direction perpendicular to the first horizontal direction, and wherein the plurality of third patterns are connected to the plurality of second patterns 235 (Fig. 1-4).
Regarding claim 20, as best understood, KIM teaches the integrated circuit of claim 17, wherein the cell region further comprises a plurality of fourth patterns (e.g. 232 and/or 231) extending in the backside wiring layer in the first horizontal direction, the plurality of fourth patterns being configured to receive a second supply voltage provided to the plurality of cells (Fig. 1-4).
Response to Arguments
With respect to the priority, the Examiner maintains that KR10-2022-0128055 (hereafter ‘055) does not have support for the instant application as the content of ‘055 submitted on 11/09/2023 is completely different from the disclosure of the instant application. Therefore, the instant application is not entitled to the priority date of ‘055.
The Examiner maintains the drawing objection to claims 4 and 19-20 as applicant has merely alluded to Fig. 8A & 7C in the Remarks without showing the claim structural relationship between said drawings and Fig.1 to which independent claim 1 is mappable. In other words, mapping of claims 4 & 19-20 limitations to Fig. 1 will help resolve this ambiguity.
With respect to the prior art rejection, applicants’ arguments have been considered but are moot in light of new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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