Prosecution Insights
Last updated: October 02, 2026
Application No. 18/374,063

CIRCUIT DESIGN AND MANUFACTURING HOTSPOT ROOT CAUSE EXTRACTION

Non-Final OA §102
Filed
Sep 28, 2023
Priority
May 16, 2023 — provisional 63/502,478
Examiner
PARIHAR, SUCHIN
Art Unit
Tech Center
Assignee
Siemens Aktiengesellschaft
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
1033 granted / 1177 resolved
+27.8% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
1184
Total Applications
across all art units

Statute-Specific Performance

§101
17.4%
-22.6% vs TC avg
§103
15.5%
-24.5% vs TC avg
§102
56.2%
+16.2% vs TC avg
§112
7.9%
-32.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1177 resolved cases

Office Action

§102
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. This Non-Final office action is in response to application 18/374,063, application filed on 09/28/2023. Claims 1-20 are currently pending in this application. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 4. Claim(s) 1-4, 9-12 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Zafar et al. (US PG Pub No. 2007/0288219). 5. With respect to independent claims 1, 9 and 17, Zafar teaches: receiving a layout design (receiving design/circuit data such as wafer and inspection data, image data, para 351; see utilizing design data, Abstract; see design circuit data space, para 17; see receiving design data stored in a data structure, design layout data, para 19, 21-25), the layout design having layout regions of interest (see determining different regions surrounding defects, para 37; see inspected regions of the design/wafer, para 130; see defects/regions of interest from received design data, para 48; see patterns/features of interest, para 57; see defects of interest vs. defects not of interest, para 135), the layout regions of interest comprising a plurality of hotspot layout regions (hot-spots discovered, patterns of interest compared to hot spot information, para 357; hot spot identification vs comparing in contrast - identifying defects not of interest, para 191); determining feature values for a plurality of design/process-related features for each of the layout regions of interest (see feature values, density of features, para 71, 106; zonal/spatial signature analysis providing parameters/values for features, para 190-195); determining population ratios for feature value ranges for each of the plurality of design/process-related features based on a number of layout regions of interest having feature values within each of the feature value ranges (population of defects, random defects vs systemic defects; see ratio of number of defects binned – population, para 65, 128-129); determining hotspot feature repeater values, a hotspot feature repeater value for a feature value range for a design/process-related feature being associated with a number of hotspot layout regions in the feature value range (see defect repeater analysis, para 37; see hot spot identification in layout regions with repeater analysis, para 188-190); performing a root cause analysis to determine, for each of the plurality of hotspot layout regions, one or more design/process-related features that are most likely causes of the each of the plurality of hotspot layout regions based on the population ratios and the hotspot feature repeater values (root cause for group of defects, para 60; see likelihood of evaluation of process conditions, root cause analysis, para 440, 463, 474); and storing information of the one or more design/process-related features for each of the plurality of hotspot layout regions (storing groups of portions of design data in storage that are a result of determining defects and hotspots of design data and evaluating likelihood of defects, para 45-48). 6. With respect to claims 2 and 10, Zafar teaches: identifying hotspot layout regions in another layout design or additional hotspot layout regions in the layout design based on the information of the one or more design/process-related features for each of the plurality of hotspot layout regions (identifying additional areas of inspection data to determine defects and hot spots based on design space, para 20-25; determining additional wafers for inspection data, para 41; see additional one or more wafers due for inspection of hot spots and defects related to design process, para 98-101); and adjusting the another layout design or the layout design based on the identified hotspot layout regions or the identified additional hotspot layout regions (adjusting geometries of layout features based on source of defects, common patterns of defects identified in additional layouts or wafers, para 373-375). 7. With respect to claims 3, 11 and 18, Zafar teaches: adjusting a manufacturing process based on the information of the one or more design/process-related features for each of the plurality of hotspot layout regions (adjusting processes to eliminate defects while ruling out defects first that do not have an impact on design, para 13, see applying corrections to design and design data, para 51, 209, 223). 8. With respect to claim 4, 12 and 19, Zafar teaches: wherein the root cause analysis comprises a decision chain process for each of the plurality of hotspot layout regions (see decision regarding design data for manufacturing process, para 312, one or more actionable decisions of defects, para 423). Allowable Subject Matter 9. Dependent claim 5 and similarly recited dependent claims 13 and 20 (and claims 6-8 and 14-16, which depend therefrom, respectively) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 10. With respect to dependent claims 5, 13 and 20, the prior art made of record fails to teach the combination of steps recited in independent claim 5, including the following particular combination of steps as recited in claim 5 and similarly recited in claims 13 and 20, as follows: determining another design/process-related feature that is a next most likely cause of the selected hotspot layout region based on the statistic model, updated population ratios, and updated hotspot feature repeater values, the updated population ratios and the updated hotspot feature repeater values derived based on the identified layout regions of interest; and repeating the identifying and the determining another design/process-related feature by replacing the initial design/process-related feature with the another design/process-related feature until a predetermined condition is met. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Sep 28, 2023
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1177 resolved cases by this examiner. Grant probability derived from career allowance rate.

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