Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to the amendment to independent claims 1 and 11, the previously-applied rejection under 35 U.S.C. § 103 is withdrawn. However, upon further consideration, a new ground of rejection is made under 35 U.S.C. § 103 as being unpatentable over Darby in view of Chen and in further view of Ben-Shlomo et al. (Full citation in PTO-892 form).
Response to Arguments
In response to the amendment to independent claims 1 and 11, the previously-applied rejection under 35 U.S.C. § 103 is withdrawn. However, upon further consideration, a new ground of rejection is made under 35 U.S.C. § 103 as being unpatentable over Darby in view of Chen and in further view of Ben-Shlomo et al. (Full citation in PTO-892 form).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Darby et al. (US PG Pub 20220284568, hereinafter “Darby”) in view of Chen et al. (US PG Pub 20220067898, hereinafter “Chen”) and in further view of Ben-Shlomo et al. (US PG Pub 20230306580, hereinafter “Ben-Shlomo”).
Regarding claim 1, Darby discloses a method comprising: receiving, at a processor, a target image of a workpiece that includes a die (paras. 0037-0039, disclosing the imaging device relaying an image to a processor, and paras. 0079-0081, wherein the SEM/optical images are explicitly recited to contain a die);
receiving, at the processor, a design file that includes a design of the die (para. 0056, reciting a GDSII file, which is a graphic display system design file containing the IC architecture);
generating, using the processor, a reference optical image of the die based on the design file with a deep convolutional neural network for image-to-image translation (para. 0038, wherein collected optical images are used to train a model to generate synthetic representations of components of devices under test given the format, requirements, and examples of GDSII files, wherein the model is a deep convolutional mapping and inference model (MIM) directed to image-to-image translation); and
subtracting the reference optical image from the target image using the processor thereby generating a difference image (para. 0076, “[f]or example, simple subtraction between the target design and the synthetic representation can be performed to detect deviations between the synthetic and target designs”, wherein these difference images can be used for defect detection as an embodiment of observing deviations);
Specifically, Darby discloses a method and system for inspecting IC devices, wherein a deep convolutional network is trained on real and synthetic optical images for image-to-image translation, directed to generating reference images of die components for difference comparisons to a target image for anomaly/defect detection.
Darby does not explicitly disclose wherein the image of the workpiece includes a die with a plurality of chips
or disclose:
generating, using the processor, during the runtime a runtime care area mask for the die based on the design file that includes the design of the die;
applying, using the processor, the runtime care area mask against the difference image thereby generating a masked difference image;
and applying, using the processor, a threshold against the masked difference image thereby generating a binarized defective image.
However, Chen explicitly discloses wherein the image of the workpiece includes a die with a plurality of chips (para. 0058, "multiple repeating units… dies", containing chips),
and further discloses:
generating, using the processor, during the runtime a runtime care area mask for the die based on the design file that includes the design of the die (paras. 0021 and 0070-0082, wherein Chen discloses care areas, the generation of a runtime context map complete with mask information to generate regional maps related to the care areas, wherein these care areas may be extracted for inspection based on the determined design from the GDS file);
applying, using the processor, the runtime care area mask against the difference image thereby generating a masked difference image that excludes parts of the difference image from inspection (para. 0084-0085, wherein the RTCM may be applied to a modified test image. Although Chen discloses wherein the RTCM is applied to a modified test image prior to the image subtraction, the RTCM data itself is generated from a design file of the die, and is based on locations on the chip, which would be the same on both the modified test image as well as the difference image. Therefore, the same masked difference image with the same care areas identified would be produced. Furthermore, paras. 0019 and 0088-0090, wherein nuisance filtering is disclosed to exclude regions having known or observed noise or containing artifacts from observation);
and applying, using the processor, a threshold against the masked difference image thereby generating a binarized defective image (para. 0085, wherein a further threshold is applied to the masked difference image, and wherein the “binary” output of the threshold would be “defect” if the pixel value exceeds a threshold, or “non-defect” if the pixel value did not exceed the threshold).
Specifically, Chen discloses a wafer inspection and defect detection method, comprising acquiring a reference image, removing random defects and signatures from the reference image, fitting the reference image to a design grid to create a golden grid image of the wafer die pattern, and saving the golden grid image, aligning a test image to the golden grid image, and performing defect detection including, in certain embodiments, median pixel gray level, thresholding, or machine learning adjacent methods. Therefore, both Darby and Chen disclose IC die-directed inspection methods specifically geared towards detection of defects as a result of comparing collected images to design/golden grid images using registration and difference-based methods. Thus, it would have been obvious for one having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the run time care area masking, mask difference image, and thresholding of Chen within the method of Darby as a use of known techniques to known devices to yield the predictable improvement of a more accurate defect detection method within specific components of integrated circuits; specifically, the inclusion of the runtime context map, targeted care area masks within the difference image, and thresholding would allow for a higher degree of specificity in inspecting particular components for defects within the workflow of Darby.
Although both Darby and Chen utilize reference images for the defect detection process, the combination of Darby in view of Chen fails to disclose wherein the reference optical image is generated during runtime, or explicitly disclose the color mapping based on thresholding of defective areas.
However, Ben-Shlomo discloses wherein the reference optical image is generated during runtime (para. 0102, “A runtime image (e.g., a FP image as described above) representative of an inspection area of the semiconductor specimen can be obtained (302) (e.g., by the examination tool 120) during runtime examination of the specimen”), and wherein a color of the pixels in the binarized defective image is selected based on the threshold (para. 0111, “In some embodiments, the examination application is a defect detection application. The label data acquired in such cases can be informative of whether a defect candidate from a list of defect candidates presented in a reference area is a defect of interest (DOI), or nuisance. For instance, the label data can be provided, e.g., in the form of bounding boxes of the DOIs, or in the form of a binary image in which only pixels belonging to DOIs get a value of “1”, and non-defective pixels get a value of “0” etc. A cost function used during training of the ML can be based on detection accuracy/capture rate, and, optionally, also based on a penalty for misdetection and over-detections.”).
Specifically, Ben-Shlomo discloses a method and system of runtime-specific examination of a semiconductor specimen to ensure robustness to SNR variations. Thus, Ben-Shlomo, like Darby and Chen, discloses a method and system of semiconductor inspection using a trained machine learning model and runtime context of test images of test specimens. Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have utilized the runtime-specific reference image generation and explicit color thresholding of Ben-Shlomo within the method and system of Darby modified by Chen as the application of a known technique to a known device ready for improvement to yield the predictable result of a more streamlined examination procedure, limiting the need for processes in advance of inference and clearer visualization.
Claim 11 is rejected, mutatis mutandis, for reasoning similar to claim 1 above. Furthermore, Chen explicitly discloses:
a light source that generates a beam of light (para. 0026 and fig. 1, with respect to the illumination subsystem and light source 16);
a stage configured to hold a workpiece in a path of the beam of light, wherein the workpiece includes a die with a plurality of chips (para. 0032 and fig. 1 for specimen/inspection die 14 and stage 22, and para. 0058 for the die with the plurality of chips);
a detector configured to receive the beam of light reflected form the workpiece (para. 0033 and fig. 1, for detectors 28 and 34);
and a processor in electronic communication with the detector, wherein the processor is configured to [perform the additional limitation of] generating a target image of the workpiece based on information from the detector (para. 0036 for the computer subsystem, a component of which is a processor, wherein both are connected electronically, and para. 0047 for image generation). Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the disclosures of Darby and Chen and Ben-Shlomo according to the rationale of claim 1.
Regarding claims 6 and 14, Darby and Chen disclose and Ben-Shlomo all limitations of claims 1 and 11, respectively. Darby further discloses wherein the design file is a graphic design system file (para. 0056, wherein the files are graphic design system II (GDSII) files).
Regarding claims 7 and 15, Darby and Chen and Ben-Shlomo disclose all limitations of claims 1 and 11, respectively. Chen further discloses aligning the target image and the reference optical image prior to the subtracting (para. 0085, wherein the alignment and orientation of the design or grid mask and the test image is performed prior to the subtraction and thresholding for the defect detection process). Thus, it would have been obvious for one having ordinary skill in the art prior to the effective filing date of the claimed invention to have utilized the pre-subtraction alignment of the reference and target images within the method of Darby modified by Chen and Ben-Shlomo according to the rationale of claim 1
Regarding claims 8 and 16, Darby and Chen and Ben-Shlomo disclose all limitations of claims 1 and 11, respectively. Chen further discloses extracting, using the processor, a care area image from the target image using the runtime care area mask (paras. 0070-0074, wherein care areas are areas on a workpiece to be segmented and specifically examined, and wherein the care areas as disclosed by Chen are defined by the golden grid image and subsequently identified on the target image, creating segments on this new “test” image; in addition, the RTCM-defined masks and care areas are determined from the design files). Thus, it would have been obvious for one having ordinary skill in the art prior to the effective filing date of the claimed invention to have extracted and utilized a care area image from the runtime care area mask as disclosed by Chen within the method of Darby modified by Chen and Ben-Shlomo according to the rationale of claim 1.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Darby and Chen and Ben-Shlomo in further view of Meyers et al. (US PG Pub 20180138133, hereafter referred to as Meyers).
Regarding claims 2 and 12, Darby and Chen and Ben-Shlomo disclose all limitations of claim 1 and 11, respectively.
Although Darby and Chen and Ben-Shlomo disclose a plurality of chips on a die, Darby and Chen and Ben-Shlomo do not disclose wherein one of the chips is a system in package device.
However, Meyers discloses a system in package (SiP) device, specifically the manufacture of a packaged integrated circuit utilizing multiple stacked dies (paras. 0017-0022). Specifically, Meyers discloses a workpiece to be manufactured involving the use of multiple dies stacked into a package. Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have applied the method and system of Darby modified by Chen and Ben-Shlomo to the system-in-package device disclosed by Meyers as the application of a known technique to improve a similar device; specifically, the method and system of Darby and Chen and Ben-Shlomo applied to the SiP device of Meyers would yield the predictable result of robust defect detection on systems in package during the manufacturing process.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Darby and Chen and Ben-Shlomo in further view of MacNaughton et al. (US PG Pub 20130310966, hereafter referred to as MacNaughton).
Regarding claim 3, Darby and Chen and Ben-Shlomo disclose all limitations of claim 1.
Although Darby and Chen and Ben-Shlomo disclose a plurality of chips on a die, Darby and Chen and Ben-Shlomo do not disclose wherein the die includes a film frame carrier (FFC).
However, MacNaughton discloses wherein a die includes a film frame carrier (para. 0047, wherein FFCs are included as elements which wafers are mounted upon, and wherein quality assurance and defect detection are performed on dies including FFCs). Specifically, MacNaughton discloses a method of substrate analysis for detecting errors post-processing of dies. Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have applied the method and system of Darby modified by Chen and Ben-Shlomo to the FFC-associated dies disclosed by MacNaughton as the application of a known technique to improve a similar device; specifically, the method and system of Darby and Chen and Ben-Shlomo applied to the FFC device of MacNaughton would yield the predictable result of robust defect detection on FFC-carried dies during the manufacturing process.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Darby and Chen and Ben-Shlomo in further view of Mandal et al. (US PG Pub 20180350684, hereafter referred to as Mandal).
Regarding claim 4, Darby and Chen and Ben-Shlomo disclose all limitations of claim 1.
Although Darby and Chen and Ben-Shlomo disclose a plurality of chips on a die, Darby and Chen and Ben-Shlomo do not disclose wherein the die includes a 3D integrated circuit (3D IC).
However, Mandal discloses a die including a 3D IC (paras. 0018-0019, wherein the 3D IC package consists of a plurality of stacked dies with interposers). Specifically, Mandal discloses a manufacturing process of a 3D integrated circuit comprising stacked dies with particularly-oriented interposers acting as connectors. Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have applied the method and system of Darby modified by Chen and Ben-Shlomo to the 3D IC disclosed by Mandal as the application of a known technique to improve a similar device; specifically, the method and system of Darby and Chen and Ben-Shlomo applied to the 3D IC device of Mandal would yield the predictable result of robust defect detection on 3D IC during the manufacturing process (the defect detection specifically being disclosed by Mandal as a step in the process in para. 0019).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Darby and Chen and Ben-Shlomo in further view of Mailhe et al. (US PG Pub 20220292742, hereafter referred to as Mailhe).
Regarding claims 5 and 13, Darby and Chen and Ben-Shlomo disclose all limitations of claims 1 and 11, respectively, Darby further discloses the usage of a deep learning convolutional neural network within the mapping and inference model utilized for inspection of the integrated circuits (paras. 0025 and 0080).
Darby and Chen and Ben-Shlomo do not disclose wherein the deep learning convolutional neural network is a CycleGAN.
However, Mailhe discloses a CycleGAN for mask definition and separation within an image-based anomaly detection method (paras. 0034 and 0037-0041, wherein the CycleGAN comprises a segmentation network which can segment objects of interest having been trained on real and synthetic image data). Specifically, Mailhe discloses a method of object annotation and synthetic image generation (through translation) for future use in anomaly detection for diagnosis. Therefore, Darby and Chen and Ben-Shlomo and Mailhe all disclose methods of anomaly detection using deep algorithmic methods trained on a combination of real and synthetic image data for defect/abnormality “diagnosis”. Thus, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to have utilized the CycleGAN of Mailhe as a substitution well-known to one having ordinary skill in the art within the method of Darby modified by Chen and Ben-Shlomo.
Conclusion
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHAN TEJAS MUKUNDHAN whose telephone number is (571)272-2368. The examiner can normally be reached Monday - Friday 9AM - 6PM.
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/ROHAN TEJAS MUKUNDHAN/Examiner, Art Unit 2663
/GREGORY A MORSE/Supervisory Patent Examiner, Art Unit 2698
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