DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-16 and 20-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected groups II and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/30/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Applicant set forth a polymer with a specific polishing rate however there is no guidance as to the specifics of the polishing technique. The polish rate depends on multiple things including specifics of the material being polished. The polish method and materials being used for CMP it will depend on Velocity of particles and pressure of the particles as well as pH. For Pad polishing it would depend on the specifics of the pad and the rpm pressure and wear life on the pad. Thus, the without specifics of the polishing method the claim is indefinite since the metes and bounds cannot be determined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen 11,239,225 cited on IDs.
a. As to claim 1, Chen teaches A semiconductor package, comprising: a first chip including (item 200) a first substrate (item 202 figure 1b), a first wiring layer on the first substrate (BP2), and through-electrodes (TSV) passing through the first substrate and connected to the first wiring layer (connected to BP2 via 210 and BV2 : In some embodiments, the second bonding metal features include second bonding vias BV2 electrically connected to the second top metal features 210a of the second interconnect structure 206 and second bonding pads BP2 electrically connected to the second bonding vias BV2 columns 5 and 6), the through-electrodes protruding from a lower surface of the first chip to have protruding portions (see figure 1G the TSV protrude into 220); a double gap-fill layer covering a side surface and the lower surface of the first chip (items 220 BS and/or F-1and or F2), the double gap-fill layer covering the protruding portions of the through-electrodes (item 220) and having a double layer structure (see 220 and BS being separate layers); a second chip on the first chip (item 100 figure 1A) and the double gap-fill layer (see figure 2A item 100 is on BS F-1 F-2), the second chip including a second wiring layer (BP1 figure 1A) and a second substrate on the second wiring layer (item 102) , and the second chip being hybrid bonded to the first chip (column 6: After the alignment is achieved, the first bonding structure BS1 and the second bonding structure BS2 are bonded together by a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.); and at least one bump on the lower surface of the first chip and connected to a corresponding one of the through-electrodes (308 or 312).
b. As to claim 8, Chen teaches a redistribution layer is positioned on a lower surface of the double gap-fill layer, and the bump is connected to one of the through-electrodes through the redistribution layer (302).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Huang (20190103375).
a. As to claims 2-5 Chen teaches wherein: the lower gap-fill layer covers the lower surface (item 220) of the first chip and the protruding portions of the through-electrodes (item 220), and the upper gap-fill layer covers at least a portion of the side surface of the first chip, the upper gap-fill layer being in contact with the second wiring layer (BLD1 is in contact with BS).
Chen does not teach wherein the double gap-fill layer includes a lower gap-fill layer and an upper gap-fill layer, the double gap- fill layer including an organic-inorganic composite material.
Huang teaches the gap fill and the under fill maybe resin or polymer with silica filler paragraphs 26 and 27 items 32 and 46.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide at least the upper gap fill as a resin and silica fillers in the resin, the silica fillers having various sizes and the lower gap-fill layer includes a polymer with silica to form an organic-inorganic composite material.
One would have been so motivated for the desired dielectric properties and thermal conductivity overall hardness of the device.
As to the polishing rate under specific processing conditions the material can have a R/R 5 k^/min or greater.
b. As to claim 6, Chen does not explicitly teach the first chip has a thickness of about 30 microns to about 40 microns ,the lower gap-fill layer has a thickness of about 5 microns to about 10 microns, and the upper gap-fill layer has a thickness of about 10 microns to about 30 microns. It is noted that the upper gap fill could reasonably considered to have to different thicknesses.
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The office will take the position that the second thickness it the thickness since it is along the laminate direction which is traditionally used to define thickness.
Applicant teaches no unexpected results for specifics of the measurements. Chips were known to have thickness of 30 to 40 microns further having dielectrics having thickness in a laminate direction were known 10 microns along the laminate direction.
Thus, it would have been obvious to one of ordinary skill in the art to provide the chip to be about 30 microns thick and the gap fill 220 and BS to be about 10 microns to provide conventional size for the known and expected result for those size including dielectric protection passivation devices to be integrated in the chip.
It is noted even though the second thickness is used the first thickness would also read on the claim since the height of BS and the Chip are the same So they would both be about 30 microns. Even at 40 microns one could interpret to be about 30 microns.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen 225 in view of Chen 11,024,605.
a. As to claim 7, Chen 225 teaches wherein: an area of the first chip in a first horizontal plane is smaller than an area of the second chip in a second horizontal plane (figure 1H or 2A).
Chen 225 does not teach and a side surface of the double gap-fill layer is substantially coplanar with a side surface of the second chip.
Chen 605 teaches a first chip 40/50 a second chip item 90 a multi-layer gap fills along the side wall of the first chip and on the wiring of a second chip 82 and through posts in the upper gap fill connected to the same RDL as the first chip (item 86). Chen 605 further teaches sidewall of the “upper” gap fill is co-planar with the sidewall of the second chip figure 18 of Chen 605.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the upper gap fill to be co-planar with the sidewall of the second chip or to reduce the size of the second chip to fit only one chip in Chen 225. For the desired modes of operation and desired components to be integrated and to reduce the lateral space used by the chips.
b. As to claim 9, Chen 225 does not teach further comprising a through-post adjacent to the side surface of the first chip, the through-post passing through the double gap-fill layer and connecting the redistribution layer to the second wiring layer.
Chen 605 teaches a first chip 40/50 a second chip item 90 a multi-layer gap fills along the side wall of the first chip and on the wiring of a second chip 82 and through posts in the upper gap fill connected to the same RDL as the first chip (item 86).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide a through-post adjacent to the side surface of the first chip, the through-post passing through the double gap-fill layer and connecting the redistribution layer to the second wiring layer to provide direct access to the second chip.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable Chen 225 in view of Chen 605 and Huang.
a. As to claims 17 and 18 , Chen 225 teaches A semiconductor package, comprising: a first chip including (item 200) a first substrate (item 202 figure 1b), a first wiring layer on the first substrate (BP2), and through-electrodes (TSV) passing through the first substrate and connected to the first wiring layer (connected to BP2 via 210 and BV2 : In some embodiments, the second bonding metal features include second bonding vias BV2 electrically connected to the second top metal features 210a of the second interconnect structure 206 and second bonding pads BP2 electrically connected to the second bonding vias BV2 columns 5 and 6), the through-electrodes protruding from a lower surface of the first chip to have protruding portions (see figure 1G the TSV protrude into 220); a double gap-fill layer covering a side surface and the lower surface of the first chip (items 220 BS and/or F-1and or F2), the double gap-fill layer covering the protruding portions of the through-electrodes (item 220) and having a double layer structure (see 220 and BS being separate layers); a second chip on the first chip (item 100 figure 1A) and the double gap-fill layer (see figure 2A item 100 is on BS F-1 F-2), the second chip including a second wiring layer (BP1 figure 1A) and a second substrate on the second wiring layer (item 102) , and the second chip being hybrid bonded to the first chip (column 6: After the alignment is achieved, the first bonding structure BS1 and the second bonding structure BS2 are bonded together by a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.);
a redistribution layer is positioned on a lower surface of the double gap-fill layer (item 302), and bump is connected to one of the through-electrodes through the redistribution layer (308 or 312). Chen teaches wherein an area of the first chip in a first horizontal plane is smaller than an area of the second chip in a second horizontal plane (figure 1H and 2A relative sizes)
Chen 225 does not teach the double gap-fill layer including an organic-inorganic composite material or and wherein the double gap-fill layer covers an area corresponding to a difference (sic corresponding will be interpreted as being the difference) between the area of the first chip in the first horizontal plane and the area of the second chip in the second horizontal plane.
Huang teaches the gap fill and the under fill maybe resin or polymer with silica filler paragraphs 26 and 27 items 32 and 46.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide at least the upper gap fill as a resin and silica fillers in the resin, the silica fillers having various sizes and the lower gap-fill layer includes a polymer with silica to form an organic-inorganic composite material.
One would have been so motivated for the desired dielectric properties and thermal conductivity overall hardness of the device. If the claim is to be interpreted to mean that there must be a plurality of different sizes this is inherent since the silica particles will vary in size due to process limitations of providing Silca in a resin or polymer.
As to the polishing rate under specific processing conditions the material can have a R/R 5 k^/min or greater.
Chen 605 teaches a first chip 40/50 a second chip item 90 a multi-layer gap fills along the side wall of the first chip and on the wiring of a second chip 82 and through posts in the upper gap fill connected to the same RDL as the first chip (item 86). Chen 605 further teaches sidewall of the “upper” gap fill is co-planar with the sidewall of the second chip figure 18 of Chen 605.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the upper gap fill to be co-planar with the sidewall of the second chip or to reduce the size of the second chip to fit only one chip in Chen 225. For the desired modes of operation and desired components to be integrated and to reduce the lateral space used by the chips. Thus, the upper gap fill would be the difference between the area of the first chip in the first horizontal plane and the area of the second chip in the second horizontal plane.
b. As to claim 19 Chen 225 does not teach further comprising a through-post adjacent to the side surface of the first chip, the through-post passing through the double gap-fill layer and connecting the redistribution layer to the second wiring layer.
Chen 605 teaches a first chip 40/50 a second chip item 90 a multi-layer gap fills along the side wall of the first chip and on the wiring of a second chip 82 and through posts in the upper gap fill connected to the same RDL as the first chip (item 86).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide a through-post adjacent to the side surface of the first chip, the through-post passing through the double gap-fill layer and connecting the redistribution layer to the second wiring layer to provide direct access to the second chip.
Conclusion
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/ Primary Examiner, Art Unit 2896