DETAILED ACTION
DETAILED ACTION
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-13, drawn to a packaging structure, classified in H01L25/0562.
II. Claims 14-20, drawn to a packaging method, classified in H01L21/4853.
The inventions are independent or distinct, each from the other because:
Inventions II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the process as claimed can be used to make another and materially different product such the product can be made without a carrier.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with Mr. Hefing Su on December 10, 2025 a provisional election was made without traverse to prosecute the invention of I, claims 1-13. Affirmation of this election must be made by applicant in replying to this Office action. Claims 14-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ho et al. (Ho, US 2024/0120316 A1).
Regarding claim 1, Ho shows a packaging structure ( FIG. 10), comprising: a plurality of device chips (chip 210 in FIG. 2 and [0031]), where a device chip (chip 210) of the plurality of device chips (chip 210) comprises a first side (top surface of chip 210) and a second side ( bottom surface of chip 210) facing away from the first side (see FIG. 2), and a first interconnection structure(interconnect structure 206 and [0029]) being formed on the first side of the device chip (chip 210); a first packaging layer (molding layer 112 in FIG. 4 and [0033]), covering a side wall of the device chip (chip 210) and filling between device chips of the plurality of device chips (see FIG. 4), the first packaging layer exposing (see FIG. 4 with respect to FIG. 5) the first side of the device chip (chip 210); an interconnect chip (RDL 122), bonded to the device chip (chip 210) and the first packaging layer ( molding layer 112), a second interconnection structure (interconnect ball 136) being formed on the interconnect chip ( element 122), the second interconnection structure being exposed from a surface of the interconnect chip (chip 210), and the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip (See FIG. 10); and a second packaging layer (layer 132 in FIG. 9), located on the first packaging layer (molding layer 112) and covering the interconnect chip ( chip 210).
Regarding claim 2, Ho shows a packaging structure ( FIG. 10), comprising, wherein the first side (top surface of chip 210) is a front side of the device chip (chip 210), and the second side is a back side of the device chip (see FIG. 9).
Regarding claim 3, Ho shows a packaging structure ( FIG. 10), comprising, wherein a plurality of first interconnection structures (interconnect structure 206) being formed in the device chip (device chip 210).
Regarding claim 4, Ho shows a packaging structure ( FIG. 10), comprising, wherein the packaging structure further comprises: a via interconnection structure (recess between element 132 in FIG. 10 ), running through the second packaging layer (layer 132) and electrically connected to the device chip (chip 210).
Regarding claim 5, Ho shows a packaging structure ( FIG. 10), comprising, wherein another first interconnection structure (RDL 206) is formed on the device chip (chip 210), and a via interconnection ( solder ball 136) structure runs through the second packaging layer on a top of the another first interconnection structure exposed by the interconnect chip and contacts the another first interconnection structure (see Fig. 10).
Regarding claim 6, Ho shows a packaging structure ( FIG. 10), comprising, wherein the packaging structure further comprises: a connection layer (solder ball 136), located in the second packaging layer (layer 132) on a top of the via interconnection structure and extending along a direction parallel to the second packaging layer; and a conductive bump, located on the connection layer (see Fig. 10).
Regarding claim 7, Ho shows a packaging structure ( FIG. 10), comprising, wherein the packaging structure further comprises: a redistribution structure (RDL 122), located on the second packaging layer and the via interconnection structure; and a conductive bump, located on the redistribution structure (see FIG. 10).
Regarding claim 8, Ho shows a packaging structure ( FIG. 10), comprising, wherein the redistribution structure comprises one or more redistribution layers (RDL 122).
Regarding claim 9, Ho shows a packaging structure ( FIG. 10), comprising, wherein a first dielectric layer (molding layer 112 in FIG. 8) is formed on the first side of the device chip, a first top layer line is formed in the first dielectric layer, and the first interconnection structure runs through the first dielectric layer above the first top layer line and contacts the first top layer line (see FIG. 8).
Regarding claim 10, Ho shows a packaging structure ( FIG. 10), comprising, wherein a first dielectric layer (molding layer 210) is formed on the first side of the device chip (chip 210), a first pad is formed in the first dielectric layer, and the first interconnection structure is located in the first dielectric layer on a top of the first pad (see FIG. 8).
Regarding claim 11, Ho shows a packaging structure ( FIG. 10), comprising, wherein a second dielectric layer is formed on the interconnect chip, a second top layer line is formed in the second dielectric layer, and the second interconnection structure runs through the second dielectric layer above the second top layer line and contacts the second top layer line (see FIG. 8).
Regarding claim 12, Ho shows a packaging structure ( FIG. 10), comprising, wherein a second dielectric layer is formed on the interconnect chip, a second pad is formed in the second dielectric layer, and the second interconnection structure is located in the second dielectric layer on a top of the second (see FIG. 8).
Regarding claim 13, Ho shows a packaging structure ( FIG. 10), comprising, wherein a material of the first interconnection structure comprises at least one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and a material of the second interconnection structure comprises at least one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium ([0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893