DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Claims 1- 7 , drawn to a packaging structure , classified in CPC H10W 90/00. II. Claim 8-17 , drawn to a process of making a packaging structure , classified in CPC H10P 72/74. The inventions are independent or distinct, each from the other because Inventions II and I FILLIN "Enter the appropriate information" \* MERGEFORMAT are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case, the product as claimed can be made by another and materially different process; i.e. instead of “providing a carrier” and “attaching plurality of device chips to the carrier” (as required by claim 8), the structure excluding the plurality of chips, it’s interconnections and first packaging layer may be formed after using a carrier to form the remainder of the structure including the second packaging layer, vias and redistribution layer (s). Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: a). the inventions have acquired a separate status in the art in view of their different classification; and b). the inventions require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries). Applicant is advised that the reply to this requirement to be complete must include ( i ) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention . The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined. In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01. Applicant is reminded that upon the cancellation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17( i ). During a telephone conversation with Hefeng Su (Registration No. L1283) on 3/12/2026 a provisional election was made without traverse to prosecute the invention of Group I, claims 1- 7 . Affirmation of this election must be made by applicant in replying to this Office action. Claims 8-17 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: PACKAGING STRUCTURE COMPRISING REDISTRIBUTION STRUCTURE CONNECTED TO INTERCONNECT CHIP AND PACKAGING METHOD FOR THE SAME Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the recitation of claim 5 that requires “the via interconnection structure running through the first packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “the via interconnection structure running through the first packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps”. However, claim 5 depends from claims 1 and 4. It is not clear how this possible in the structure shown in Figures. The specification explains that micro bumps (150, see para 51 of specification & Fig. 1) are connecting only to first redistribution structure (130, see para 32 of specification & Fig. 1) , and as the micro bumps (150) are entirely outside of first packaging layer (110, see para 32 of specification & Fig. 1) , the vias would not reach the “first packaging layer” or would be “running through the first packaging layer” for “contacting the micro bumps”. For the purposes of this office action, it will be assumed that the recitation “the via interconnection structure running through the first packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps” of claim 5 is equivalent of “the via interconnection structure running through the first second packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps ” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20230245991), hereinafter Chen, in view of Lin ( CN 114334946 A ), hereinafter Lin. Lin (US 20230187363 A1) is being used as a full English translation of the Lin ( CN 114334946 A ) reference, and all references to figures and paragraph numbers of Lin are to Lin (US 20230187363 A1) . Note that Lin ( CN 114334946 A ) corresponds to Chinese Application No. CN 202111496539 A Regarding claims 1 and 7, Chen (US 20230245991) (refer to Figure 10; also see Figures 2-9 for intermediate structure details) teaches a packaging structure (100, described as "integrated circuit package 100," in para 22), comprising: a plurality of device chips (50, described as "one or more integrated circuit dies 50" in para 22, best seen in Figure 2), where a device chip of the plurality of device chips comprises a first side (side of “active surface”; i.e. side facing upward in orientation of Figure 10 – see para 16) and a second side (side of “inactive surface” that is “facing downward” in orientation of Figure 10; see para 16) facing away from the first side, and an interconnection structure (56, described as "die connectors 56" in para 15) is formed on the first side of the device chip (50); a first packaging layer (108, described as "encapsulant 108" in para 25), covering a side wall of the device chip (50) and filling between (see Figure 10) device chips of the plurality of device chips (50), the first packaging layer (108) exposing the first side (side of 50 that is farthest from 142 - see Figure 10) of the device chip (50); an intermediate layer (110) located on the first packaging layer (108) and the device chip (50); an interconnect chip (140, described as "interconnection die 140" in para 45); and a second packaging layer (154, described as "encapsulant 154" in para 49), located on the intermediate layer (110) and covering (best seen in Figure 10) the interconnect chip (140). Although Chen teaches redistribution structures comprising one or more redistribution layers (para 50), Chen does not teach that the intermediate layer includes “a first redistribution structure” such that “the first redistribution structure” is “electrically connected to the interconnection structure of the device chip” and that the interconnect chip (140) is bonded to “the first redistribution structure, the interconnect chip being electrically connected to the first redistribution structure” and the second packaging layer (154) is located “on the first redistribution structure”. Lin (refer to Figure 1) teaches a similar packaging structure (100) comprising a plurality of device chips (121, described as "chip 121" in para 83; two such 121 are shown in Figure 1) comprising an interconnection structure (i.e. flip-chip bond of 121, described as "device package 121 is flip-bonded above the first redistribution stack layer 130" in para 83), a first packaging layer (122, described as "second plastic packaging layer 122" in para 83) and an interconnect chip (1133, described as "first chip 1133" in para 75) that serves to connect to the plurality of device chips, an intermediate layer (130, described as "first redistribution stack layer 130" in para 59) located on the first packaging layer (122) and the device chip (121), a second packaging layer (112, described as "first plastic packaging layer 112" in para 68) wherein : the intermediate layer (130) includes a first redistribution structure (para 59 describes 130 as "first redistribution stack layer 130") such that the first redistribution structure (130) is electrically connected to (para 83; also see para 77) the interconnection structure (as described above) of the device chip (121) and that the interconnect chip (1133) is bonded to the first redistribution structure (130), the interconnect chip (1133) being electrically connected (para 77; also see para 83) to the first redistribution structure (130) and the second packaging layer (112) is located on the first redistribution structure (130). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Chen to replace the intermediate layer of Chen with the intermediate layer (130) taught by Lin, which includes the first redistribution structure, thus resulting in a structure where the intermediate layer includes “a first redistribution structure” such that “the first redistribution structure” is “electrically connected to the interconnection structure of the device chip” and that the interconnect chip is bonded to “the first redistribution structure, the interconnect chip being electrically connected to the first redistribution structure” and the second packaging layer is located “on the first redistribution structure”, wherein the first redistribution structure comprises (as required by claim 7) one or more redistribution layers. The ordinary artisan would have been motivated to modify Chen for at least the purpose of including an additional redistribution layer structure with at least one redistribution layer for connections made to interconnection structure of the device chip for enhanced connectivity and greater flexibility in routing signals, especially for devices with large number of input/output connections. Regarding claim 2, Chen (refer to Figure 10; also see Figures 2-9 for intermediate structure details) teaches the packaging structure according to claim 1, wherein the first side (i.e. side of “active surface”; i.e. side facing upward in orientation of Figure 10 – see para 16) is a front side (i.e. side of active surface, as explained above) of the device chip , and the second side (side of “inactive surface” that is “facing downward” in orientation of Figure 10; see para 16) is a back side (i.e. side of inactive surface, as explained above) of the device chip (50). Regarding claim 3, Chen (refer to Figure 10; also see Figures 2-9 for intermediate structure details), as modified above in view of Lin above so that the intermediate layer (110) is a first redistribution structure , teaches the packaging structure further comprises: micro bumps (150, described as “micro bumps” in para 47) located between the interconnect chip (140) and the first redistribution structure (110, as modified for claim 1). Regarding claims 4-5, Chen (refer to Figure 10; also see Figures 2-9 for intermediate structure details), as modified above in view of Lin above so that the intermediate layer (110) is a first redistribution structure , teaches the the packaging structure further comprises (as recited in claim 4): a via interconnection structure (comprising 116, described as "through vias 116." in para 28), running through the second packaging layer (154) and electrically connected to the first redistribution structure (as modified for claim 1); and further (as recited in claim 5) micro bumps (150, described as “micro bumps” in para 47), located between the interconnect chip (140) and the first redistribution structure (110, as modified for claim 1), the micro bumps (150) being further located on the first redistribution structure exposed by the interconnect chip (140), but does not show that the via interconnection structure (116) is “running through the first packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps” (also see 35 USC, 112, 2 nd paragraph rejection above). Lin teaches that via interconnection structure may comprise vias (1131, described as "conductive pillars 1131" in para 75) such that they may connect to components in a first packaging layer (122, described as "second plastic packaging layer 122" in para 83) and the interconnection structure comprising the vias (1131) may extend to electrically connect to components in the first packaging layer. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Chen so that the via interconnection structure (116) runs through additional packaging layers such as first packaging layer to connect to specific components; i.e. via interconnection structure (116) is “running through the first packaging layer on tops of the micro bumps exposed by the interconnect chip and contacting the micro bumps”. The ordinary artisan would have been motivated to modify Chen for at least the purpose of using the via interconnection structure to run through additional packaging layers as required to make contact with additional circuit components, as may be required by circuit design. Regarding claim 6, Chen (refer to Figure 10; also see Figures 2-9 for intermediate structure details) teaches the packaging structure according to claim 4, wherein the packaging structure further comprises: a second redistribution structure (170, described as "redistribution structure 170" in para 50), located on the second packaging layer (154) and the via interconnection structure (comprising 116); and a conductive bump (178, described as "conductive connectors 178" that may be "bumps" -see para 55), located on (best seen in Figure 10) the second redistribution structure (170). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (US 20200176397) Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT AJAY ARORA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8347 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9 AM - 5 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Drew Richards can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712721736 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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