DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to Claims 22, 24, and 27 – 29 addressing the rejections under 35 U.S.C. 112(b) in the reply—filed 19 March 2026—are acknowledged. These rejections have been overcome by the amendments of said claims, and the associated rejections are withdrawn.
Applicant’s arguments and amendments in the aforementioned reply regarding the rejection of the claims under 35 U.S.C. 103 are acknowledged and have been fully considered but are not found persuasive.
On pages 11 – 12 of the aforementioned reply, Applicant argues the prior art of record does not teach the limitations of amended Claim 19 and supports this argument with a non-limiting interpretation of the prior art of record, which does not satisfy the limitations of amended Claim 19. The Examiner respectfully disagrees with Applicant’s conclusion, as the Examiner is not limited to Applicant’s non-limiting interpretation and provides a different non-limiting interpretation of the prior art of record, as seen in the new rejection of amended Claim 19 below, which does satisfy the limitations of amended Claim 19.
For the sake of clarity of record, the Examiner’s interpretation is not provided here, as the Examiner’s interpretation regards annotated figures and context provided in the prior art rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22—and any claims dependent thereon—are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 22,
Lin. 3 recites the limitation “a first gate metal layer”. However, this limitation is unclear in light of the instant specification, as the instant specification discloses only one “gate metal layer” element, and this element was claimed in Claim 1, upon which this claim depends.
For the purposes of examination, this limitation will be interpreted as “the gate metal layer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 – 20 & 22 – 30 are rejected under 35 U.S.C. 103 as being unpatentable over HO (US 20120061813 A1) in view of CHEN (US 20110037120 A1).
Examiner’s Note
In addition to the original figures, consider the annotated figure of CHEN below for the following prior art rejection.
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Regarding Independent Claim 19,
HO discloses:
A distributed drive package (Fig. 3) comprising:
a first transistor device (Fig. 3 & 10: 22; Par. 47 – 49)
…
a gate controller integrated circuit (Fig. 3 & 4: 40; Par. 43) including
a first gate driver output node (Fig. 3: 2 of the 4 terminals where 40 connects to 134 via a 51; Par. 43);
and a first gate conductive redistribution material (Fig. 10: 222; Par. 49)
conductively coupling…to the first gate driver output node (Fig. 3 & 10: 222 of 22 conductively couples to 134 via a 51s, and 134 conductively couples to the first gate driver output node via other 51s)
However, HO does not disclose:
The first transistor device
having two or more first gate vias
on a first top edge portion of the first transistor device
electrically connecting a first gate electrode material;
and the first gate conductive redistribution material
conductively coupling the first gate electrode material of the first transistor device…through the two or more first gate vias;
wherein the first transistor device includes
a first insulating layer,
a gate metal layer, and
a second insulating layer,
wherein the first insulating layer covers the top of a substrate composition over a gate contact region,
wherein the gate metal layer is sandwiched between the first insulating layer and the second insulating layer,
wherein the first insulating layer is sandwiched between the first gate conductive redistribution material and the gate metal layer,
wherein the first insulating layer includes one or more conductive vias that provide electrical connection between the first gate conductive redistribution material and the gate metal layer,
wherein the second insulating layer includes one or more conductive vias that provide electrical connection between the gate metal layer and one or more gate runners in the substrate composition.
Although, for a similar first transistor device, CHEN discloses:
A first transistor device
(Fig. 1A: 100; Par. 22)
having two or more first gate vias
(Fig. 1A: 112s in GCR1, each corresponding to Fig. 33LL’: CVIA/3375)
on a first top edge portion of the first transistor device (100)
(Fig. 1A: portion of 100 corresponding to GCR1.)
electrically connecting a first gate electrode material
(Fig. 33LL’: CVIA/3375 electrically connects to the material of which 3374 is comprised: polysilicon; Par. 62. That is, polysilicon is construed to be the “first gate electrode material”, but 3374 is not construed to be the “first gate electrode”.);
and a first gate conductive redistribution material
(Fig. 1A: 114 corresponding to Fig. 33LL’: 3378; Par. 22 & 62)
conductively coupling the first gate electrode material (polysilicon) of the first transistor device (100)…through the two or more first gate vias (CVIA/3375)
wherein the first transistor device (100) includes
a first insulating layer (Fig. 33LL’: 3384/3382),
a gate metal layer (Fig. 33LL’: 3376), and
(Under a broad but reasonable interpretation, a “gate metal layer” may be any “metal layer” associated with the “gate”. As such, 3376—which may be tungsten, Par. 62—is construed to be the “gate metal layer”.)
a second insulating layer (Fig. 33LL’: 3373),
wherein the first insulating layer (3384/3382) covers the top of a substrate composition (Fig. 33LL’: COMP) over a gate contact region (Fig. 1A: GCR1),
wherein the gate metal layer (3376) is sandwiched between the first insulating layer (3384/3382) and the second insulating layer (3373), (As seen in Fig. 33LL’, 3376 is sandwiched along LOR1 between the endpoints of LOR1, which correspond to portions of 3384/3382 and 3373.)
wherein the first insulating layer (3384/3382) is sandwiched between the first gate conductive redistribution material (3378) and the gate metal layer (3376),
(As seen in Fig. 33LL’, 3384/3382 is sandwiched along LOR2 between the endpoints of LOR2, which correspond to portions of 3378 and 3376.)
wherein the first insulating layer (3384/3382) includes one or more conductive vias (CVIA of CVIA/3375) that provide electrical connection between the first gate conductive redistribution material (3378) and the gate metal layer (3376),
wherein the second insulating layer (3373) includes one or more conductive vias (3375 of CVIA/3375)
(Under a broad but reasonable interpretation, a “conductive via” may be any hole or opening filled with a conductive material. As 3375 is a hole in 3374—as seen in Fig. 33LL’—and is filled with polycide—Par. 62—3375 may be construed as a conductive via. Further, 3375 is contained within layer 3373. Therefore, 3373 includes 3375.)
that provide electrical connection between the gate metal layer (3376) and one or more gate runners (Fig. 33LL’: 3374, which comprise polysilicon, Par. 62, and thus comprise the “first gate electrode material”. However, 3374 are not construed to be the “first gate electrode/s”) in the substrate composition (COMP).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first transistor device of HO Fig. 10: 22 with that of CHEN Fig. 1A: 100, as these inventions are from the same field of endeavor. Further still, while HO Par. 47 and CHEN Par. 22 both disclose their respective first transistor devices to be MOSFETs, HO focuses on a packaging of its MOSFET, neglecting the details of its MOSFET structure. As such, it would have been obvious to one of ordinary skill in the art to search the prior art for the details of an acceptable MOSFET structure, which CHEN provides. Additionally, CHEN Par. 21 asserts a number of advantages to its particular MOSFET structure.
Regarding Claim 20,
HO further discloses:
The distributed drive package of claim 19 further comprising
a second transistor device (Fig. 3 & 4: 21; Par. 42 – 43)
…
and a second gate conductive redistribution material (Fig. 4: 212; Par. 42 – 43)
conductively coupling…to a second gate output node (Fig. 3: terminals where 40 connects to 212 of 21 via a 51; Par. 43) of the gate controller integrated circuit (Fig. 3: 212 of 21 conductively couples to the second gate output node of 40 via 51s).
However, HO does not disclose:
The second transistor device
having two or more second gate vias
along a top edge of the second transistor device
exposing a second gate electrode material
and the second gate conductive redistribution material
conductively coupling the second gate electrode material
Although, for a similar second transistor device, CHEN discloses:
A second transistor device (Fig. 1A: 100; same as the first transistor device)
having two or more second gate vias (As described for the first transistor device)
along a top edge of the second transistor device (As described for the first transistor device)
exposing a second gate electrode material
(Fig. 33LL’: 3375 of CVIA/3375 exposes 3374, which comprises polysilicon; Par. 62. That is 3375 exposes polysilicon, which is construed to be the “second gate electrode material”, but 3374 is not construed to be the “second gate electrode”.)
and a second gate conductive redistribution material (As described for the first transistor device)
conductively coupling the second gate electrode material (As described for the first transistor device).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the second transistor device of HO Fig. 10: 21 with that of CHEN Fig. 1A: 100, as these inventions are from the same field of endeavor. Further still, while HO Par. 47 and CHEN Par. 22 both disclose their respective second transistor devices to be MOSFETs, HO focuses on a packaging of its MOSFET, neglecting the details of its MOSFET structure. As such, it would have been obvious to one of ordinary skill in the art to search the prior art for the details of an acceptable MOSFET structure, which CHEN provides. Additionally, CHEN Par. 21 asserts a number of advantages to its particular MOSFET structure.
Regarding Claim 22,
HO further discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes
two or more connections [to] the first gate driver output node (Fig. 3: 222 of 22 is connected to two or more 51s connected to the first gate driver output node—the 2 of the 4 terminals where 40 connects to 134 via a 51—via 134)
However, HO does not disclose:
wherein the first gate conductive redistribution material includes
two or more connections [to] the gate metal layer to the first gate electrode material through two or more Redistribution layer vias.
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the first gate conductive redistribution material includes
two or more connections [to] the gate metal layer (Fig. 33LL’: 3378 includes a connection to 3376) to the first gate electrode material (Fig. 33LL’: 3376 includes a connection to the polysilicon of 3374) through two or more Redistribution layer vias (Fig. 33LL’: CVIA).
(The plurality of these connections is shown by each 112 in Fig. 1A corresponding to a CVIA/3375, as per Fig. 33LL’. Further, due to the multitude of 112’s in Fig. 1A—and thus CVIA/3375—if Applicant is concerned with the CVIA as being labeled as both the “redistribution layer vias” of this claim and the “conductive vias” included in the first insulating layer of Claim 1, different CVIAs may be considered for each label. Further still, this provides a connection between the first gate conductive redistribution material and the first gate electrode material for each redistribution layer via).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes two or more connections between the first gate driver output node and the gate metal layer to the first gate electrode material through two or more Redistribution layer vias (As previously stated, HO discloses two or more connections from the first gate conductive redistribution material to the first gate driver output node, and CHEN discloses two or more connections from the first gate conductive redistribution material to the gate metal layer to the first gate electrode material through two or more redistribution layer vias. As such, by the transitive property of connections, HO in view of CHEN satisfies the limitations of this claim.)
Regarding Claim 23,
HO further discloses:
The distributed drive package of claim 22
wherein the two or more connections are [each connected to the first gate conductive redistribution material] (As previously stated in Claim 22).
However, HO does not disclose:
wherein the two or more connections are [each connected between the first gate conductive redistribution material and the first gate electrode material through a given redistribution layer via].
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the two or more connections are [each connected between the first gate conductive redistribution material and the first gate electrode material through a given redistribution layer via] (As previously stated in Claim 22).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 22
wherein the two or more connections are proportionally distributed between the two or more redistribution layer vias (By the above, each redistribution layer via corresponds to the same number of the two or more connections. As such, the two or more connections are proportionally distributed between the two or more redistribution layer vias with respect to the number of the two or more redistribution layer vias)
Regarding Claim 24,
HO further discloses:
The distributed drive package of claim 22
wherein the two or more connections are each formed between two or more first gate driver output nodes (Fig. 3: 2 of the 4 terminals where 40 connects to 134 via a 51 are construed to be one of the two or more first gate driver output nodes, and the other 2 of the 4 terminals where 40 connects to 134 via a 51 are construed to be another of the two or more first gate driver output nodes) on the gate controller integrated circuit and [the first gate conductive redistribution material] (As stated in Claim 22, the two or more connections are each formed between one of the two or more first gate driver output nodes—which is on the gate controller integrated circuit 40 by definition—and the first gate conductive redistribution material. Similarly, Fig. 3 shows the two or more connections 51 are also each formed between another of the two or more first gate driver output nodes—which is also on the gate controller integrated circuit 40 by definition—and the first gate conductive redistribution material 222 of 22 via 134)
However, HO does not disclose:
wherein the two or more connections are each formed between…[the first gate conductive redistribution material] and the first gate electrode material.
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the two or more connections are each formed between…[the first gate conductive redistribution material] and the first gate electrode material (As stated in Claim 22).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 22
wherein the two or more connections are each formed between two or more first gate driver output nodes on the gate controller integrated circuit and the first gate electrode material (As previously stated, HO discloses the two or more connections are each formed between two or more first gate driver output nodes on the gate controller integrated circuit and the first gate conductive redistribution material, and CHEN discloses the two or more connections are each formed between the first gate conductive redistribution material and the first gate electrode material. As such, by the transitive property of connections, HO in view of CHEN satisfies the limitations of this claim).
Regarding Claim 25,
HO further discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes a metal wire connected to the first gate driver output node (Fig. 3 & 10: 222 of 22 may be construed to include the metal wire 51—Par. 49—to which it is directly connected and provides a connection to the first gate driver output node via 134.).
However, HO dose not disclose:
wherein the first gate conductive redistribution material… [is] conductively coupled to the first gate electrode material.
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the first gate conductive redistribution material… [is] conductively coupled to the first gate electrode material (As stated for claim 19).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes a metal wire connected to the first gate driver output node and conductively coupled to the first gate electrode material (As previously stated, HO discloses the first gate conductive redistribution material includes a metal wire connected to the first gate driver output node, and CHEN discloses the first gate conductive redistribution material is conductively coupled to the first gate electrode material. As such, by the transitive property of connections, HO in view of CHEN satisfies the limitations of this claim).
Regarding Claim 26,
HO further discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes one or more conductive [pathways not integrated into the substrate of the first transistor device] conductively coupled to the first gate driver output node (Same argument as for Claim 25 where the one or more conductive pathways not integrated into the substrate of the first transistor device is the metal wire).
However, HO does not disclose:
wherein the first gate conductive redistribution material includes one or more conductive traces conductively coupled to the first gate driver output node and conductively coupled to the first gate electrode material.
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the first gate conductive redistribution material…[is] conductively coupled to the first gate electrode material (As stated for Claim 19).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes one or more conductive [pathways not integrated into the substrate of the first transistor device] conductively coupled to the first gate driver output node and conductively coupled to the first gate electrode material (Same argument as for Claim 25 where the one or more conductive pathways not integrated into the substrate of the first transistor device is the metal wire).
However, HO in view of CHEN does not disclose:
The distributed drive package of claim 19
wherein the first gate conductive redistribution material includes one or more conductive traces conductively coupled to the first gate driver output node and conductively coupled to the first gate electrode material.
Regardless, one of ordinary skill in the art would have recognized the finite number of predictable means to conductively couple the first gate conductive redistribution material to the first gate driver output node—i.e. via conductive pathways not integrated into the substrate of the first transistor device or via conductive pathways integrated into the substrate of the first transistor device, which would be construed as traces under a broad but reasonable interpretation. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try both types of conductive pathways to determine which type is suitable for conductively coupling the first gate conductive redistribution material to the first gate driver output node.
Regarding Claim 27,
HO further discloses:
The distributed drive package of claim 19
…
wherein the first gate conductive redistribution material also conductively couples…to the first gate driver output node of the gate controller integrated circuit (As stated for Claim 19).
However, HO does not disclose:
wherein the first transistor device includes two or more additional first gate vias on a second top edge portion of the first transistor device and
wherein the first gate conductive redistribution material also conductively couples the first gate electrode material of the first transistor device…through the two or more additional first gate vias on the second top edge portion of the first transistor device.
Although, for the similar first transistor device of CHEN, CHEN discloses:
wherein the first transistor device includes two or more additional first gate vias on a second top edge portion of the first transistor device (Fig. 1A: 100 includes two or more additional 112s on the portion of 100 corresponding to GCR2.)
and wherein the first gate conductive redistribution material also conductively couples the first gate electrode material of the first transistor device…through the two or more additional first gate vias on the second top edge portion of the first transistor device (Same argument as for Claim 19, as all 112s of 100 have the same structure).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 19
wherein the first transistor device includes two or more additional first gate vias on a second top edge portion of the first transistor device and wherein the first gate conductive redistribution material also conductively couples the first gate electrode material of the first transistor device to the first gate driver output node of the gate controller integrated circuit through the two or more additional first gate vias on the second top edge portion of the first transistor device (As previously stated, HO discloses the first gate conductive redistribution material also conductively couples…to the first gate driver output node of the gate controller integrated circuit, and CHEN discloses the first transistor device includes two or more additional first gate vias on a second top edge portion of the first transistor device, and the first gate conductive redistribution material also conductively couples the first gate electrode material of the first transistor device…through the two or more additional first gate vias on the second top edge portion of the first transistor device. As such, by the transitive property of conductive coupling, HO in view of CHEN satisfies the limitations of this claim).
Regarding Claim 28,
HO further discloses:
The distributed drive package of claim 19
wherein the gate controller integrated circuit includes a second gate driver output node (Fig. 3: 40 includes the remaining 2 of the 4 terminals where 40 connects to 134 via a 51) [conductively coupled to the first gate conductive redistribution material] (Fig. 3 & 10: the second gate driver output node conductively couples to 222 of 22 via 134)
However, HO does not disclose:
and wherein the first transistor device includes two or more second gate vias on a second top edge portion of the first transistor device
and wherein a second gate conductive redistribution layer conductively couples a second gate electrode material of the first transistor device to the…[first gate conductive redistribution material] through the two or more second gate vias on the second top edge portion of the first transistor device.
Although, for the similar first transistor device of CHEN, CHEN discloses:
and wherein the first transistor device includes two or more second gate vias on a second top edge portion of the first transistor device (Fig. 1A: 100 includes two or more 112s on the portion of 100 corresponding to GCR2.)
and wherein a second gate conductive redistribution layer (Fig. 1A: conductive material within 120s corresponding to Fig. 33AA’: 3316; Par. 22 & 58) conductively couples a second gate electrode material (Fig. 1A: conductive material within 104s corresponding to Fig. 33AA’: 3312 & 3314; Par. 22 & 59) of the first transistor device to the…[first gate conductive redistribution material] through the two or more second gate vias on the second top edge portion of the first transistor device (Fig. 1A: conductive material within 120s conductively couples the conductive material within the 104s of 100 to 114 through the two or more 112s in GCR2).
As such, HO in view of CHEN discloses:
The distributed drive package of claim 19
wherein the gate controller integrated circuit includes a second gate driver output node and wherein the first transistor device includes two or more second gate vias on a second top edge portion of the first transistor device and wherein a second gate conductive redistribution layer conductively couples a second gate electrode material of the first transistor device to the second gate driver output node through the two or more second gate vias on the second top edge portion of the substrate composition (As previously stated, HO discloses the gate controller integrated circuit includes a second gate driver output node conductively coupled to the first gate conductive redistribution material, and CHEN discloses the first transistor device includes two or more second gate vias on a second top edge portion of the first transistor device, and a second gate conductive redistribution layer conductively couples a second gate electrode material of the first transistor device to the first gate conductive redistribution material through the two or more second gate vias on the second top edge portion of the first transistor device. As such, by the transitive property of conductive coupling, HO in view of CHEN satisfies the limitations of this claim).
Regarding Claim 29,
HO fails to disclose:
The distributed drive package of claim 28
wherein the two or more second gate vias are proportionally distributed over a second gate electrode contact region.
Although, for the similar first transistor device of CHEN, CHEN discloses:
The distributed drive package of claim 28
wherein the two or more second gate vias are proportionally distributed over a second gate electrode contact region (Fig. 1A: the two or more 112s on the portion of 100 corresponding to GCR2 are distributed over the portion of 114 corresponding to GCR2—i.e. the second gate electrode contact region. Further, there is a single 112 in the second gate electrode contact region corresponding to each “gate runner extension trench” 120; Par. 22. As such, the two or more additional 112s are proportionally distributed over the second gate electrode contact region with respect to the number 120s in said second gate electrode contact region).
Regarding Claim 30,
HO further discloses:
The distributed drive package of claim 19
wherein the first transistor device includes at least one on-chip capacitor (Par. 47: the first transistor device 22 is a MOSFET, which inherently includes an on-chip capacitor).
Claims 21 & 31 are rejected under 35 U.S.C. 103 as being unpatentable over HO in view of CHEN and in further view of WILLIAMS (US 20070146020 A1).
Regarding Claim 21,
HO further discloses:
The distributed drive package of claim 20
wherein the first transistor device is a low side field effect transistor (Fig. 3 & 10: 22; Par. 47 – 49)
and the second transistor is a high side field effect transistor (Fig. 3 & 4: 21; Par. 42 – 43)
for a voltage regulator (HO Par. 4 – 24 disclose the distributed drive package of HO to be a “DC-DC converter”, using the high side and low side field effect transistors as its switches. As such, this type of “DC-DC converter” is known in the art as a switching voltage regulator, as per WILLIAMS Par. 2 – 5).
Regarding Claim 31,
HO further discloses:
The distributed drive package of claim 19
wherein the gate controller integrated circuit is a monolithic integrated circuit including a second transistor device (Fig. 1 & 2 indicate the gate controller in analogous prior art and, thus, Fig. 4: 40 is an integrated circuit, which is also known in the art as a monolithic integrated circuit. Further, gate controllers of DC-DC converters—such as 40 of Fig. 3—are known in the art to comprise operational amplifiers, which comprise a number of transistors, which satisfies the requirement of a second transistor device for this claim, as per WILLIAMS Fig. 5A; Par. 70).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over HO in view of CHEN and in further view of SHIBIB (US 20160056138 A1).
Regarding Claim 32,
HO further discloses:
The distributed drive package of claim 19
wherein the first transistor device includes…[the first gate conductive] redistribution material between the [first transistor device] and [the first gate driver output] node on the gate controller integrated circuit (Fig. 3 & 10: 22 includes 222 between 22 and the first gate driver output node on 40).
However, neither HO nor CHEN disclose:
wherein the first transistor device includes a sense FET and a sense FET redistribution material between the sense FET and a Sense FET node on the gate controller integrated circuit.
Although, for a similar first transistor device, SHIBIB discloses:
wherein the first transistor device (Fig. 1A: 150) includes a sense FET (Fig. 1A: 160) and a sense FET redistribution material (Fig. 1A: 140).
As such, HO in view of CHEN and in further view of SHIBIB discloses:
The distributed drive package of claim 19
wherein the first transistor device includes a sense FET and a sense FET redistribution material between the sense FET and a Sense FET node on the gate controller integrated circuit (As previously stated, HO discloses the first transistor device includes the first gate conductive redistribution material between the first transistor device and the first gate driver output node on the gate controller integrated circuit, and SHIBIB discloses the first transistor device includes a sense FET and a sense FET redistribution material. Further, by the design of SHIBIB Fig. 1B, the connection to the gate of the sense FET is shared with the connection of the gate to the first transistor device. That is, the sense FET redistribution material—SHIBIB Fig. 1A: 140—is the same element as the first gate conductive redistribution material—HO Fig. 10: 222—in this prior art combination. As a consequence, the sense FET node on the gate controller integrated circuit is also the same element as the first gate driver output node on the gate controller integrated circuit in this prior art combination. Therefore, the sense FET redistribution material is between the sense FET and the sense FET node on the gate controller integrated circuit because the first gate conductive redistribution material is between the first transistor device—which comprises sense FET—and the first gate driver output node on the gate controller integrated circuit, satisfying the limitations of this claim).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the sense FET of SHIBIB with the distributed device package of HO in view of CHEN, as these inventions are from the same field of endeavor, and sense FETs are a known means in the art to provide enhanced control of such distributed device packages, SHIBIB Par. 1 – 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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/K.S.S./Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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