DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 7, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al. (US 2023/0387031) (“Yang”).
With regard to claim 1, figs. 2, 4, and 24 of Yang discloses a semiconductor package 10, comprising: a first redistribution structure (606, 608) having a structure in which at least one first redistribution layer 608 and at least one first insulating layer 606 are alternately stacked on each other; a first semiconductor chip 120 disposed on the first redistribution structure (606, 608); a second semiconductor chip 140 disposed on the first redistribution structure (606, 608); and bumps 26 disposed between the first redistribution structure (606, 608) and the first semiconductor chip 120 and between the first redistribution structure (606, 608) and the second semiconductor chip 140, wherein the at least one first redistribution layer 608 includes a detour redistribution line 1320 disposed so that a portion of the detour redistribution line 1320 overlaps a space RS between the first 120 and second semiconductor chips 140, and the detour redistribution line 1320 circuitously extends across the space RS between the first 120 and second 140 semiconductor chips so as not to overlap a stress concentration region (top region of RS in fig. 4) partially overlapping a portion of one flank (bottom portion of RS in fig. 4) of the space RS between the first 120 and second 140 semiconductor chips, or extends into the stress concentration region (top portion of RS in fig. 4).
With regard to claim 5, figs. 2, 4, and 24 of Yang discloses that the first redistribution structure (608, 606) comprises first redistribution vias (“via openings”, par [0053]) penetrating the at least one first insulating layer 606 and connected to the at least one first redistribution layer 608, one of the first redistribution vias (“via”, par [0053]) connected to the detour redistribution line 1320 overlaps the stress concentration region (top of RS in fig. 4), and the detour redistribution line 1320 extends to the stress concentration region (top of RS in fig. 4).
With regard to claim 7, figs. 2, 4, and 24 of Yang discloses that the detour redistribution line 1320 has a shape in which an extending direction (vertical extending portion of 1320 in fig. 4) is bent at a portion overlapping between RS the first 120 and second 140 semiconductor chips.
With regard to claim 9, figs. 2, 4, and 24 of Yang discloses that the at least one first redistribution layer 606 further comprises an additional redistribution line 608T disposed so that a portion of the additional redistribution line 608T overlaps the space RS between the first 120 and second 140 semiconductor chips, and the detour redistribution line 1320 and the additional redistribution line 608T are more adjacent to each other in one portion overlapping the space RS between the first 120 and second semiconductor 140 chips than in another portion that is not overlapping the space RS between the first 120 and second 140 semiconductor chips.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2023/0387031) (“Yang”) in view of Hsieh et al. (US 9,741,690) (“Hsieh”).
With regard to claim 8, figs. 2, 4, and 24 of Yang discloses that a portion of the detour redistribution line 1320, overlapping a boundary line (edge of 120) of one of the first 120 or second semiconductor chips.
Yang does not disclose that the detour redistribution line is oblique with respect to the boundary line.
However, fig. 17 of Hsieh that the detour redistribution line 710 is oblique (710 not perpendicular to 702A) with respect to the boundary line 702a.
Therefore, it would have been obvious to one of ordinary skill in the art to form the first metal line of Yang at an oblique angle with the edge of the die as taught in Hsieh in order to reduce the stress in the conductive lines. See col. 11 ll. 46-47 of Hsieh.
Claims 10-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2023/0387031) (“Yang”) in view of Lee et al. (US 10,109,617) (“Lee”).
With regard to claims 10 and 13, figs. 2, 4, and 24 of Yang discloses that a portion (1132 in RS) of the detour redistribution line 1132 does not overlap the first semiconductor chips 120, and does not overlap the second semiconductor chips 140.
Yang does not disclose that the first semiconductor chip is composed of stacked first semiconductor chips, the second semiconductor chip is composed of stacked second semiconductor chips.
However, fig. 9 of Lee discloses that the first semiconductor chip ST1 is composed of stacked first semiconductor chips ST1, the second semiconductor chip ST2 is composed of stacked second semiconductor chips ST2.
Therefore, it would have been obvious to one of ordinary skill in the art to form the chips of Yang with the chip stacks as taught in Lee in order to provide a plurality of non-volatile memory chips. See col. 6 ll. 39-42 of Lee.
With regard to claim 11, Yang does not disclose a second redistribution structure having a structure in which at least one second redistribution layer and at least one second insulating layer are alternately stacked on each other; an embedded semiconductor chip disposed between the first and second redistribution structures; conductive vias electrically connecting the first and second redistribution structures to each other; and an encapsulant disposed between the first and second redistribution structures and encapsulating the embedded semiconductor chip.
However, fig. 9 of Lee discloses a second redistribution structure 120 having a structure in which at least one second redistribution layer 123 and at least one second insulating layer 121 are alternately stacked on each other; an embedded semiconductor chip 10 disposed between the first 140 and second redistribution structures 120; conductive vias 115 electrically connecting the first 140 and second 120 redistribution structures to each other; and an encapsulant 110c disposed between the first 140 and second 120 redistribution structures and encapsulating 110c the embedded semiconductor chip 10.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
With regard to claim 12, figs. 2, 4, and 24 of Yang discloses a semiconductor package 10, comprising: a first redistribution structure (606, 608) having a structure in which at least one first redistribution layer 608 and at least one first insulating layer 606 are alternately stacked on each other; a first semiconductor chip 120 disposed on the first redistribution structure (606, 608); a second semiconductor chip 140 disposed on the first redistribution structure (606, 608); wherein the at least one first redistribution layer 608 includes a detour redistribution line 1320 disposed so that a portion of the detour redistribution line 1320 overlaps a space RS between the first 120 and second semiconductor chips 140, and the detour redistribution line 1320 circuitously extends across the space RS between the first 120 and second 140 semiconductor chips so as not to overlap a stress concentration region (top region of RS in fig. 4) partially overlapping a portion of one flank (bottom portion of RS in fig. 4) of the space RS between the first 120 and second 140 semiconductor chips, or extends into the stress concentration region (top portion of RS in fig. 4).
Yang does not disclose a second redistribution structure having a structure in which at least one second redistribution layer and at least one second insulating layer are alternately stacked on each other; an embedded semiconductor chip disposed between the first and second redistribution structures; conductive vias electrically connecting the first and second redistribution structures to each other; andan encapsulant disposed between the first and second redistribution structures and encapsulating the embedded semiconductor chip.
However, fig. 9 of Lee discloses a second redistribution structure 120 having a structure in which at least one second redistribution layer 123 and at least one second insulating layer 121 are alternately stacked on each other; an embedded semiconductor chip 10 disposed between the first 140 and second redistribution structures 120; conductive vias 115 electrically connecting the first 140 and second 120 redistribution structures to each other; and an encapsulant 110c disposed between the first 140 and second 120 redistribution structures and encapsulating 110c the embedded semiconductor chip 10.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
With regard to claim 14, figs. 2, 4, and 24 of Yang discloses that the portion of the detour redistribution line 1320, overlapping the space RS between the first semiconductor chips 120 and the second semiconductor chips 140.
Yang does not disclose that the detour redistribution line also overlaps the embedded semiconductor chip.
However, fig. 9 of Lee discloses that the detour redistribution line 143 also overlaps the embedded semiconductor chip 10.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
With regard to claim 15, Yang does not disclose a core insulating layer disposed between the first and second redistribution structures and at least partially surrounding the embedded semiconductor chip and at least a portion of the encapsulant, wherein the conductive vias are disposed in the core insulating layer, and at least a portion of the stress concentration region overlaps a portion of the core insulating layer.
However, fig. 9 of Lee discloses a core insulating layer 111 disposed between the first 140 and second 120 redistribution structures and at least partially surrounding the embedded semiconductor chip 10 and at least a portion of the encapsulant 110c, wherein the conductive vias 115 are disposed in the core insulating layer 111, and at least a portion of the stress concentration region (space between ST1 and ST2) overlaps a portion of the core insulating layer 111.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
With regard to claim 18, figs. 2, 4, and 24 of Yang discloses that the detour redistribution line 1320 has a shape in which an extending direction is bent at a portion overlapping the space RS between the first 120 and second 140 semiconductor chips.
With regard to claim 19, figs. 2, 4, and 24 of Yang discloses a semiconductor package 10, comprising: a first redistribution structure (606, 608) having a structure in which at least one first redistribution layer 608 and at least one first insulating layer 606 are alternately stacked on each other; a first semiconductor chip 120 disposed on a first surface (top of 606) the first redistribution structure (606, 608); a second semiconductor chip 140 disposed on the first surface (top of 606) of first redistribution structure (606, 608); wherein the at least one first redistribution layer 608 includes a detour redistribution line 1320 disposed so that a portion of the detour redistribution line 1320 overlaps a space RS between the first 120 and second semiconductor chips 140, at least one first redistribution layer 606 further comprises an additional redistribution line 608T disposed so that a portion of the additional redistribution line 608T overlaps the space RS between the first 120 and second 140 semiconductor chips, and the detour redistribution line 1320 and the additional redistribution line 608T are more adjacent to each other in one portion overlapping the space RS between the first 120 and second semiconductor 140 chips than in another portion that is not overlapping the space RS between the first 120 and second 140 semiconductor chips.
Yang does not disclose a second redistribution structure having a structure in which at least one second redistribution layer and at least one second insulating layer are alternately stacked on each other; an embedded semiconductor chip disposed between the first and second redistribution structures; conductive vias electrically connecting the first and second redistribution structures to each other; and an encapsulant disposed between the first and second redistribution structures and encapsulating the embedded semiconductor chip.
However, fig. 9 of Lee discloses a second redistribution structure 120 having a structure in which at least one second redistribution layer 123 and at least one second insulating layer 121 are alternately stacked on each other; an embedded semiconductor chip 10 disposed between the first 140 and second redistribution structures 120; conductive vias 115 electrically connecting the first 140 and second 120 redistribution structures to each other; and an encapsulant 110c disposed between the first 140 and second 120 redistribution structures and encapsulating 110c the embedded semiconductor chip 10.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
With regard to claim 20, figs. figs. 2, 4, and 24 of Yang discloses bumps 26 electrically connecting one of the first semiconductor chips 120 and the first redistribution structure (606, 608) to each other, or electrically connecting one of the second semiconductor chips and the first redistribution structure to each other.
Yang does not disclose a core insulating layer disposed between the first and second redistribution structures and at least partially surrounding the embedded semiconductor chip and at least a portion of the encapsulant.
However, fig. 9 of Lee discloses a core insulating layer 111 disposed between the first 140 and second 120 redistribution structures and at least partially surrounding the embedded semiconductor chip 10 and at least a portion of the encapsulant 110c.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer of Yang with the integrated circuit substrate as taught Lee in order to provide a buffer memory chip for the solid state drive package. See col. 9 ll. 36-38 of Lee.
Allowable Subject Matter
Claims 2-4, 6, 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893