DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 13, and 17-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2020/0194455) (“Cho”).
With regard to claim 1, figs. 12a-16 of Cho discloses a memory device comprising: a memory block CAR comprising a plurality of wordlines (“horizontal layers HL may be word lines”, par [0067]) stacked in a vertical direction D3 and extending in a first horizontal direction D1; and a pass transistor block BSR comprising a plurality of pass transistors (“block selection transistors”, par [0071]) stacked in the vertical direction D3, wherein the plurality of pass transistors (“block selection transistors”, par [0071]) are configured to transmit a plurality of driving signals respectively to the plurality of wordlines HL, wherein each pass transistor (“block selection transistors”, par [0071]) of the plurality of pass transistors (“block selection transistors”, par [0071]) comprises: a body region CHR having an upper surface (upper surface of CHR in fig.13) and a lower surface (lower surface of CHR in fig. 13) which face in the vertical direction D3, a first side surface (right side of CHR in fig. 14) and a second side surface (left side of CHR in fig. 14) which face in the first horizontal direction D1, and a front surface (bottom surface of CHR in fig. 14) and a rear surface (top surface of CHR in fig. 14) which face in a second horizontal direction D2; a first source-drain electrode SD2 on the first side surface (right side of CHR in fig. 14), and configured to receive a corresponding driving signal of the plurality of driving signals (“signal”, par [0032]); a second source-drain electrode SD1 on the second side surface (left side of CHR in fig. 14), wherein the second source-drain electrode SD1 is electrically connected to a side surface of a corresponding wordline HL of the plurality of wordlines HL; and a first vertical gate electrode VGH on a first surface (bottom surface of CHR in fig. 14) from among the front surface and the rear surface (bottom and top surfaces of CHR in fig. 14).
With regard to claim 2, figs. 12a-16 of Cho discloses that the first vertical gate electrode VGE is included in a first gate line VGE extending in the vertical direction D3.
With regard to claim 3, figs. 12a-16 of Cho discloses that the plurality of pass transistors (“block selection transistors”, par [0071]) are simultaneously switched based on a block selection signal BSL applied to the first gate line VGE.
With regard to claim 13, figs. 12a-16 of Cho discloses that each pass transistor (“block selection transistors”, par [0071]) and the corresponding wordline HL are disposed at a same height in the vertical direction D3.
With regard to claim 17, figs. 12a-16 of Cho discloses a memory device comprising: a plurality of memory blocks BLK, wherein each memory block of the plurality of memory blocks BLK comprises a plurality of wordlines HL stacked in a vertical direction D3 and extending in a first horizontal direction D1; and a plurality of pass transistor blocks BSR, wherein each pass transistor block BSR from among the plurality of pass transistor blocks BSR comprises a plurality of pass transistors (“block selection transistors”, par [0071]) stacked in the vertical direction D3, and is configured to transmit a plurality of driving signals to a plurality of wordlines HL included in a corresponding memory block BLK, wherein each pass transistor (“block selection transistors”, par [0071]) of the plurality of pass transistors (“block selection transistors”, par [0071]) comprises: a body region CHR having an upper surface (upper surface of CHR in fig.13) and a lower surface (lower surface of CHR in fig. 13) which face in the vertical direction D3, a first side surface (right side of CHR in fig. 14) and a second side surface (left side of CHR in fig. 14) which face in the first horizontal direction D1, and a front surface (bottom surface of CHR in fig. 14) and a rear surface (top surface of CHR in fig. 14) which face in a second horizontal direction D2; a first source-drain electrode SD2 on the first side surface (right side of CHR in fig. 14), and configured to receive a corresponding driving signal of the plurality of driving signals (“signal”, par [0032]); a second source-drain electrode SD1 on the second side surface (left side of CHR in fig. 14), wherein the second source-drain electrode SD1 is electrically connected to a side surface of a corresponding wordline HL of the plurality of wordlines HL; and a first vertical gate electrode VGH on a first surface (bottom surface of CHR in fig. 14) from among the front surface and the rear surface (bottom and top surfaces of CHR in fig. 14).
With regard to claim 18, figs. 12a-16 of Cho discloses that the plurality of memory blocks BLK are arranged in the second horizontal direction D2, and wherein the plurality of pass transistor blocks BSR are distributed on the first side surface (right side of CHR in fig. 14) and the second side surface (left side of CHR in fig. 14) in the first horizontal direction D1.
With regard to claim 19, figs. 12a-16 of Cho discloses that the plurality of memory blocks BLK are formed on a first wafer (CAR in 10) and the plurality of pass transistor blocks are formed on a second wafer (BSR in 10), and wherein the plurality of memory blocks BLK are coupled to the plurality of pass transistor blocks (“block selection transistors”, par [0071]).
Applicant's claim 19 do not distinguish over the Cho reference regardless of the process used to form the coupling of memory to transistor blocks because only the final product is relevant, not the process of making such as by a bonding process.
Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps. See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Once a product appearing to be substantially identical is found and a 35 U.S.C. 102/103 rejection made, the burden shifts to the applicant to show an unobvious difference. See In re Fessmann, 489 F.2d 742, 744, 180 USPQ 324, 326 (CCPA 1974), In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983), and Ex parte Gray, 10 USPQ2d 1922 (Bd. Pat. App. & Inter. 1989). The use of 35 U.S.C. 102/103 rejections for product-by-process claims has been approved by the courts. See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also MPEP § 2113.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-12 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0194455) (“Cho”) in view of Bi et al. (US 10,804,274) (“Bi”).
With regard to claim 4, Cho does not disclose that the each pass transistor further comprises: an upper horizontal gate electrode disposed on the upper surface of the body region; and a lower horizontal gate electrode disposed on the lower surface of the body region.
However, fig. 42 of Bi discloses that the each pass transistor 4200a further comprises: an upper horizontal gate electrode 3810 disposed on the upper surface of the body region 135; and a lower horizontal gate electrode 3810 disposed on the lower surface of the body region 135.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claim 5, figs. 12a-16 of Cho disclose that the first vertical gate electrode VGE is included in a first gate line VGE extending in the vertical direction D3.
Cho does not disclose that the upper horizontal gate electrode and the lower horizontal gate electrode are connected to the first gate line.
However, fig. 42 of Bi discloses that the upper horizontal gate electrode 3810 and the lower horizontal gate electrode 3810 are connected to the first gate line 3810.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claim 6, Cho does not disclose that the plurality of pass transistors comprise a first pass transistor which is vertically adjacent to a second pass transistor, wherein the first pass transistor comprises a first upper horizontal gate electrode and a first lower horizontal gate electrode, and the second pass transistor comprises a second upper horizontal gate electrode and a second lower horizontal gate electrode, and wherein the first upper horizontal gate electrode and the second lower horizontal gate electrode are integrally formed as one conductor.
However, fig. 42 of Bi discloses that the plurality of pass transistors comprise a first pass transistor (middle 135, fig. 42) which is vertically adjacent to a second pass transistor (top 135, fig. 42), wherein the first pass transistor (middle 135, fig. 42) comprises a first upper horizontal gate electrode (middle 3810) and a first lower horizontal gate electrode (bottom 3810), and the second pass transistor (top 135) comprises a second upper horizontal gate electrode (top 3810) and a second lower horizontal gate electrode (middle 3810, fig. 42), and wherein the first upper horizontal gate electrode (middle 3810, fig. 42) and the second lower horizontal gate electrode (middle 3810, fig. 42) are integrally formed as one conductor (middle 3810, fig. 42).
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claim 7, figs. 12a-16 of Cho disclose a channel CHR of the each pass transistor is formed in the body region CHR under the first surface (bottom of CHR, fig. 14), the upper surface (top of CHR, fig. 13) and the lower surface (bottom of CHR, fig. 13).
With regard to claim 8, Cho does not disclose that each pass transistor further comprises: a second vertical gate electrode disposed on a second surface from among the front surface and the rear surface.
However, fig. 42 of Bi discloses that each pass transistor further comprises: a second vertical gate electrode (“gate-all-around”, abstract) disposed on a second surface from among the front surface (further side surface of 135 along plane of page fig. 42) and the rear surface (closer side surface of 135 along plane of page in fig. 42).
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claims 9 and 11, figs. 12a-16 of Cho discloses that the first vertical gate electrode VGE is included in a first gate line VGE extending in the vertical direction D3.
However, fig. 42 of Bi discloses that the second vertical gate electrode (“gate-all-around”, abstract) is included in a second gate line 810 extending in the vertical direction, and wherein an end portion in the vertical direction of the first gate line is electrically connected (“gate-all-around”, abstract) to an end portion in the vertical direction of the second gate line.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claim 10, Cho does not disclose that each pass transistor further comprises: a second vertical gate electrode disposed on a second surface from among the front surface and the rear surface; an upper horizontal gate electrode disposed on the upper surface; and a lower horizontal gate electrode disposed on the lower surface.
However, fig. 42 of Bi discloses that each pass transistor further comprises: a second vertical gate electrode (“gate-all-around”, abstract) disposed on a second surface from among the front surface and the rear surface (side surfaces of 135 along plane of page in fig. 42); an upper horizontal gate electrode (middle 3810 in fig. 42) disposed on the upper surface; and a lower horizontal gate electrode (lower 3810 in fig. 42) disposed on the lower surface.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate electrodes of Cho surrounding the channel as taught in Bi in order to provide a relatively small FET footprint, superior channel electrostatics controls, and desirable device characteristics. See col. 4 ll. 34, 55-68 of Bi.
With regard to claim 12, figs. 12a-17 of Cho discloses a channel CHR of the each pass transistor is formed in the body region CHR under the front surface (bottom CHR, fig. 14), the rear surface (top CHR, fig. 14), the upper surface (top page plane of CHR, fig. 14) and the lower surface (bottom page plane of CHR, fig. 14).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0194455) (“Cho”) in view of Ninomiya (US 11,626,418).
With regard to claim 20, figs. 12A-16 of Cho discloses a memory device comprising: a plurality of first bonding metal patterns (“Bit line conductive pads”, par [0069]) in a cell region CAR; a plurality of memory blocks BLK in the cell region CAR, wherein each memory block BLK comprises a plurality of wordlines HL stacked in a vertical direction D3 and extending in a first horizontal direction D1; and a plurality of pass transistor blocks (“block selection transistors”, par [0071]) in the cell region CAR, wherein each pass transistor block (“block selection transistors”, par [0071]) from among the plurality of pass transistor blocks (“block selection transistors”, par [0071]) comprises a plurality of pass transistors (“block selection transistors”, par [0071]) stacked in the vertical direction D3, and configured to transmit a plurality of driving signals to a plurality of wordlines included in a corresponding memory block, wherein each pass transistor (“block selection transistors”, par [0071]) of the plurality of pass transistors (“block selection transistors”, par [0071]) comprises: a body region CHR having an upper surface (upper surface of CHR in fig.13) and a lower surface (lower surface of CHR in fig. 13) which face in the vertical direction D3, a first side surface (right side of CHR in fig. 14) and a second side surface (left side of CHR in fig. 14) which face in the first horizontal direction D1, and a front surface (bottom surface of CHR in fig. 14) and a rear surface (top surface of CHR in fig. 14) which face in a second horizontal direction D2; a first source-drain electrode SD2 on the first side surface (right side of CHR in fig. 14), and configured to receive a corresponding driving signal of the plurality of driving signals (“signal”, par [0032]); a second source-drain electrode SD1 on the second side surface (left side of CHR in fig. 14), wherein the second source-drain electrode SD1 is electrically connected to a side surface of a corresponding wordline HL of the plurality of wordlines HL; and a first vertical gate electrode VGH on a first surface (bottom surface of CHR in fig. 14) from among the front surface and the rear surface (bottom and top surfaces of CHR in fig. 14).
Cho does not disclose a plurality of second bonding metal patterns in a peripheral region under the cell region, wherein the peripheral region is vertically coupled to the cell region by the plurality of first bonding metal patterns and the plurality of second bonding metal patterns.
However, fig. 18 of Ninomiya discloses a plurality of second bonding metal patterns 788 in a peripheral region 700 under the cell region 1000, wherein the peripheral region 700 is vertically coupled to the cell region 1000 by the plurality of first bonding metal patterns 188 and the plurality of second bonding metal patterns 788.
Therefore, it would have been obvious to one of ordinary skill in the art to form the control logic of Cho under the memory cells as taught in Ninomiya in order to take up less lateral space and drive the memory cells in the memory die. See col. 36 ll 42-44 of Ninomiya.
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893