DETAILED ACTION
Response to Arguments
Applicant's arguments filed 7/1/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 10, applicant argues on page 8 of the arguments that Vladimirova does not disclose a copper layer extending laterally beyond a separate copper tile to provide laterally outward electrical connection region. However, fig. 1 of Vladimirova discloses that the Cu tile 110 is disposed above the first Cu layer 118 and beneath the IC chip 102, wherein the first Cu layer 118 extends laterally beyond a perimeter of the Cu tile 110, wherein the Cu tile 110 has a thickness greater than a thickness of the first Cu layer 118, and wherein a plurality of electrical conductors 112 electrically connect corresponding electrical contacts (“pads 112 in contact with the chip 102”, par [0070]) of the IC chip 102 to portions of the first Cu layer 118 disposed laterally outward of the Cu tile 110. Thus, claims 1 and 10 remain rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9-13, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vladimirova et al. (US 2021/0351100) (“Vladimirova”).
With regard to claim 1, fig. 1 of Vladimirova discloses a package comprising: a substrate 114 comprising a ceramic (“ceramic”, par [0073]) layer 116, a first Cu (“copper”, par [0073]) layer 118 disposed on one side (top of 116) of the ceramic layer 116, and a second Cu (“copper”, par [0073]) layer 120 disposed on an opposing side (bottom of 116) of the ceramic layer 116, wherein the second Cu layer 120 is to be thermally coupled to a heat sink (“metallised support 114 may be secured, at the rear face thereof and by means of another layer of solder, to a cooling assembly comprising for example a metal sole plate”, par [0074]); an integrated (IC) chip 102; a Cu (“copper”, par [0066]) tile 110 having a predetermined thickness (thickness of 110), a first side (top of 110), and a second side (bottom of 110) opposing the first side (top of 110), the first side (top of 110) of the Cu tile 110 being configured to thermally couple to the IC chip 102; and a thermally conducting layer 122 disposed between the first Cu layer 118 of the substrate 114 and the second side (bottom of 110) of the Cu tile 110, wherein the Cu tile 110 is disposed above the first Cu layer 118 and beneath the IC chip 102, wherein the first Cu layer 118 extends laterally beyond a perimeter of the Cu tile 110, wherein the Cu tile 110 has a thickness greater than a thickness of the first Cu layer 118, and wherein a plurality of electrical conductors 112 electrically connect corresponding electrical contacts (“pads 112 in contact with the chip 102”, par [0070]) of the IC chip 102 to portions of the first Cu layer 118 disposed laterally outward of the Cu tile 110.
With regard to claim 2, fig. 1 of Vladimirova discloses that the thermally conducting layer 122 includes solder (“solder 122”, par [0073]).
With regard to claim 3, fig. 1 of Vladimirova discloses that the predetermined thickness of the Cu tile 110 is in a range of 0.5 to 2.5 mm (“thickness of each of the metal layers 108, 110 is for example greater than approximately 100 μm, and for example equal to several hundreds of microns”, par [0066]).
With regard to claim 4, fig. 1 of Vladimirova discloses that the predetermined thickness of the Cu tile 110 is about 1.5 mm (“several hundreds of microns”, par [0066]).
With regard to claim 7, fig. 1 of Vladimirova discloses a second thermally conducting layer 112 sandwiched between the first side (top of 110) of the Cu tile 110 and the IC chip 102; and the heat sink (“metal sole plate”, par [0074]) having a thermal interface (“another layer of solder,”, par [0074]) with the second Cu layer 120 of the substrate 114.
With regard to claims 9, fig. 1 of Vladimirova discloses that the power module (“power electronic module”, par [0029]) configured as a power-converter device, wherein the IC chip 102 includes GaN (“GaN”, par [0030]) or SiC-based power-electronic switches.
With regard to claim 10, fig. 1 of Vladimirova discloses a multilayer substrate 114 for an integrated circuit (IC) component 102, the multilayer substrate 114 comprising: a dielectric layer 116; first 118 and second 120 copper layers disposed on opposing sides of the dielectric layer 116; and a copper tile 110 including a first side (top of 110) and a second side (bottom of 110) that opposes the first side (top of 110), the second side (bottom of 110) of the copper tile 110 being configured to couple 122 to the first copper layer 118, the first side (top of 110) of the copper tile 110 configured to thermally couple 112 to the IC component 102, wherein the Cu tile 110 is disposed above the first Cu layer 118 and beneath the IC chip 102, wherein the first Cu layer 118 extends laterally beyond a perimeter of the Cu tile 110, wherein the Cu tile 110 has a thickness greater than a thickness of the first Cu layer 118, and wherein a plurality of electrical conductors 112 electrically connect corresponding electrical contacts (“pads 112 in contact with the chip 102”, par [0070]) of the IC chip 102 to portions of the first Cu layer 118 disposed laterally outward of the Cu tile 110.
With regard to claim 11, fig. 1 of Vladimirova discloses a thermally conducting layer 122 disposed between the first copper layer 118 and the second side (bottom of 110) of the copper tile 110.
With regard to claim 12, fig. 1 of Vladimirova discloses that the thermally conducting layer 122 includes solder (“solder 122”, par [0073]).
With regard to claim 13, fig. 1 of Vladimirova discloses that the dielectric layer 116 is a ceramic layer (“ceramic”, par [0073]).
With regard to claim 15, fig. 1 of Vladimirova discloses that the thickness of the copper tile 110 is in a range of 0.5 mm (“110 is for example greater than approximately 100 μm, and for example equal to several hundreds of microns”, par [0066]) to 2.5 mm.
With regard to claim 16, fig. 1 of Vladimirova discloses that the second copper layer 120 is operable to be thermally coupled to a heat sink (“metal sole plate”, par [0074]).
With regard to claim 17, fig. 1 of Vladimirova discloses a power module comprising: the multilayer substrate 114; a second thermally conducting layer 112 disposed between the first side of the copper tile 110 and the integrated circuit component 102; the integrated circuit component 102; and a heat sink (“metal sole plate”, par [0074]) operable to thermally interface with the second copper layer 120.
the integrated circuit component includes a GaN- based or SiC-based power electronic switch.
With regard to claim 19, fig. 1 of Vladimirova discloses that the power module (“power electronic module”, par [0029]) configured as a power-converter device, wherein the IC chip 102 includes GaN (“GaN”, par [0030]) or SiC-based power-electronic switches.
With regard to claim 20, fig. 1 of Vladimirova discloses that the copper tile 110 includes copper (“AlCu”, par [0065]) and one or more additional conductive metals (“AlCu”, par [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Vladimirova et al. (US 2021/0351100) (“Vladimirova”) in view of Bayerer et al. (US 2008/0079021) (“Bayerer”).
With regard to claim 5, Vladimirova does not disclose that each of the first and second Cu layers of the substrate has a thickness of about 0.3 mm.
However, fig. 1 of Bayerer discloses that each of the first 15 and second 16 Cu layers of the substrate has a thickness of about 0.3 mm (“0.3mm”, par [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the copper layers of Vladimirova with the .3 mm thickness as taught in Bayerer in order to provide a high CTE substrate. See par [0037] of Bayerer.
With regard to claim 6, Vladimirova does not disclose that the ceramic layer of the substrate includes one of A1203, AlN, or silicon nitride Si3N4.
However, fig. 1 of Bayerer discloses disclose that the ceramic layer 14 of the substrate 14 includes one of A1203, AlN (“AlN”, par [0021]), or silicon nitride Si3N4.
Therefore, it would have been obvious to one of ordinary skill in the art to form the ceramic substrate of Vladimirova from AlN as taught in Bayerer in order to provide high thermal conductivity, electrical insulation, and mechanical stability. See par [0021] of Bayerer.
With regard to claim 14, Vladimirova does not disclose that the ceramic layer of the substrate includes one of A1203, AlN, or silicon nitride Si3N4.
However, fig. 1 of Bayerer discloses disclose that the ceramic layer 14 of the substrate 14 includes one of A1203, AlN (“AlN”, par [0021]), or silicon nitride Si3N4.
Therefore, it would have been obvious to one of ordinary skill in the art to form the ceramic substrate of Vladimirova from AlN as taught in Bayerer in order to provide high thermal conductivity, electrical insulation, and mechanical stability. See par [0021] of Bayerer.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Vladimirova et al. (US 2021/0351100) (“Vladimirova”) in view of Komorita et al. (US 6,232,657) (“Komorita”).
With regard to claim 8, Vladimirova does not disclose that the second thermally conducting layer includes solder.
However, fig. 5 of Komorita discloses that the second thermally conducting layer (“solder bonding”, col. 3 ll. 56) includes solder.
Therefore, it would have been obvious to one of ordinary skill in the art to bond the chip to the metal layer of Vladimirova with the solder as taught in Komorita in order to create a reliable conductive and mechanically stable connection. See col. 3ll. 56 of Komorita.
With regard to claim 18, Vladimirova does not disclose that the second thermally conducting layer includes solder.
However, fig. 5 of Komorita discloses that the second thermally conducting layer (“solder bonding”, col. 3 ll. 56) includes solder.
Therefore, it would have been obvious to one of ordinary skill in the art to bond the chip to the metal layer of Vladimirova with the solder as taught in Komorita in order to create a reliable conductive and mechanically stable connection. See col. 3ll. 56 of Komorita.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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