Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 9, & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17].
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CLAIM 1: Park’18 teaches a semiconductor package comprising:
a first substrate 100 having an upper surface 101 and a lower surface 102 opposite to the upper surface, and including a substrate pad 111&113 arranged on the upper surface 101;
a first chip stacked structure 300 mounted on the upper surface of the first substrate 100, the first chip stacked structure 300 including a plurality of first chips [310+320+330+340] offset-stacked in a first direction (Fig. 1);
a lowermost first wire 301E electrically connecting a lowermost first chip 210 at a lowermost end among the plurality of first chips to the substrate pad 113; and
a second chip stacked structure 200 mounted on the upper surface 101 of the first substrate 100, the second chip stacked structure 200 including a plurality of second chips [0310+320+330+340]offset- stacked in the first direction, wherein the second chip stacked structure 200 is spaced apart from the first chip stacked structure 300 and an upper surface 511 of a lowermost second chip at a lowest end among the plurality of second chips is at a higher level (Chips of second stack may have a greater thickness D1 than the small thickness D2, thereby the surface may be at a higher level.) in a vertical direction than a highest level of the lowermost first wire 301E in the vertical direction.
Park’18 merely shows an outwardly arranged wire configuration, but it is silent regarding the placement of the lowermost wire between chip stacks. However, positioning wires between stacked chips, as shown in Park’17 Fig. 1, was a known, functional alternative.
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Park’17 Fig. 1 explicitly teaches arranging the lowermost wire 207 between chip stacks, it would be obvious to a PHOSITA to apply this known arrangement to Park’18 for footprint optimization. Such a modification constitutes a predictable, routine optimization yielding no unexpected results. Utilizing Park’17's teaching to modify Park’18's arrangement to place wires between chips represents a predictable, optimizing choice that yields no unexpected benefits, making the modification obvious to a PHOSITA (MPEP §2144.04).
CLAIM 2. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 1, wherein the lowermost second chip is arranged on the upper surface of the first substrate, and a thickness D1 of the lowermost second chip in the vertical direction is greater than a maximum height D2 of the lowermost first wire in the vertical direction (Park’18 – Fig. 1)).
CLAIM 4. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 2, wherein at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction (Park’18 – Fig. 1 & Park’17 – Fig. 1A)
CLAIM 5. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 1, wherein the second chip stacked structure further includes a first spacer 201 or 210 on the upper surface of the first substrate, and the lowermost second chip 210 or 220 is arranged on an upper surface of the first spacer 201 or 210 (Park’18 – Fig. 1).
CLAIM 9. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 8, wherein a sidewall opposite to a sidewall of the first spacer facing the first chip stacked structure, and a sidewall opposite to a sidewall of the lowermost second chip facing the first chip stacked structure are substantially coplanar.
CLAIM 10. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 5, wherein at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction.
Claim(s) 3 and 7is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Zhou et al. (US 20210375848 A1).
CLAIM 3. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 2, however are silent upon wherein the thickness of the lowermost second chip in the vertical direction is in a range of about 500 to about 1000 micrometers. Zhou et al. ¶31 teaches chips stacked as claimed were known to have thickness within the claimed range. As such, it would be obvious to a PHOSITA to select chips having conventional thicknesses for the device.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 7. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 5, however are silent upon wherein the thickness of the lowermost second chip in the vertical direction is in a range of about 500 to about 1000 micrometers. Zhou et al. ¶31 teaches chips stacked as claimed were known to have thickness within the claimed range. As such, it would be obvious to a PHOSITA to select chips having conventional thicknesses for the device.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Tai et al. (US 11309281 B2).
CLAIM 6. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 5, wherein the upper surface of the first spacer is at a higher level in the vertical direction than a maximum height of the lowermost first wire in the vertical direction (Park’18 – Fig. 1).
While Park’18 discloses an active chip 210 at th base of th stack, it provides the physical thickness and structural support required for the assembly. A PHOSITA would find it a matter of routine design choice to substitute this active chip with a non-active spacer of the same dimensions when electrical connectivity is not required at the level (MPEP ¶2144.04: Omission of an Element and its Function – Under this guidance, if the prior art uses an active chip that that provides both electronic function and physical spacing, it is a predictable variation to omit the electronic function while retaining the mechanical structure.)
The substitution represents a predictable variation of known elements to achieve the same mechanical standoff. Selecting a spacer instead of a chip to provide vertical clearance yields no unexpected results or synergistic benefit, as both components occupy the same footprint to maintain the physical geometry of the stack.
For further support, se Tai Fig. 3A-3B which depicts the obvious predictable variation of Park’17. Figs. 3A-B of Tai depicts the analogous chip stacks as claimed and shown in Park’17, but further imply swaps the lower most chip in Fig. 3B with a spacer 340 in Fig. 3A to provide desired standoff in the arrangement.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] in view of Park et al. (US 20170125378 A1) [Park’17] in view of Lee et al. (US 20180342481 A1).
CLAIM 8. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 5, however may be silent upon the capability of wherein a width of the first spacer in a first horizontal direction is less than a width of the lowermost second chip in the first horizontal direction Although Park’18 and Park’17 may not explicitly state that the first spacer’s width is less than the lowermost second chip’s width, this specific dimensioning was a routine design choice and obvious modification for a PHOSITA at the time of the invention. Adjusting chip sizes (thickness and width) in stacked arrangements to meet design needs was conventional knowledge. as confirmed by Lee et al. (¶[0036])1, which teaches that chips within a stack can vary in size.
Such dimensional configuration was a routine design choice and obvious modification for a PHOSITA at the time of the invention. It was well-known in the art that stacked chips could vary in thickness and width, as corroborated by Lee et al., first and second chips constituting a stack can have different sizes, thicknesses, and widths, and that these, optionally, can be the same. Therefore, adjusting these dimensions to meet specific design requirements was well within the ordinary skill of a PHOSITA.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Ng et al. (US 10312219 B2).
CLAIM 11. Park’18 in view of Park’17 teach the semiconductor package comprising:
a first substrate 200 having an upper surface and a lower surface, the lower surface being opposite to the upper surface, the first substrate including a plurality of substrate pads 111&113 arranged on the upper surface (Park’18 Fig. 1);
a first chip stacked structure mounted on the upper surface of the first substrate, the first substrate including a plurality of first chips offset-stacked in a first direction (Park’18 Fig. 1);
a lowermost first wire electrically connecting a lowermost first chip at a lowermost end among the plurality of first chips to the substrate pad arranged adjacent to the lowermost first chip (Park’18 Fig. 1);
a second chip stacked structure mounted on the upper surface of the first substrate and apart from the first chip stacked structure with the first wire therebetween in a horizontal direction (Park’18 as modified by Park’17 demonstrating the relative armament and known capability. See regarding claim 1 addressing the relative chip/wiring orientation/location modification of Park’18 in view of Park’17.), the second chip stacked structure including a plurality of second chips offset-stacked in the first direction (Park’18 Fig. 1 and Park’17 Fig. 1A).
While Park’17 and Park’18 lack explicit disclosure of the third chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of third chips offset-stacked in a second direction, adding such structures is a known, predictable modification for increasing performance (MPEP § 2144.04, Multiplication/ Duplication of Parts). Ng, Figures 5–7 & Col. 4 line 64 -Col. 5 line 8, teaches horizontally spaced, offset-stacked chips, in order to improve device performance2, making its application to Park’17/18 a trivial optimization of design constraints or mere rearrangement of existing, known components. Ng teaches, individual stacks of chips allows for increased memory and dedicated stacks of memory to different memory channels thereby improving operation and performance of the memory device.
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Therefore, a PHOSIA would find it obvious to apply Ng’s teachings to Park’17/18, arranging additional stacks to meet design constraints such as meeting number of channels and optimizing performance (MPEP § 2144.04, Design Choice Optimization & Rearrangement of Parts).
Further additional offset chip stacks would be expected to further comprise, a lowermost third wire electrically connecting a lowermost third chip at a lowermost end among the plurality of third chips to the substrate pad arranged adjacent to the lowermost third chip (Park’18 Fig. 1, Park’17 Fig. 1A & Ng figs 5-7); and a fourth chip stacked structure mounted on the upper surface of the first substrate and spaced apart from the third chip stacked structure with the third wire therebetween in the horizontal direction (Park’18 Fig. 1, Park’17 Fig. 1A – Simply duplication the arrangement of Park’18 as modified by Park’17 (as applied as addressed above and regarding claim 1, would meet the scope of the claim. See below for further clarity.), the fourth chip stacked structure including a plurality of fourth chips offset-stacked in the second direction, wherein an upper surface of a lowermost second chip at a lowest end among the plurality of second chips is at a higher level in a vertical direction than a maximum height of the first wire in a vertical direction, and an upper surface of a lowermost fourth chip at a lowest end among the plurality of fourth chips is at a higher level in the vertical direction than a maximum height of the third wire in the vertical direction (Park’18 Fig. 1, Park’17 Fig. 1A – Simply duplication the arrangement of Park’18 as modified by Park’17 (as applied as addressed above and regarding claim 1, would meet the scope of the claim. See below for further clarity.).
To clearly demonstrate the proposed modification, Figure 1A of Park’17 has been modified (shown below). Park’17 discloses offset stacked memory chips; increasing memory capacity by adding stacks is an obvious design choice, as taught by Ng. Consequently, duplicating the arrangement in Park’17 Fig. 1A directly results in the claimed arrangement and orientation of the invention.
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Park’18 as modified by Park’17 discloses offset stacked chips for memory. Modifying this structure by adding additional stacks to increase memory capacity is an obvious design choice in view of Ng, as established above. Simply duplicating the arrangement shown in Park’17 Fig. 1A yields the configuration claimed.
CLAIM 12. Park’18 in view of Park’17 in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction, and at least a portion of an upper surface of the lowermost third chip overlaps the fourth chip stacked structure in the vertical direction (Park 18 – Fig. 1 & Park’17 – Fig. 1A).
CLAIM 13. Park’18 in view of Park’17 in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the first direction and the second direction are in opposite directions to each other (Park 18 – Fig. 1 & Park’17 – Fig. 1A – Note: This limitation is not understood to provide any further distinction. The particular arrangements and orientation are addressed with respect to claim 11, taking these directions in to consideration. See Modified Figure 1A of Park’17 as discussed regarding claim 11.).
CLAIM 14. Park’18 in view of Park’17 in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the first direction and the second direction are substantially identical directions (Park 18 – Fig. 1 & Park’17 – Fig. 1A – Note: This limitation is not understood to provide any further distinction. The particular arrangements and orientation are addressed with respect to claim 11, taking these directions in to consideration. See Modified Figure 1A of Park’17 as discussed regarding claim 11.).
CLAIM 15. Park’18 in view of Park’17 in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the lowermost second chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost second chip in the vertical direction is greater than a maximum height of the lowermost first wire in the vertical direction, and wherein the lowermost fourth chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost fourth chip in the vertical direction is greater than a maximum height of the lowermost third wire in the vertical direction (Park 18 – Fig. 1 demonstrates known height variations and relationships between adjacent chip stacks. & Park’17 – Fig. 1A demonstrates the capable orientation and location of a lowermost wiring therebetween.).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] in view of Park et al. (US 20170125378 A1) [Park’17] in view of Ng et al. (US 10312219 B2) in view of Tai et al. (US 11309281 B2).
CLAIM 16. . Park’18 in view of Park’17 in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the second chip stacked structure further comprises a first spacer on the upper surface of the first substrate, and the lowermost second chip is arranged on an upper surface of the first spacer, and wherein the fourth chip stacked structure further comprises a second spacer on the upper surface of the first substrate, and the lowermost fourth chip is arranged on an upper surface of the second spacer (Park 18 – Fig. 1 demonstrates known height variations and relationships between adjacent chip stacks, and the use of spacers. & Park’17 – Fig. 1A demonstrates the capable orientation and location of a lowermost wiring therebetween.).
While Park’18 discloses an active chip 210 at the base of the stack, it provides the physical thickness and structural support required for the assembly. A PHOSITA would find it a matter of routine design choice to substitute this active chip with a non-active spacer of the same dimensions when electrical connectivity is not required at the level (MPEP ¶2144.04: Omission of an Element and its Function – Under this guidance, if the prior art uses an active chip that that provides both electronic function and physical spacing, it is a predictable variation to omit the electronic function while retaining the mechanical structure.)
The substitution represents a predictable variation of known elements to achieve the same mechanical standoff. Selecting a spacer instead of a chip to provide vertical clearance yields no unexpected results or synergistic benefit, as both components occupy the same footprint to maintain the physical geometry of the stack.
For further support, se Tai Fig. 3A-3B which depicts the obvious predictable variation of Park’17. Figs. 3A-B of Tai depicts the analogous chip stacks as claimed and shown in Park’17, but further imply swaps the lower most chip in Fig. 3B with a spacer 340 in Fig. 3A to provide desired standoff in the arrangement.
Further, simple duplication of parts to increase memory, would be expected to enable the additional stacks (third and fourth) as addressed with respect to claim 11 in view of Ng. Simple duplication for increased memory, would also be capable of comprising the spacers as claimed.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] in view of Park et al. (US 20170125378 A1) [Park’17] in view of Ng et al. (US 10312219 B2) in view of Tai et al. (US 11309281 B2) in view of Lee et al. (US 20180342481 A1).
CLAIM 17. Park’18 in view of Park’17 in view of Ng et al. in view of Tai et al. teach the semiconductor package as claimed in claim 16, however may be silent upon the capability of wherein a width of the first spacer in a first horizontal direction is less than a width of the lowermost second chip in the first horizontal direction, and thereby also a width of the second spacer in the first horizontal direction is less than a width of the lowermost fourth chip in the first horizontal direction. Although Park’18 or Park’17 may not explicitly state that the first spacer’s width is less than the lowermost second chip’s width, this specific dimensioning was a routine design choice and obvious modification for a PHOSITA at the time of the invention. Adjusting chip sizes (thickness and width) in stacked arrangements to meet design needs was conventional knowledge. as confirmed by Lee et al. (¶[0036])3, which teaches that chips within a stack can vary in size.
Such dimensional configuration was a routine design choice and obvious modification for a PHOSITA at the time of the invention. It was well-known in the art that stacked chips could vary in thickness and width, as corroborated by Lee et al., first and second chips constituting a stack can have different sizes, thicknesses, and widths, and that these, optionally, can be the same. Therefore, adjusting these dimensions to meet specific design requirements was well within the ordinary skill of a PHOSITA.
CLAIM 18. Park’18 in view of Park’17 in view of Ng et al. in view of Tai et al. in view of Lee et al. teach a semiconductor package comprising:
a first substrate 200 having an upper surface and a lower surface opposite to the upper surface, the first substrate including a plurality of substrate pads arranged on the upper surface (Park’18 & Park’17);
an external connection terminal 120&130 arranged under the lower surface of the first substrate (Park’18 Fig. 1 – Demonstrates known convention of BGA connections/interface below a substrate.);
a first chip stacked structure including a plurality of first chips mounted on the upper surface of the first substrate and offset-stacked in a first direction, and first chip pads each being arranged on a region upwardly exposed on an upper surface of each of the plurality of first chips(Park’18 & Park’17);
a lowermost first wire electrically connecting a lowermost first chip at a lowermost end among the plurality of first chips to a substrate pad arranged adjacent to the lowermost first chip (Park’18 & Park’17);
a second chip stacked structure mounted on the upper surface of the first substrate and spaced apart in a horizontal direction from the first chip stacked structure with the first wire therebetween (Park’18 as modified by Park’17 – Park’17 demonstrates the orientation/arrangement and the wiring located between.); the second chip stacked structure including a plurality of second chips offset-stacked in the first direction, and second chip pads each arranged on a region upwardly exposed on an upper surface of each of the plurality of second chips (Park’18 & Park’17);
a third chip stacked structure including a plurality of third chips mounted on the upper surface of the first substrate and offset-stacked in a second direction (Park’18 & Park’17 as modified by Ng. Ng discloses the known modification to provide a third and fourth offset chip stack on the same substrate.), and third chip pads each arranged on a region upwardly exposed on an upper surface of each of the plurality of third chips (Park’18 Fig. 1 as modified by Park’17 Fig. 1A & Ng figs. 5-7);
a lowermost third wire electrically connecting a lowermost third chip at a lowermost end among the plurality of third chips to the substrate pad arranged adjacent to the lowermost third chip (Park’18 Fig. 1 as modified by Park’17 Fig. 1A & Ng figs. 5-7); and
a fourth chip stacked structure including a plurality of fourth chips mounted on the upper surface of the first substrate, spaced apart in the horizontal direction from the third chip stacked structure with the third wire therebetween (Park’18 Fig. 1 as modified by Park’17 Fig. 1A & Ng figs. 5-7. Note: See regarding claim 11 for modified Fig. 1A of Park’17 demonstrating a generic duplication of parts a PHOSITA would arrive at meeting the scope of the claim, in order to increase memory capacity.), and offset-stacked in the second direction, and third chip pads each arranged on a region upwardly exposed on an upper surface of each of the plurality of fourth chips, wherein:
an upper surface of a lowermost second chip at a lowest end among the plurality of second chips is at a higher vertical direction level than a maximum height of the first wire in the vertical direction (Park’18 – Adjacent chip stacks are known to have different heights as shown, resulting in the claimed relative height relationships as recited.), an upper surface of a lowermost fourth chip at a lowest end among the plurality of fourth chips is at a higher level in the vertical direction than a maximum height of the third wire in the vertical direction, at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction, and at least a portion of an upper surface of the lowermost third chip overlaps the fourth chip stacked structure in the vertical direction (Park’18 – Adjacent chip stacks are known to have different heights as shown, resulting in the claimed relative height relationships as recited. Simple duplication of parts for increased memory capacity resulting in the claimed structure would be obvious to a PHOSITA. Duplication as recited will result in two adjacent stacks, each having the recited height relationships as demonstrated in Park’18 fig. 1.).
Further, the combination of Park ’18, Park’17, and Ng teach the substrate and the duplication of parts (multiple chip stacks [Ng] with relative stepped stack direction [Park’18 & Park’17]) to increase capacity and channels. It would have been further obvious to incorporate the teaching of Tai and Lee because, as taught in Lee ¶[0036], chips may have a different size (i.e., a different thickness and/or a different width, necessitating the use of spacers to adjust thickness (as taught by Tai) to maintain the structural integrity of a stack arrangements. Therefore, the references are included to provide a complete teaching of the claimed semiconductor package as best understood..
CLAIM 19. Park’18 in view of Park’17 in view of Ng et al. in view of Tai et al. in view of Lee et al. teach a semiconductor package as claimed in claim 18, wherein: the lowermost second chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost second chip in the vertical direction is greater than a maximum height of the lowermost first wire in the vertical direction, and the lowermost fourth chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost fourth chip in the vertical direction is greater than a maximum height of the lowermost third wire in the vertical direction (Park’18 – Adjacent chip stacks are known to have different heights as shown, resulting in the claimed relative height relationships as recited. Simple duplication of parts for increased memory capacity resulting in the claimed structure would be obvious to a PHOSITA. Duplication as recited will result in two adjacent stacks, each having the recited height relationships as demonstrated in Park’18 fig. 1.),
CLAIM 20. Park’18 in view of Park’17 in view of Ng et al. in view of Tai et al. in view of Lee et al. teach a semiconductor package as claimed in claim 18, wherein: the second chip stacked structure further comprises a first spacer on the upper surface of the first substrate, and the lowermost second chip is arranged on an upper surface of the first spacer, and the fourth chip stacked structure further comprises a second spacer on the upper surface of the first substrate, and the lowermost fourth chip is arranged on an upper surface of the second spacer.
(Park 18 – Fig. 1 demonstrates known height variations and relationships between adjacent chip stacks, and the use of spacers. & Park’17 – Fig. 1A demonstrates the capable orientation and location of a lowermost wiring therebetween.).
While Park’18 discloses an active chip 210 at the base of the stack, it provides the physical thickness and structural support required for the assembly. A PHOSITA would find it a matter of routine design choice to substitute this active chip with a non-active spacer of the same dimensions when electrical connectivity is not required at the level (MPEP ¶2144.04: Omission of an Element and its Function – Under this guidance, if the prior art uses an active chip that that provides both electronic function and physical spacing, it is a predictable variation to omit the electronic function while retaining the mechanical structure.)
The substitution represents a predictable variation of known elements to achieve the same mechanical standoff. Selecting a spacer instead of a chip to provide vertical clearance yields no unexpected results or synergistic benefit, as both components occupy the same footprint to maintain the physical geometry of the stack.
For further support, se Tai Fig. 3A-3B which depicts the obvious predictable variation of Park’17. Figs. 3A-B of Tai depicts the analogous chip stacks as claimed and shown in Park’17, but further imply swaps the lower most chip in Fig. 3B with a spacer 340 in Fig. 3A to provide desired standoff in the arrangement.
Further, simple duplication of parts to increase memory, would be expected to enable the additional stacks (third and fourth) as addressed with respect to claim 11 in view of Ng. Simple duplication for increased memory, would also be capable of comprising the spacers as claimed.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/18/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Lee et al. - ¶[0036] - The first chips 210 constituting the first chip stack 200 may have the same size (i.e., the same thickness and the width) and the same function. Alternatively, at least one of the first chips 210 constituting the first chip stack 200 may have a different size (i.e., a different thickness and/or a different width) and a different function from the other chips of the first chips 210. The second chips 310 constituting the second chip stack 300 may have the same size (i.e., the same thickness and the width) and the same function. Alternatively, at least one of the second chips 310 constituting the second chip stack 300 may have a different size (i.e., a different thickness and/or a different width) and a different function from the other chips of the second chips 310. In some embodiments, the first and second chips 210 and 310 may have the same size (i.e., the same thickness and the width) and the same function. In such a case, each of the first and second chips 210 and 310 may be a memory chip in which memory cells are integrated.
2 Ng et al. – “(21) As set forth above, the semiconductor dies in a semiconductor device assembly can include dies that provide a variety of different functions (e.g., logic, memory, sensors, etc.). In an embodiment in which stacks of shingled memory dies are included in a semiconductor device assembly, an advantage of including multiple stacks of memory dies is the possibility to dedicate different stacks of memory dies to different memory channels (e.g., in a one-to-one relationship where each stack corresponds to one channel, or in an n-to-one or one-to-n relationship in which multiple stacks correspond to each channel, or even multiple channels to each stack).”
3 Lee et al. - ¶[0036] - The first chips 210 constituting the first chip stack 200 may have the same size (i.e., the same thickness and the width) and the same function. Alternatively, at least one of the first chips 210 constituting the first chip stack 200 may have a different size (i.e., a different thickness and/or a different width) and a different function from the other chips of the first chips 210. The second chips 310 constituting the second chip stack 300 may have the same size (i.e., the same thickness and the width) and the same function. Alternatively, at least one of the second chips 310 constituting the second chip stack 300 may have a different size (i.e., a different thickness and/or a different width) and a different function from the other chips of the second chips 310. In some embodiments, the first and second chips 210 and 310 may have the same size (i.e., the same thickness and the width) and the same function. In such a case, each of the first and second chips 210 and 310 may be a memory chip in which memory cells are integrated.