Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments directed to amended claim 1 & 11 filed 6/24/2026 have been fully considered but they are not persuasive.
Regarding Claim 1: Applicant’s traversal relies on a hypothetical mirror-reversal layout of their own design rather than the actual structural layout of the applied art. As demonstrated in Figure 1C of the secondary reference Park’17, positioning two chip stacks offset-stacked in the identical direction inherently results in an uppermost chip that overhangs and vertically overlaps at least two chips of the adjacent stack within an open-ended "comprising" claim scope. Furthermore, modifying the vertical level of the lowermost second chip's upper surface to be higher than the peak of the adjacent lowermost wire loop is a matter of routine design choice and inherent structural necessity; ensuring adequate vertical loop profile clearance is the standard engineering method required to provide mechanical clearance and prevent the overhanging chip/die from physically short-circuiting or crushing the underlying wire.
Regarding Claim 11: Applicant argues that the prior art fails to teach a single chip stacked structure consisting of memory chips where the lowermost chip has a greater vertical thickness than the remaining chips in that same stack. However, Park'18 explicitly teaches the core concept of varying chip thicknesses (D32B vs. D32T) within a semiconductor package in Fig. 3.
PNG
media_image1.png
336
478
media_image1.png
Greyscale
To the extent that Applicant contends Park'18 does not explicitly disclose a single stack where the lowermost chip is specifically thicker than the memory chips stacked on top of it, Tai (US 11,309,281 B2) explicitly bridges this gap. As shown in Figure 3A and Column 4 lines 59-601 of Tai, a baseline structural block or spacer positioned directly underneath the bottommost die of a cascading chip stack can explicitly comprise a "memory die." It would have been a matter of routine design choice and standard engineering practice for a person having ordinary skill in the art to incorporate the explicit thickness variations of Park '18 with the memory stack configuration of Tai. Doing so explicitly demonstrates the claimed concept of a thicker lowermost memory die utilized to optimize structural rigidity, mechanical support, and baseline stability at the bottom of a high-density memory stack.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Allowable Subject Matter
Claims 9, 6-7,10 are allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation “the second sidewall of the first spacer and the second sidewall of the lowermost second chip are coplanar”, in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Tai et al. (US 11309281 B2).
PNG
media_image2.png
470
734
media_image2.png
Greyscale
CLAIM 1: Park’18 teaches a semiconductor package comprising:
a first substrate 100 having an upper surface 101 and a lower surface 102 opposite to the upper surface, and including a substrate pad 111&113 arranged on the upper surface 101;
a first chip stacked structure 300 mounted on the upper surface of the first substrate 100, the first chip stacked structure 300 including a plurality of first chips [310+320+330+340] offset-stacked in a first direction (Fig. 1), each of the plurality of first chips being a memory chip (Park’18 (¶22) discloses the use of memory chips. The specific type of chip integrated into the package is a routine design choice. It does not alter the claimed package structure or physical arrangement. A PHOSITA would readily recognize this and be able to select the appropriate chip type to achieve the desired package functionality);
a lowermost first wire 301E electrically connecting a lowermost first chip 210 at a lowermost end among the plurality of first chips to the substrate pad 113 the lowermost chip mounted on the upper surface of the first substrate with no chip or substrate between the lowermost first chip and the first substrate (Fig. 1); and
a second chip stacked structure 200 mounted on the upper surface 101 of the first substrate 100, the second chip stacked structure 200 including a plurality of second chips [0310+320+330+340]offset- stacked in the first direction each chip of the plurality of second chips being a memory chip (Park’18 (¶22) discloses the use of memory chips. The specific type of chip integrated into the package is a routine design choice. It does not alter the claimed package structure or physical arrangement. A PHOSITA would readily recognize this and be able to select the appropriate chip type to achieve the desired package functionality); wherein the second chip stacked structure 200 is spaced apart from the first chip stacked structure 300 and wherein an upper surface 511 of a lowermost second chip at a lowest end among the plurality of second chips is at a higher level (Chips of second stack may have a greater thickness D1 than the small thickness D2, thereby the surface may be at a higher level.) in a vertical direction than a highest level of the lowermost first wire 301E in the vertical direction, wherein the lowermost second chip is mounted on the upper surface of the first substate with no other chip or substrate between the lowermost second chip and the first substrate (Fig. 1).
Park’18 merely shows an outwardly arranged wire configuration, stacking of opposing offset directions, and it is silent regarding the placement of the lowermost wire between chip stacks. However, positioning wires between stacked chips, and orienting in the same offset direction, as shown in Park’17 Fig. 1, was a known, functional alternative.
PNG
media_image3.png
464
520
media_image3.png
Greyscale
PNG
media_image4.png
464
520
media_image4.png
Greyscale
Park’17 Fig. 1 explicitly teaches arranging the lowermost wire 207 between chip stacks arranged in the same offset direction.
As further demonstrated in Figure 1C of Park’17, positioning two chip stacks offset-stacked in the identical direction is understood to result in an uppermost chip that overhangs and vertically overlaps at least two chips of the adjacent stack within an open-ended "comprising" claim scope.
PNG
media_image5.png
370
516
media_image5.png
Greyscale
Furthermore, modifying the vertical level of the lowermost second chip's upper surface to be higher than the peak of the adjacent lowermost wire loop is a matter of routine design choice and inherent structural necessity; ensuring adequate vertical loop profile clearance is the standard engineering method required to provide mechanical clearance and prevent the overhanging chip/die from physically short-circuiting or crushing the underlying wire. As shown in Park’18, having chips of different thickness in the first and second stacks is a known way of providing appropriate height clearances of adjacent stacks which may overlap.
It would be obvious to a PHOSITA to apply this known arrangement to Park’18 for footprint optimization. Such a modification constitutes a predictable, routine optimization yielding no unexpected results. Utilizing Park’17's teaching to modify Park’18's arrangement to place wires between chips represents a predictable, optimizing choice that yields no unexpected benefits, making the modification obvious to a PHOSITA (MPEP §2144.04).
CLAIM 2. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 1, wherein a thickness D1 of the lowermost second chip in the vertical direction is greater than a distance D2 between the maximum height of the lowermost first wire and the upper surface of the first substrate in the vertical direction (Park’18 – Fig. 1 – The relative distances and chip thicknesses/height is a understood optimizable parameter, understood to optimized footprint, packing density and allowance for optimal clearances of overlapping chips and connection wiring as addressed regarding claim 1.)).
CLAIM 4. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 2, wherein at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction (Park’18 – Fig. 1 & Park’17 – Fig. 1A)
CLAIM 5. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 1, wherein the lowermost second chip has a different thickness in the vertical direction than remaining second chips of the plurality of second chips (Park’18 – Fig. 1 – The relative distances and chip thicknesses/height is a understood optimizable parameter, understood to optimized footprint, packing density and allowance for optimal clearances of overlapping chips and connection wiring as addressed regarding claim 1.)).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Zhou et al. (US 20210375848 A1).
CLAIM 3. Park’18 in view of Park’17 teach the semiconductor package as claimed in claim 2, however are silent upon wherein the thickness of the lowermost second chip in the vertical direction is in a range of about 500 to about 1000 micrometers. Zhou et al. ¶31 teaches chips stacked as claimed were known to have thickness within the claimed range. As such, it would be obvious to a PHOSITA to select chips having conventional thicknesses for the device.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180254261 A1) [Park’18] n view of Park et al. (US 20170125378 A1) [Park’17] in view of Tai et al. (US 11309281 B2) in view of Ng et al. (US 10312219 B2).
CLAIM 11. Park’18 in view of Park’17 teach the semiconductor package comprising:
a first substrate 200 having an upper surface and a lower surface, the lower surface being opposite to the upper surface, a plurality of substrate pads 111&113 arranged on the upper surface (Park’18 Fig. 1);
a first chip stacked structure mounted on the upper surface of the first substrate, the first chip stacked structure including a plurality of first chips offset-stacked in a first direction (Park’18 Fig. 1);
a lowermost first wire electrically connecting a lowermost first chip at a lowermost end among the plurality of first chips to a substrate pad of the plurality of substrate pads, the substrate pad arranged adjacent to the lowermost first chip (Park’18 Fig. 1);
a second chip stacked structure mounted on the upper surface of the first substrate and apart from the first chip stacked structure with the lower most first wire therebetween in a horizontal direction (Park’18 as modified by Park’17 demonstrating the relative armament and known capability. See regarding claim 1 addressing the relative chip/wiring orientation/location modification of Park’18 in view of Park’17.), the second chip stacked structure consisting of a plurality of second chips offset-stacked in the first direction (Park’18 Fig. 1 and Park’17 Fig. 1A),
wherein the plurality of first chips, the plurality of second chips are memory chips (Park’18 teaches that the chips may be memory chips. However, the operation of these chips does not provide a significant structural distinction in the claimed package. Selecting chips to achieve specific operations or functionalities represents an obvious design choice for a PHOSITA and does not significantly modify the package structure over the prior art.) and a thickness of the lower most chip 3200B in the vertical direction is greater than the thickness of the other second chips 3200T. It is note, Park'18 explicitly teaches the core concept of varying chip thicknesses (D32B vs. D32T) within a semiconductor package in Fig. 3.
PNG
media_image1.png
336
478
media_image1.png
Greyscale
To the extent that Park'18 does not explicitly disclose a single stack where the lowermost chip is specifically thicker than the memory chips stacked on top of it, Tai explicitly bridges this gap. As shown in Figure 3A and Column 4 lines 59-602 of Tai, a baseline structural block or spacer positioned directly underneath the bottommost die of a cascading chip stack can explicitly comprise a "memory die." It would have been a matter of routine design choice and standard engineering practice for a person having ordinary skill in the art to incorporate the explicit thickness variations of Park '18 with the memory stack configuration of Tai. Doing so explicitly demonstrates the claimed concept of a thicker lowermost memory die utilized to optimize structural rigidity, mechanical support, and baseline stability at the bottom of a high-density memory stack. As such, modifying a offset chip stack to have only the lowermost chip thicker than the overlying second chips would be a routing modification and optimization to a PHOSITA at the time of the invention to provide clearance to an adjacent offset chip stack of which it may overlap.
While Park’17 and Park’18 lack explicit disclosure of the third chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of third chips offset-stacked in a second direction, adding such structures is a known, predictable modification for increasing performance (MPEP § 2144.04, Multiplication/ Duplication of Parts). Ng, Figures 5–7 & Col. 4 line 64 -Col. 5 line 8, teaches horizontally spaced, offset-stacked chips, in order to improve device performance3, making its application to Park’17/18 a trivial optimization of design constraints or mere rearrangement of existing, known components. Ng teaches, individual stacks of chips allows for increased memory and dedicated stacks of memory to different memory channels thereby improving operation and performance of the memory device.
PNG
media_image6.png
682
548
media_image6.png
Greyscale
Therefore, a PHOSIA would find it obvious to apply Ng’s teachings to Park’17/18, arranging additional stacks to meet design constraints such as meeting number of channels and optimizing performance (MPEP § 2144.04, Design Choice Optimization & Rearrangement of Parts).
Further additional offset chip stacks would be expected to further comprise, a lowermost third wire electrically connecting a lowermost third chip at a lowermost end among the plurality of third chips to the substrate pad arranged adjacent to the lowermost third chip (Park’18 Fig. 1, Park’17 Fig. 1A & Ng figs 5-7); and a fourth chip stacked structure mounted on the upper surface of the first substrate and spaced apart from the third chip stacked structure with the third wire therebetween in the horizontal direction (Park’18 Fig. 1, Park’17 Fig. 1A – Simply duplication the arrangement of Park’18 as modified by Park’17 (as applied as addressed above and regarding claim 1, would meet the scope of the claim. See below for further clarity.), the fourth chip stacked structure including a plurality of fourth chips offset-stacked in the second direction, wherein an upper surface of a lowermost second chip at a lowest end among the plurality of second chips is at a higher level in a vertical direction than a maximum height of the first wire in a vertical direction, and an upper surface of a lowermost fourth chip at a lowest end among the plurality of fourth chips is at a higher level in the vertical direction than a maximum height of the third wire in the vertical direction (Park’18 Fig. 1, Park’17 Fig. 1A – Simply duplication the arrangement of Park’18 as modified by Park’17 (as applied as addressed above and regarding claim 1, would meet the scope of the claim. See below for further clarity.).
To clearly demonstrate the proposed modification, Figure 1A of Park’17 has been modified (shown below). Park’17 discloses offset stacked memory chips; increasing memory capacity by adding stacks is an obvious design choice, as taught by Ng. Consequently, duplicating the arrangement in Park’17 Fig. 1A directly results in the claimed arrangement and orientation of the invention.
PNG
media_image7.png
390
482
media_image7.png
Greyscale
Park’18 as modified by Park’17 discloses offset stacked chips for memory. Modifying this structure by adding additional stacks to increase memory capacity is an obvious design choice in view of Ng, as established above. Simply duplicating the arrangement shown in Park’17 Fig. 1A yields the configuration claimed.
CLAIM 12. Park’18 in view of Park’17 in view of Tai in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein at least a portion of an upper surface of the lowermost first chip overlaps the second chip stacked structure in the vertical direction, and at least a portion of an upper surface of the lowermost third chip overlaps the fourth chip stacked structure in the vertical direction (Park 18 – Fig. 1 & Park’17 – Fig. 1A).
CLAIM 13. Park’18 in view of Park’17 in view of Tai in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the first direction and the second direction are in opposite directions to each other (Park 18 – Fig. 1 & Park’17 – Fig. 1A – Note: This limitation is not understood to provide any further distinction. The particular arrangements and orientation are addressed with respect to claim 11, taking these directions in to consideration. See Modified Figure 1A of Park’17 as discussed regarding claim 11.).
CLAIM 14. Park’18 in view of Park’17 in view of Tai in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the first direction and the second direction are substantially identical directions (Park 18 – Fig. 1 & Park’17 – Fig. 1A – Note: This limitation is not understood to provide any further distinction. The particular arrangements and orientation are addressed with respect to claim 11, taking these directions in to consideration. See Modified Figure 1A of Park’17 as discussed regarding claim 11.).
CLAIM 15. Park’18 in view of Park’17 in view of Tai in view of Ng et al. teach the semiconductor package as claimed in claim 11, wherein the lowermost second chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost second chip in the vertical direction is greater than a distance between a maximum height of the lowermost first wire and the upper surface of the first substrate in the vertical direction, and wherein the lowermost fourth chip is arranged on the upper surface of the first substrate, and a thickness of the lowermost fourth chip in the vertical direction is greater than a distance between the maximum height of the lowermost third wire and the top surface of the first substrate in the vertical direction (Park 18 – Fig. 1 demonstrates known height variations and relationships between adjacent chip stacks. & Park’17 – Fig. 1A demonstrates the capable orientation and location of a lowermost wiring therebetween.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/8/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Tai et al. – “includes a spacer 340 (e.g., dielectric spacer, controller die, logic die, memory die, or any other suitable structure). The spacer 340 can be disposed at any suitable location within the second stack 303.”
2 Tai et al. – “includes a spacer 340 (e.g., dielectric spacer, controller die, logic die, memory die, or any other suitable structure). The spacer 340 can be disposed at any suitable location within the second stack 303.”
3 Ng et al. – “(21) As set forth above, the semiconductor dies in a semiconductor device assembly can include dies that provide a variety of different functions (e.g., logic, memory, sensors, etc.). In an embodiment in which stacks of shingled memory dies are included in a semiconductor device assembly, an advantage of including multiple stacks of memory dies is the possibility to dedicate different stacks of memory dies to different memory channels (e.g., in a one-to-one relationship where each stack corresponds to one channel, or in an n-to-one or one-to-n relationship in which multiple stacks correspond to each channel, or even multiple channels to each stack).”
Prosecution Insights