DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A, sub-species i in the reply filed on April 13, 2026 is acknowledged.
Claims 9-11 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 13, 2026.
It is noted for clarity of the record that claim 10 requires a conductive plug connected to a bit line extending along a second lateral direction. This appears to be drawn to Fig 3C and 3D, wherein there is a bit line contact 365 connected to a bit line 360 and the vertical semiconductor portion 324 is laterally surrounded by the vertical gate dielectric portion. The bit line extending along a second lateral direction ([0076] of disclosure). However, elected species A, sub-species i, as drawn to Figs 2A and 2C has the 12, has the vertical gate dielectric portion laterally surrounded by vertical semiconductor portion 224.
Claim 11 would also be withdrawn since it is dependent on claim 10.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 an 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the claim recites the limitation "the bit line" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “one of the bit lines.”
Regarding claim 14, the claim recites the limitation " one of the vertical transistors" in lines 8-9. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “one of the plurality of vertical transistors.”
Claims 15-17 would also be rejected since they are dependent on claim 14.
Regarding claim 15, the claim recites the limitation "the bit line" in line 2 and “each vertical transistor” in line 2. There is insufficient antecedent basis for these limitations in the claim. For purposes of examination, Examiner will interpret the first limitation to mean “one of the plurality of bit lines.” For purposes of examination, Examiner will interpret the second limitation to mean “each of the plurality of vertical transistors.”
Claims 16-17 would also be rejected since they are dependent on claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Atanasov et. al. (US 20220189913 A1), hereinafter Atanasov.
Regarding claim 1, Atanasov teaches a semiconductor device (Fig 1 IC structure 100, [0016]), comprising: a plurality of vertical transistors (Fig 1 transistor 104, [0016]) each comprising: a semiconductor layer (Fig 1 channel material 120, [0020]) having a leakage value lower than a pico-ampere (See note below) and comprising a vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]) and at least one lateral semiconductor portion (Fig 1 lateral portion of channel material 120 on capacitor 106, [0020]), a gate dielectric layer (Fig 1 gate dielectric 122, [0017]) comprising a vertical gate dielectric portion (Fig 1 vertical portion of gate dielectric 122, [0017]) on the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]) and extending in the vertical direction (Fig 1), a gate electrode (Fig 1 gate electrode 124, [0017]) on the gate dielectric layer (Fig 1 gate dielectric 122, [0017]) and separated from (Fig 1) the semiconductor layer (Fig 1 channel material 120, [0020]) by the gate dielectric layer (Fig 1 gate dielectric 122, [0017]); and a plurality of capacitors (Fig 1 capacitors 106, [0017]) each coupled with ([0016]) the semiconductor layer (Fig 1 channel material 120, [0020]) of a corresponding one of the plurality of vertical transistors (Fig 1 transistor 104, [0016]).
Regarding the leakage value, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 2, Atanasov teaches the gate electrode (Fig 1 gate electrode 124, [0017]) extends along the vertical direction (Fig 1), and is laterally surrounded (Fig 1) by the vertical gate dielectric portion (Fig 1 vertical portion of gate dielectric 122, [0017]).
Regarding claim 3, Atanasov teaches the vertical gate dielectric portion (Fig 1 vertical portion of gate dielectric 122, [0017]) is laterally surrounded by (Fig 1) the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]).
Regarding claim 4, Atanasov teaches the gate dielectric layer (Fig 1 gate dielectric 122, [0017]) further comprises a lateral gate dielectric portion (Fig 1 lateral portion of gate dielectric 122, [0017]) in contact with a first end (Fig 1 bottom of gate electrode 124) of the gate electrode (Fig 1 gate electrode 124, [0017]).
Regarding claim 5, Atanasov teaches a first lateral semiconductor portion (Fig 1 lateral portion of channel material 120 on capacitor 106, [0020]) is between (Fig 1) the lateral gate dielectric portion (Fig 1 lateral portion of gate dielectric 122, [0017]) and one corresponding capacitor (Fig 1 corresponding capacitor 106, [0017]).
Regarding claim 6, Atanasov teaches word lines (Fig 1 memory control line 128, [0017]) each extending along a first lateral direction (Fig 4 up/down) and connected to second ends (Fig 1 top of gate electrode 124) of the gate electrodes (Fig 1 gate electrode 124, [0017]).
Regarding claim 7, Atanasov teaches bit lines (Fig 1 memory control line 126, [0017]) each extending along a second lateral direction (Fig 4 left/right) and in direct contact (Fig 1) with the vertical semiconductor portions (Fig 1 vertical portion of channel material 120, [0020]).
Regarding claim 12, Atanasov fails to teach the leakage value of the semiconductor layer is lower than an intrinsic leakage value of monocrystalline silicon.
However, in support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 13, Atanasov teaches the semiconductor layer (Fig 1 channel material 120, [0020]) is a metal oxide semiconductor layer (indium gallium zinc oxide IGZO, [0020]).
Regarding claim 14, Atanasov teaches a semiconductor device (Fig 1 IC structure 100, [0016]), comprising: a plurality of vertical transistors (Fig 1 transistor 104, [0016]) each comprising: a gate electrode (Fig 1 gate electrode 124, [0017]) extending in a vertical direction (Fig 1 up/down), a gate dielectric layer (Fig 1 gate dielectric 122, [0017]) laterally surrounding (Fig 1) the gate electrode (Fig 1 gate electrode 124, [0017]) and covering a first end of the gate electrode (Fig 1 gate electrode 124, [0017]), a semiconductor layer (Fig 1 channel material 120, [0020]) laterally surrounding the gate dielectric layer (Fig 1 gate dielectric 122, [0017]) and covering a first end (Fig 1 bottom of gate electrode 124) of the gate dielectric layer (Fig 1 gate dielectric 122, [0017]); a plurality of capacitors (Fig 1 capacitors 106, [0017]) each coupled ([0016]) with the semiconductor layer (Fig 1 channel material 120, [0020]) of a corresponding one of the vertical transistors (Fig 1 transistor 104, [0016]); a plurality of word lines (Fig 1 memory control line 128, [0017]) each extending along a first lateral direction (Fig 4 up/down) and coupled with the gate electrodes (Fig 1 gate electrode 124, [0017]); and a plurality of bit lines (Fig 1 memory control line 126, [0017]) each extending along a second lateral direction (Fig 4 left/right) and coupled with the semiconductor layers (Fig 1 channel material 120, [0020]).
Regarding claim 15, Atanasov teaches the bit line (Fig 1 memory control line 126, [0017]) at least partially surrounds (Fig 4 fully surrounds) the semiconductor layer (Fig 1 channel material 120, [0020]) of each vertical transistor (Fig 1 transistor 104, [0016]) in a lateral plane (Fig 4 planar view).
Regarding claim 16, Atanasov fails to teach the leakage value of the semiconductor layer is lower than an intrinsic leakage value of monocrystalline silicon.
However, in support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 17, Atanasov teaches the semiconductor layer (Fig 1 channel material 120, [0020]) is a metal oxide semiconductor layer (indium gallium zinc oxide IGZO, [0020]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Atanasov et. al. (US 20220189913 A1), hereinafter Atanasov, in view of Yamazaki et. al. (US 20250015194 A1), hereinafter Yamazaki.
Atanasov teaches the bit line (Fig 1 memory control line 126, [0017]) fully surrounds (Fig 4) a sidewall (Fig 1 sidewall of vertical portion of channel material 120) of the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]) and in contact (Electrical contact) with a second lateral semiconductor portion.
Atanasov fails to teach the bit line in contact with a second lateral semiconductor portion.
However, Yamazaki teaches the bit line (Fig 27B conductive layer 240, [0338] corresponds to Atanasov: Fig 1 memory control line 126, [0017]) in contact (Electrical contact, [0338]) with a second lateral semiconductor portion (Fig 27B lateral top lateral portion of oxide semiconductor layer 230, [0338]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Atanasov to incorporate the teachings of Yamazaki by having a second lateral semiconductor portion. This would allow for an increase in contact area between the bit line and semiconductor portion to reduce the contact resistance between the two ([0338]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gomes et. al. (US 20230200075 A1) teaches a memory structure that meets the limitations along with different capacitor configurations.
Sung et. al. (US 20200411528 A1) teaches a memory structure wherein a dielectric material and semiconductor material extend above a top surface of an insulating material that a transistor is made inside of. The amounts of extension is dependent on processing considerations.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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