DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed August 17, 2026, has been entered. Claims 1-17 and 21-23 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 12-17, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Atanasov et. al. (US 20220189913 A1), hereinafter Atanasov, in view of Yamazaki et. al. (US 20250015194 A1), hereinafter Yamazaki.
Regarding claim 1, Atanasov teaches a semiconductor device (Fig 1 IC structure 100, [0016]), comprising: a plurality of vertical transistors (Fig 1 transistor 104, [0016]) each comprising: a semiconductor layer (Fig 1 channel material 120, [0020]) having a leakage value lower than a pico-ampere (See note below) and comprising a vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]), a first lateral semiconductor portion (Fig 1 lateral portion of channel material 120 on capacitor 106, [0020])at a first end of the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]), a gate dielectric layer (Fig 1 gate dielectric 122, [0017]) comprising a vertical gate dielectric portion (Fig 1 vertical portion of gate dielectric 122, [0017]) on the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]) and extending in a vertical direction (Fig 1), and a gate electrode (Fig 1 gate electrode 124, [0017]) on the gate dielectric layer (Fig 1 gate dielectric 122, [0017]) and separated from (Fig 1) the semiconductor layer (Fig 1 channel material 120, [0020]) by the gate dielectric layer (Fig 1 gate dielectric 122, [0017]); and a plurality of capacitors (Fig 1 capacitors 106, [0017]) each coupled with ([0016]) the semiconductor layer (Fig 1 channel material 120, [0020]) of a corresponding one of the plurality of vertical transistors (Fig 1 transistor 104, [0016]).
Atanasov fails to teach a second lateral semiconductor portion at a second end of the vertical semiconductor portion.
However, Yamazaki teaches the bit line (Fig 25C conductive layer 240, [0338] corresponds to Atanasov: Fig 1 memory control line 126, [0017]) in contact (Electrical contact, [0338]) with a second lateral semiconductor portion (Fig 25C lateral top lateral portion of oxide semiconductor layer 230, [0338]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Atanasov to incorporate the teachings of Yamazaki by having a second lateral semiconductor portion. This would allow for an increase in contact area between the bit line and semiconductor portion to reduce the contact resistance between the two ([0338]).
Regarding the leakage value, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 2, Atanasov as modified in claim 1 teaches the gate electrode (Atanasov: Fig 1 gate electrode 124, [0017]) extends along the vertical direction (Atanasov: Fig 1), and is laterally surrounded (Atanasov: Fig 1) by the vertical gate dielectric portion (Atanasov: Fig 1 vertical portion of gate dielectric 122, [0017]).
Regarding claim 3, Atanasov as modified in claim 2 teaches the vertical gate dielectric portion (Atanasov: Fig 1 vertical portion of gate dielectric 122, [0017]) is laterally surrounded by (Atanasov: Fig 1) the vertical semiconductor portion (Atanasov: Fig 1 vertical portion of channel material 120, [0020]).
Regarding claim 4, Atanasov as modified in claim 3 teaches the gate dielectric layer (Atanasov: Fig 1 gate dielectric 122, [0017]) further comprises a lateral gate dielectric portion (Atanasov: Fig 1 lateral portion of gate dielectric 122, [0017]) in contact with a first end (Atanasov: Fig 1 bottom of gate electrode 124) of the gate electrode (Atanasov: Fig 1 gate electrode 124, [0017]).
Regarding claim 5, Atanasov as modified in claim 4 teaches the first lateral semiconductor portion (Atanasov: Fig 1 lateral portion of channel material 120 on capacitor 106, [0020]) is between (Atanasov: Fig 1) the lateral gate dielectric portion (Atanasov: Fig 1 lateral portion of gate dielectric 122, [0017]) and one corresponding capacitor (Atanasov: Fig 1 corresponding capacitor 106, [0017]).
Regarding claim 6, Atanasov as modified in claim 2 teaches word lines (Atanasov: Fig 1 memory control line 128, [0017]) each extending along a first lateral direction (Atanasov: Fig 4 up/down) and connected to second ends (Atanasov: Fig 1 top of gate electrode 124) of the gate electrodes (Atanasov: Fig 1 gate electrode 124, [0017]).
Regarding claim 7, Atanasov as modified in claim 3 teaches bit lines (Atanasov: Fig 1 memory control line 126, [0017]) each extending along a second lateral direction (Atanasov: Fig 4 left/right) and in direct contact (Atanasov: Fig 1) with the vertical semiconductor portions (Atanasov: Fig 1 vertical portion of channel material 120, [0020]).
Regarding claim 8, Atanasov as modified in claim 7 teaches one of the bit lines (Atanasov: Fig 1 memory control line 126, [0017]) fully surrounds (Atanasov: Fig 4) a sidewall (Atanasov: Fig 1 sidewall of vertical portion of channel material 120) of the vertical semiconductor portion (Atanasov: Fig 1 vertical portion of channel material 120, [0020]) and in contact (Electrical contact) with the second lateral semiconductor portion (Yamazaki: Fig 25C lateral top lateral portion of oxide semiconductor layer 230, [0338]).
Regarding claim 12, Atanasov as modified in claim 1 fails to teach the leakage value of the semiconductor layer is lower than an intrinsic leakage value of monocrystalline silicon.
However, in support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 13, Atanasov as modified in claim 1 teaches the semiconductor layer (Atanasov: Fig 1 channel material 120, [0020]) is a metal oxide semiconductor layer (Atanasov: indium gallium zinc oxide IGZO, [0020]).
Regarding claim 14, Atanasov teaches a semiconductor device (Fig 1 IC structure 100, [0016]), comprising: a plurality of vertical transistors (Fig 1 transistor 104, [0016]) each comprising: a gate electrode (Fig 1 gate electrode 124, [0017]) extending in a vertical direction (Fig 1 up/down), a gate dielectric layer (Fig 1 gate dielectric 122, [0017]) laterally surrounding (Fig 1) the gate electrode (Fig 1 gate electrode 124, [0017]) and covering a first end of the gate electrode (Fig 1 gate electrode 124, [0017]), and a semiconductor layer (Fig 1 channel material 120, [0020]) laterally surrounding the gate dielectric layer (Fig 1 gate dielectric 122, [0017]) and covering a first end (Fig 1 bottom of gate electrode 124) of the gate dielectric layer (Fig 1 gate dielectric 122, [0017]), the semiconductor layer (Fig 1 channel material 120, [0020]) comprising a vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]), a first lateral semiconductor portion (Fig 1 lateral portion of channel material 120 on capacitor 106, [0020]) at a first end of the vertical semiconductor portion (Fig 1 vertical portion of channel material 120, [0020]); a plurality of capacitors (Fig 1 capacitors 106, [0017]) each coupled ([0016]) with the semiconductor layer (Fig 1 channel material 120, [0020]) of a corresponding one of the plurality of vertical transistors (Fig 1 transistor 104, [0016]); a plurality of word lines (Fig 1 memory control line 128, [0017]) each extending along a first lateral direction (Fig 4 up/down) and coupled with the gate electrodes (Fig 1 gate electrode 124, [0017]); and a plurality of bit lines (Fig 1 memory control line 126, [0017]) each extending along a second lateral direction (Fig 4 left/right) and coupled with the semiconductor layers (Fig 1 channel material 120, [0020]).
Atanasov fails to teach a second lateral semiconductor portion at a second end of the vertical semiconductor portion.
However, Yamazaki teaches the bit line (Fig 25C conductive layer 240, [0338] corresponds to Atanasov: Fig 1 memory control line 126, [0017]) in contact (Electrical contact, [0338]) with a second lateral semiconductor portion (Fig 25C lateral top lateral portion of oxide semiconductor layer 230, [0338]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Atanasov to incorporate the teachings of Yamazaki by having a second lateral semiconductor portion. This would allow for an increase in contact area between the bit line and semiconductor portion to reduce the contact resistance between the two ([0338]).
Regarding claim 15, Atanasov as modified in claim 14 teaches one of the plurality of bit lines (Atanasov: Fig 1 memory control line 126, [0017]) at least partially surrounds (Atanasov: Fig 4 fully surrounds) the semiconductor layer (Atanasov: Fig 1 channel material 120, [0020]) of each of the plurality of vertical transistors (Atanasov: Fig 1 transistor 104, [0016]) in a lateral plane (Atanasov: Fig 4 planar view).
Regarding claim 16, Atanasov as modified in claim 15 fails to teach a leakage value of the semiconductor layer is lower than an intrinsic leakage value of monocrystalline silicon.
However, in support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01. In this case, the channel material may include IGZO ([0020]).
Regarding claim 17, Atanasov as modified in claim 15 teaches the semiconductor layer (Atanasov: Fig 1 channel material 120, [0020]) is a metal oxide semiconductor layer (Atanasov: indium gallium zinc oxide IGZO, [0020]).
Regarding claim 21, Atanasov as modified in claim 14 the gate dielectric layer (Atanasov: Fig 1 gate dielectric 122, [0017]) comprises: a first lateral gate dielectric portion (Atanasov: Fig 1 bottom of gate dielectric 122, [0017]) in contact with a first end of the gate electrode (Atanasov: Fig 1 gate electrode 124, [0017]); a vertical gate dielectric portion (Atanasov: Fig 1 vertical portion of gate dielectric 122, [0017]) surrounded by the vertical semiconductor portion (Atanasov: Fig 1 vertical portion of channel material 120, [0020]); and a second lateral gate dielectric portion (Yamazaki: Fig 25C lateral top lateral portion of insulating layer 250, [0255]; insulating layer 250 corresponds to Atanasov: gate dielectric 122) in contact with the second lateral semiconductor portion (Yamazaki: Fig 25C lateral top lateral portion of oxide semiconductor layer 230, [0338]; oxide semiconductor layer 230 corresponds to Atanasov: channel material 120).
Regarding claim 22, Atanasov as modified in claim 14 teaches the first lateral semiconductor portion (Atanasov: Fig 1 lateral portion of channel material 120 on capacitor 106, [0020]) is in contact (electrical contact) with a lateral portion (Atanasov: a portion of dielectric 112 has a lateral portion about halfway in the layer with dielectric 116; or there is a small lateral [horizontal] portion of dielectric 112 in direct contact with material 120) of a capacitor dielectric (Atanasov: Fig 1 high-k dielectric 112, [0019]) of one of the plurality of capacitors (Atanasov: Fig 1 capacitors 106, [0017]).
Regarding claim 23, Atanasov as modified in claim 14 teaches the second lateral semiconductor portion (Yamazaki: Fig 25C lateral top lateral portion of oxide semiconductor layer 230, [0338]; oxide semiconductor layer 230 corresponds to Atanasov: channel material 120) is in contact with one of the plurality of bit lines (Atanasov: Fig 1 memory control line 126, [0017]).
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 6, filed August 17, 2026, with respect to amendments to claims 8 and 14-17 have been fully considered and are persuasive. The 35 USC §112 rejection of claims 8 and 14-17 has been withdrawn.
Applicant's arguments, see 35 USC §102 and 103 section starting on page 6, filed August 17, 2026, with respect to the rejection of claims 1 and 14, have been fully considered but they are not persuasive.
Examiner notes that while Atanasov and Yamazaki does not teaching a second lateral semiconductor in the amended claims 1 and 14. Claim 8 of the Office Action filed May 28, 2026 shows that Yamazaki does teach a second lateral semiconductor and provided motivation that one having ordinary skill in the art before the effective filing date of the claimed invention would have used to modify Antanasov.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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