DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/06/2026 has been entered.
Status of Application
In response to Office action mailed 11/06/2025, Applicants amended claims 1, 8, 14 and 20 in and cancelled claims 15-16 in the response filed 02/06/2026.
Claim(s) 1-14 and 17-20 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 and 17-20 have been considered but are moot because the arguments do not apply to the new rejection being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1-5, 8-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub 2018/0122772; hereinafter Kim) and Lin et al. (PG Pub 2016/0343685; hereinafter Lin).
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Regarding claim 1, refer to Fig. 3b and Examiner’s mark-up of Fig. 14 (Primary emphasis on Fig. 14), Kim teaches a device (para [0021-0069]) comprising:
an upper package P200 comprising a first die (800; die-1) laterally spaced apart from a second die (800; die-2) by a first mold compound 900, the mold compound having a portion between the first die and the second die with an uppermost surface above an uppermost surface of the first die and above an uppermost surface of the second die (see Fig. 14), and a first redistribution layer 700 beneath the first die and the second die and the first mold compound (see Fig. 14);
a lower package P100, wherein the first redistribution layer of the upper package is coupled to the lower package by first solder balls 690 (as shown in Fig. 3b; see para [0063]), wherein the lower package comprises a third die 300, and vias 230 (para [0035]) adjacent to the third die (see Fig. 14), the vias having an uppermost surface (surface above 293) at a different level than an uppermost surface of the third die (see Fig. 14); wherein the lower package comprises a second redistribution layer 500 beneath the third die and the vias (see Fig. 14), wherein the lower package comprises a second mold compound 400 (para [0024]) in contact with sidewalls and a top of the third die (see Fig. 14), and the second die of the upper package extends laterally beyond a second one of the sidewalls of the third die (beyond the right sidewall of 300), the second one of the sidewalls laterally opposite the first one of the sidewalls (see Fig. 14); and second solder balls 550 coupled to the second redistribution layer (see Fig. 14), the second solder balls beneath the third die and the vias (see Fig. 14).
Although, Kim teaches the first die of the upper package and a first one of the sidewalls of the third die, he does not teach “the first die of the upper package extends laterally beyond a first one of the sidewalls of the third die”, and “a first one of the first solder balls is vertically between the third die and the first die along a first vertical axis, and a second one of the first solder balls is vertically between the third die and the second die along a second vertical axis;” and “wherein a first one of the first solder balls is vertically between the third die and the first die along a first vertical axis, and a second one of the first solder balls is vertically between the third die and the second die along a second vertical axis.”
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In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 5 provided above, Lin teaches a semiconductor package 500 comprising: an upper package (annotated “upper pkg” in Fig. 5 above) comprising a first die 110b (“die-1”) laterally spaced apart from a second die 110b (“die-2”) by a first mold compound 120b, the mold compound having a portion (annotated “portion” in Fig. 5 above) between the first die and the second die (see Fig. 5), and a first redistribution layer 130b beneath the first die and the second die and the first mold compound (see Fig. 5); a lower package (annotated “lower pkg” in Fig. 5 above), wherein the first redistribution layer of the upper package is coupled to the lower package by first solder balls 170, wherein the lower package comprises a third die 110 (“die-3”), and vias 160 adjacent to the third die (see Fig. 5), wherein a first one of the first solder balls (annotated “ball-1”) is vertically between the third die and the first die along a first vertical axis (see Fig. 5), and a second one of the first solder balls (annotated “ball-2”) is vertically between the third die and the second die along a second vertical axis (see Fig. 5), wherein the lower package comprises a second redistribution layer 200 beneath the third die and the vias (see Fig. 5), wherein the lower package comprises a second mold compound 120b in contact with sidewalls of the third die (see Fig. 5), and wherein the first die of the upper package extends laterally beyond a first one of the sidewalls of the third die (left sidewall of die-1 extends beyond the left sidewall of die-3), and the second die of the upper package extends laterally beyond a second one of the sidewalls of the third die (right sidewall of die-2 extends beyond the right sidewall of die-3), the second one of the sidewalls laterally opposite the first one of the sidewalls (see Fig. 5); and second solder balls 210 coupled to the second redistribution layer, the second solder balls beneath the third die and the vias (see Fig. 5).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the upper package to the lower package with solder balls, as taught by Lin, to provide electrical communication throughout the package.
Regarding claim 2, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches the upper package P200 has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 14), wherein the lower package P100 has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 14), wherein the first sidewall of the upper package is in vertical alignment with the first sidewall of the lower package (see Fig. 14), and wherein the second sidewall of the upper package is in vertical alignment with the second sidewall of the lower package (see Fig. 14).
Regarding claim 3, refer to the cited figures above, in the combination of Kim and Lin, Lin teaches the upper package (“upper pkg”) has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 5), wherein the lower package (lower pkg) has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 4), wherein the first die (110b; die-1) is closer to the first sidewall of the upper package than the third die (110a; die-3) is to the first sidewall of the lower package (see Fig. 5), and wherein the second die (110b; die-2) is closer to the second sidewall of the upper package than the third die is to the second sidewall of the lower package (see Fig. 5).
Regarding claim 4, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches the upper package P200 further comprises an additional die (para [0067]).
Regarding claim 5, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches a portion of one or more of the vias 230 of the lower package P100 has a vertical thickness (vertical length of 230). He does not teach the portion of one or more of the vias of the lower package has a vertical thickness “less than a vertical thickness of the second mold compound.” However, it would have been obvious to one of ordinary skill in the art to choose from a finite number of identified, predictable solutions, (i.e. to have the vertical thickness of the via in the lower package be either greater than, less than or equal to that of the vertical thickness of the second mold compound) to achieve the same desired outcome (see MPEP 2143 (I)(E) and KSR, 550 U.S. at 421, 82 USPQ2d at 1397).
Regarding claim 8, refer to Fig. 3b and Examiner’s mark-up of Fig. 14 (Primary emphasis on Fig. 14), Kim teaches a device (para [0021-0069]) comprising:
an upper package P200 comprising a first die (800; die-1) laterally spaced apart from a second die (800; die-2) by a first region of encapsulant 900 (portion between the dies), the first region of encapsulant having an uppermost surface above an uppermost surface of the first die and above an uppermost surface of the second die (portion about the dies; see Fig. 14), and a first layer of connections (within 700) beneath the first die and the second die and the first region of encapsulant (see Fig. 14);
a lower package P100, wherein the first layer of connections of the upper package is coupled to the lower package by first solder balls (690 of Fig. 3b), wherein the lower package comprises a third die (300; die-3), and vias 230 adjacent to the third die (see Fig. 14), the vias having an uppermost surface at a different level than an uppermost surface of the third die (the top of the vias is higher than the height of die-3),
wherein the lower package comprises a second layer of connections (connections within 500) beneath the third die and the vias (see Fig. 14), and
wherein the lower package comprises a second region of encapsulant 400 in contact with sidewalls and a top of the third die (see Fig. 14), and the second die of the upper package extends laterally beyond a second one of the sidewalls of the third die (beyond the right sidewall of 300), the second one of the sidewalls laterally opposite the first one of the sidewalls (see Fig. 14); and second solder balls 550 coupled to the second layer of connections, (see Fig. 14), the second solder balls beneath the third die and the vias (see Fig. 14).
Kim does not teach the first die of the upper package extends laterally beyond a first one of the sidewalls of a third die; and a first one of the first solder balls is vertically between the third die and the first die along a first vertical axis, and a second one of the first solder balls is vertically between the third die and the second die along a second vertical axis,
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 5 provided above, Lin teaches a semiconductor package 500 comprising: an upper package (annotated “upper pkg” in Fig. 5 above) comprising a first die 110b (“die-1”) laterally spaced apart from a second die 110b (“die-2”) by a first mold compound 120b, the mold compound having a portion (annotated “portion” in Fig. 5 above) between the first die and the second die (see Fig. 5), and a first redistribution layer 130b beneath the first die and the second die and the first mold compound (see Fig. 5); a lower package (annotated “lower pkg” in Fig. 5 above), wherein the first redistribution layer of the upper package is coupled to the lower package by first solder balls 170, wherein the lower package comprises a third die 110 (“die-3”), and vias 160 adjacent to the third die (see Fig. 5), wherein a first one of the first solder balls (annotated “ball-1”) is vertically between the third die and the first die along a first vertical axis (see Fig. 5), and a second one of the first solder balls (annotated “ball-2”) is vertically between the third die and the second die along a second vertical axis (see Fig. 5), wherein the lower package comprises a second redistribution layer 200 beneath the third die and the vias (see Fig. 5), wherein the lower package comprises a second mold compound 120b in contact with sidewalls of the third die (see Fig. 5), and wherein the first die of the upper package extends laterally beyond a first one of the sidewalls of the third die (left sidewall of die-1 extends beyond the left sidewall of die-3), and the second die of the upper package extends laterally beyond a second one of the sidewalls of the third die (right sidewall of die-2 extends beyond the right sidewall of die-3), the second one of the sidewalls laterally opposite the first one of the sidewalls (see Fig. 5); and second solder balls 210 coupled to the second redistribution layer, the second solder balls beneath the third die and the vias (see Fig. 5).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the upper package to the lower package with solder balls, as taught by Lin, to provide electrical communication throughout the package.
Regarding claim 9, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches the upper package P200 has a first lateral width (horizontal distance), wherein the lower package P100 has a second lateral width (horizontal distance), and wherein the second lateral width is the same as and is aligned with the first lateral width (see Fig. 14).
Regarding claim 10, refer to the cited figures above, in the combination of Kim and Lin, Lin teaches the first die 110b (“die-1”) is closer to a first edge of the upper package (left sidewall of upper pkg) than the third die (110a) is to the first sidewall of the lower package (left sidewall of lower pkg) (see Fig. 5), and wherein the second die 110b (“die-2”) is closer to the second sidewall of the upper package (right sidewall of upper pkg) than the third die is to the second sidewall of the lower package (right sidewall of lower pkg) (see Fig. 5).
Regarding claim 11, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches the upper package P200 further comprises an additional die (para [0067]).
Regarding claim 12, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches a portion of one or more of the vias 230 of the lower package P100 has a vertical thickness (vertical length of 230). He does not teach the portion of one or more of the vias of the lower package has a vertical thickness “less than a vertical thickness of the second mold compound.” However, it would have been obvious to one of ordinary skill in the art to choose from a finite number of identified, predictable solutions, (i.e. to have the vertical thickness of the via in the lower package be either greater than, less than or equal to that of the vertical thickness of the second mold compound) to achieve the same desired outcome (see MPEP 2143 (I)(E) and KSR, 550 U.S. at 421, 82 USPQ2d at 1397).
Regarding claim 14, refer to Fig. 3b and Examiner’s mark-up of Fig. 14 (Primary emphasis on Fig. 14), Kim teaches a device (para [0021-0069]) comprising:
a first die (800; die-1) laterally spaced apart from a second die (800; die-2) by a first mold compound 900, the first mold compound having a portion between the first die and the second die with an uppermost surface above an uppermost surface of the first die and above an uppermost surface of the second die (see Fig. 14);
a first redistribution layer 700 beneath the first die and the second die and the first mold compound (see Fig. 14);
a third die 300 beneath the first redistribution layer (see Fig. 14), wherein the first die extends laterally beyond a first sidewall of the third die, and the second die extends laterally beyond a second sidewall of the third die (beyond the right sidewall of 300), the second sidewall laterally opposite the first sidewall (see Fig. 14);
vias adjacent to the third die 230, the vias having an uppermost surface at a different level than an uppermost surface of the third die (see Fig. 14);
a second redistribution layer 500 beneath the third die and the vias (see Fig. 14);
a second mold compound 400 in contact with sidewalls and a top of the third die (see Fig. 14); and
solder balls 550 coupled to the second redistribution layer, the solder balls beneath the third die and the vias (see Fig. 14).
Kim does not teach the first die of the upper package extends laterally beyond a first one of the sidewalls of a third die; and a first one of the first solder balls is vertically between the third die and the first die along a first vertical axis, and a second one of the first solder balls is vertically between the third die and the second die along a second vertical axis.
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 5 provided above, Lin teaches a semiconductor package 500 comprising: an upper package (annotated “upper pkg” in Fig. 5 above) comprising a first die 110b (“die-1”) laterally spaced apart from a second die 110b (“die-2”) by a first mold compound 120b, the mold compound having a portion (annotated “portion” in Fig. 5 above) between the first die and the second die (see Fig. 5), and a first redistribution layer 130b beneath the first die and the second die and the first mold compound (see Fig. 5); a lower package (annotated “lower pkg” in Fig. 5 above), wherein the first redistribution layer of the upper package is coupled to the lower package by first solder balls 170, wherein the lower package comprises a third die 110 (“die-3”), and vias 160 adjacent to the third die (see Fig. 5), wherein a first one of the first solder balls (annotated “ball-1”) is vertically between the third die and the first die along a first vertical axis (see Fig. 5), and a second one of the first solder balls (annotated “ball-2”) is vertically between the third die and the second die along a second vertical axis (see Fig. 5), wherein the lower package comprises a second redistribution layer 200 beneath the third die and the vias (see Fig. 5), wherein the lower package comprises a second mold compound 120b in contact with sidewalls of the third die (see Fig. 5), and wherein the first die of the upper package extends laterally beyond a first one of the sidewalls of the third die (left sidewall of die-1 extends beyond the left sidewall of die-3), and the second die of the upper package extends laterally beyond a second one of the sidewalls of the third die (right sidewall of die-2 extends beyond the right sidewall of die-3), the second one of the sidewalls laterally opposite the first one of the sidewalls (see Fig. 5); and second solder balls 210 coupled to the second redistribution layer, the second solder balls beneath the third die and the vias (see Fig. 5).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the upper package to the lower package with solder balls, as taught by Lin, to provide electrical communication throughout the package.
Regarding claim 17, refer to the cited figures above, in the combination of Lin, Hung and Kim, Lin teaches the first mold compound 120b has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 5), wherein the second mold compound 120a has a first sidewall (ex. left sidewall) and a second sidewall (ex. right sidewall) laterally opposite the first sidewall (see Fig. 5), wherein the first sidewall of the first mold compound is in vertical alignment with the first sidewall of the second mold compound (see Fig. 5), and wherein the second sidewall of the first mold compound is in vertical alignment with the second sidewall of the second mold compound (see Fig. 5).
Regarding claim 18, refer to the cited figures above, in the combination of Kim and Lin, Lin teaches the first mold compound 120b has a first sidewall (ex. left) and a second sidewall (ex. right) laterally opposite the first sidewall (see Fig. 5), wherein the second mold compound 120a has a first sidewall (ex. eft) and a second sidewall (ex. right) laterally opposite the first sidewall (see Fig. 5), wherein the first die 110b (“die-1”) is closer to the first sidewall of the first mold compound than the third die 110a is to the first sidewall of the second mold compound (see Fig. 5), and wherein the second die 110b (“die-2”) is closer to the second sidewall of the first mold compound than the third die is to the second sidewall of the second mold compound (see Fig. 5).
Regarding claim 19, refer to the cited figures above, in the combination of Kim and Lin, Kim teaches the first mold compound 900 has a first lateral width (horizontal length of 900), wherein the second mold compound 400 has a second lateral width (horizontal length of 400), and wherein the second lateral width is the same as and is aligned with the first lateral width (see Fig.14).
2. Claim(s) 6-7,13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Lin, as applied to claim 1, 8 and 14 respectively above, and further in view of Katkar et al. (PG Pub 2015/0348873; hereinafter Katkar).
Regarding claim 6 and claim 7, refer to the figures provided above, in the combination of Kim and Lin, Lin teaches (claim 6) the second solder balls 210 (see Fig. 5), he does not explicitly teach “a board beneath the second solder balls; (claim 7) wherein a package substrate intervening between the board and the second solder balls.”
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In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 1a-provided above, Katkar teaches a device 100 (para [0049-0085]) comprising: (claim 6) a board 50 (para [0055]) beneath a second solder balls (annotated “balls” in Fig. 1a above); (claim 7) wherein a package substrate 20 (para [0053]) intervening between the board and the second solder balls (see Fig. 1a).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a board and package substrate below the second solder balls of the combined invention, as taught by Katkar, for the purpose of providing means to transmit signals to and from the device.
Regarding claim 13, refer to the figures provided above, in the combination of Lin and Kim, Lin teaches the second solder balls 210 (see Fig. 5), he does not explicitly teach “a board beneath the second solder balls.
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 1a-provided above, Katkar teaches a device 100 (para [0049-0085]) comprising: a board 50 (para [0055]) beneath a second solder balls (annotated “balls” in Fig. 1a above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a board and package substrate below the second solder balls, as taught by Katkar, for the purpose of providing means to transmit signals to and from the device.
Regarding claim 20, refer to the figures provided above, in the combination of Lin and Kim, Lin teaches the second solder balls 210 (see Fig. 5), he does not explicitly teach “a board beneath the second solder balls.
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 1a-provided above, Katkar teaches a device 100 (para [0049-0085]) comprising: a board 50 (para [0055]) beneath a second solder balls (annotated “balls” in Fig. 1a above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a board and package substrate below the second solder balls, as taught by Katkar, for the purpose of providing means to transmit signals to and from the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817