DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7, 8-14 &15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 & 15 recite the limitation “the underfill extending laterally beyond the first sidewall and the second sidewall of the double-sided die”. There is no support in the specification for said limitation. It is understood that the drawings (e.g. Fig. 1 that depicts the underfill material 150) are in greatly simplified form and are not to precise scale. The Examiner suggests that applicant provide a specific paragraph/s in the specification where said limitation is disclosed.
Claims 2-7 & 16-20 are rejected for being dependent on claims 1 & 15.
Claim 8 recites the limitation “the second insulating material extending laterally beyond the first sidewall and the second sidewall of the double-sided die”. There is no support in the specification for said limitation. It is understood that the drawings (e.g. Fig. 1 that depicts the second insulating material 150) are in greatly simplified form and are not to precise scale. The Examiner suggests that applicant provide a specific paragraph/s in the specification where said limitation is disclosed.
Claims 9-14 are rejected for being dependent on claim 8.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recite the limitations “a first insulating material… conductive pathways” and “a second insulating material vertically between the second die and the fist die, the second insulating material laterally surrounding the first interconnects, the second insulating material extending laterally beyond a first sidewall and a second sidewall of the first die, and the second insulating material having a bottom surface below a top surface of the conductive via”. It is unclear what features said limitations are referring to. It would be helpful if applicant identified what reference numerals in the drawings refer to “first insulating material”, “second insulating material” and “first interconnects”. It appears that claim 8 is directed towards the device shown in Fig. 5 and it is unclear if the first insulating material and second insulating material refer to components 178 & 170, 150 or 112 (Applicant’s Fig. 1 & Fig. 5)? This ambiguity also creates confusion to map the rest of the claim to Fig. 5. The Examiner suggests that applicant map the claim to a specific drawing to help expedite the prosecution.
Claims 9-14 are rejected based on their dependency on claim 8
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 2017/0263518) in view of Park et al. (US Pub. 2012/0292745).
Regarding claim 1, Yu teaches a microelectronic assembly, comprising:
a redistribution layer 60 comprising conductive traces 62 and conductive vias 62 (see Fig. 19);
a double-sided die (e.g. 100B and/or 100C) having a top side and a bottom side, the bottom side on a portion of the redistribution layer 60, and the double-sided die 100B/100C having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the double-sided die 100B/100C having conductive contacts (see Fig. 19 below and note annotations) on the top side, and the double-sided die 100B/100C having through silicon vias (TSVs) (136A-136B, see Fig. 4 and Fig. 19) coupled to conductive traces 62 of the portion of the redistribution layer 60 beneath the double-sided die 100B/100C (see Fig. 19 below);
a conductive via 30 laterally spaced apart from the first sidewall of the double-sided die (Fig. 19);
a second die 66B over the double-sided die 100B/100C and over the conductive via 30, the second die 66B coupled to the conductive contacts on the top side of the double-sided die by first interconnects (see Fig. 19 below and note the annotations), and the second die 66B directly overlapping with and coupled to the conductive via 30 (Fig. 19);
an underfill material134 (die-attach film DAF is a type of underfill material) vertically between the second die 66B and the double-sided die 100B/100C, the underfill material 134 laterally surrounding the first interconnects, and the underfill material having a bottom surface below a top surface of the conductive via 30 (see Fig. 19 below); and
second interconnects 70 beneath and coupled to the redistribution layer 60, a portion of the second interconnects 70 vertically beneath the double-sided die 100B/100C, the second interconnects comprising solder (Fig. 19 and Para [0035]).
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Yu is silent on wherein the underfill extends laterally beyond the first sidewall and the second sidewall of the double-sided die. However, Park teaches in Fig. 14 a semiconductor device, wherein an underfill extends laterally beyond a first sidewall and a second sidewall of a double-sided die. This has the advantages of improving mechanical strength and stress distribution. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yu with the underfill material, as taught by Park, so as to provide improved mechanical strength and stress distribution.
Regarding claim 2, the combination of Yu and Park teaches the microelectronic assembly of claim 1, wherein the second die 66B is coupled to all of the conductive contacts on the top side of the double-sided die 10B/100C (Yu’s Fig. 19).
Regarding claim 3, the combination of Yu and Park teaches the microelectronic assembly of claim 1, wherein the underfill material comprises an epoxy (e.g. Park’s Para [0060]).
Regarding claim 4, the combination of Yu and Park teaches the microelectronic assembly of claim 1, wherein the second interconnects further comprise copper pillars, and wherein the solder is on the copper pillars (Yu’s Fig. 19 & Para [0028]).
Regarding claim 5, the combination of Yu and Park teaches the microelectronic assembly of claim 1, wherein the double-sided die 100B/100C has a footprint entirely within a footprint of the second die 66B (Yu’s Fig. 19).
Regarding claim 6, the combination of Yu and Park teaches the microelectronic assembly of claim 1, further comprising: a third die (100A or 100D) laterally spaced apart from the double-sided die (Yu’s Fig. 19).
Regarding claim 7, the combination of Yu and Park teaches the microelectronic assembly of claim 1, further comprising: a package substrate 76 beneath and coupled to the second interconnects 70 (Yu’s Fig. 19).
Regarding claim 8, as best understood, Yu teaches a microelectronic assembly, comprising:
a first insulating material 60 having one or more conductive pathways 62 therein (Fig. 19);
a first die 100B/100C on a portion of the first insulating material 60 having one or more conductive pathways 62, the first die 100B/100C having conductive contacts on a top side of the first die (see Fig. 19 above), and the first die 100B/100C having through substrate vias 136A-136B coupled to conductive pathways 62 of the portion of the first insulating material 60 having one or more conductive pathways (Fig. 19);
a conductive via 30 laterally spaced apart from the first die 100B/100C (Fig. 19);
a second die 66B over the first die 100B/100C and over the conductive via 30, the second die 66B coupled to the conductive contacts on the top side of the first die by first interconnects (note annotations on Fig. 19 above), and the second die 66B vertically overlapping with and coupled to the conductive via 30 (Fig. 19);
a second insulating material (135 and/or 134) vertically between the second die 66B and the first die 100B/100C, the second insulating material 134 laterally surrounding the first interconnects (see Fig. 19 above), and the second insulating material 134/135 having a bottom surface below a top surface of the conductive via 130 (see Fig. 19); and
second interconnects 70 beneath and coupled to the first insulating material 60 having the one or more conductive pathways 62, a portion of the second interconnects 70 vertically beneath the first die 100B/100C (Fig. 19).
Yu is silent on wherein the second insulating material extends laterally beyond the first sidewall and the second sidewall of the double-sided die. However, Park teaches in Fig. 14 a semiconductor device, wherein a second insulating material extends laterally beyond a first sidewall and a second sidewall of a double-sided die. This has the advantages of improving mechanical strength and stress distribution. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yu with the underfill material, as taught by Park, so as to provide improved mechanical strength and stress distribution.
Regarding claim 9, the combination of Yu and Park teaches the microelectronic assembly of claim 8, wherein the second die 66B is coupled to all of the conductive contacts on the top side of the first die 100B/100C (Fig. 19).
Regarding claim 10, the combination of Yu and Park teaches the microelectronic assembly of claim 8, wherein the underfill material comprises an epoxy (e.g. Park’s Para [0060]).
Regarding claim 11, the combination of Yu and Park teaches the microelectronic assembly of claim 8, wherein each of the second interconnects 70 comprises a copper pillar with a solder cap (Yu’s Fig. 19).
Regarding claim 12, the combination of Yu and Park teaches the microelectronic assembly of claim 8, wherein the first die 100B/100C has a footprint entirely within a footprint of the second die 66B (Yu’s Fig. 19).
Regarding claim 13, the combination of Yu and Park teaches the microelectronic assembly of claim 8, further comprising: a third die (100A or 100D) laterally spaced apart from the first die (Yu’s Fig. 19).
Regarding claim 14, the combination of Yu and Park teaches the microelectronic assembly of claim 8, further comprising: a package substrate 76 beneath and coupled to the second interconnects 70 (Yu’s Fig. 19).
Regarding claim 15, Yu teaches a system, comprising:
a board 76; and
a microelectronic assembly coupled to the board (Fig. 19), the microelectronic assembly, comprising:
a redistribution layer 60 comprising conductive traces 62 and conductive vias 62 (Fig. 19);
a double-sided die 100B/100C having a top side and a bottom side, the bottom side on a portion of the redistribution layer 60, and the double-sided die 100B/100C having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the double-sided die 100B/100C having conductive contacts on the top side (note annotations in Fig. 19 above), and the double-sided die 100B/100C having through silicon vias (TSVs) (136A-136B) coupled to conductive traces 62 of the portion of the redistribution layer 60 beneath the double-sided die 100B/100C (Fig. 19);
a conductive via 30 laterally spaced apart from the first sidewall of the double-sided die (Fig. 19);
a second die 66B over the double-sided die 100B/100C and over the conductive via 30, the second die 66B coupled to the conductive contacts on the top side of the double-sided die by first interconnects (note annotations in Fig. 19 above), and the second die 66B vertically overlapping with and coupled to the conductive via 30 (Fig. 19);
an underfill material 134 (die-attach film DAF is a type of underfill material) vertically between the second die 66B and the double-sided die 100B/100C, the underfill material laterally surrounding the first interconnects (see Fig. 19 above), and the underfill material 134 having a bottom surface below a top surface of the conductive via 30 (Fig. 19); and
second interconnects 70 beneath and coupled to the redistribution layer 60, a portion of the second interconnects 70 vertically beneath the double-sided die 100B/100C, the second interconnects comprising solder (Fig. 19 and Para [0035]).
Yu is silent on wherein the underfill extends laterally beyond the first sidewall and the second sidewall of the double-sided die. However, Park teaches in Fig. 14 a semiconductor device, wherein an underfill extends laterally beyond a first sidewall and a second sidewall of a double-sided die. This has the advantages of improving mechanical strength and stress distribution. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yu with the underfill material, as taught by Park, so as to provide improved mechanical strength and stress distribution.
Regarding claim 16, the combination of Yu and Park teaches the system of claim 15, further comprising: a memory coupled to the board (e.g. Para [0018 & 0032]).
Regarding claim 17, the combination of Yu and Park teaches the system of claim 15, further comprising: a communication chip (e.g. any of the chips in Yu’s Fig. 19) can be coupled to the board 76 (Fig. 19).
Regarding claim 18, the combination of Yu and Park teaches the system of claim 15, further comprising: a display device can be coupled to the board (Yu’s Fig. 19).
Regarding claim 19, the combination of Yu and Park teaches the system of claim 15, further comprising: a GPS device can be coupled to the board (Yu’s Fig. 19).
Regarding claim 20, the combination of Yu and Park teaches the system of claim 15, further comprising: a battery can be coupled to the board (Yu’s Fig. 19).
With respect to claims 16-20, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in light of new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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