Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 09/28/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (LUTNet: Rethinking Inference in FPGA Soft Logic, Department of Electrical and Electronic Engineering Imperial College London, London, SW7 2AZ, United Kingdom, April 2019).
Regarding claim 1, Wang discloses:
A method, comprising:
pruning elements of a current circuit design, at a bit-level, to provide an optimized circuit design (see page 2-3, III. Network construction and training, LUTNet’s initialization comprises three successive stages: training, pruning and “logic expansion” (XNOR to K-LUT conversion), with each of the latter two including a retraining phase….., B. Pruning, Following high-precision training, fine-grained pruning is conducted through the application…., see Fig. 2); and
selecting one of the current circuit design and the optimized circuit design as a circuit design solution based on one or more of measures of accuracy of the circuit designs, metrics of the circuit designs, and optimization criteria (see page 4-5, we were primarily interested in logic density, which we define as the number of LUTs required to construct a network able to achieve a particular test accuracy for a given dataset….., see page 1, elements are any K components of the original input vector …… for some binary selection matrix….);
wherein the current circuit design and the optimized circuit design comprise technology-mapped circuit designs (see page 1-2, Since its inputs and outputs are binary, each gn maps directly to a single K-LUT…, a BNN architecture from a dense array of simple XNOR gates into a sparse network of arbitrary K-input functions directly mappable onto K-LUTs…..).
Regarding claim 2, Wang discloses:
wherein the elements comprise look-up tables (LUTs) of a network of LUTs, and wherein the metrics comprise measures of LUT utilization (see Fig., see page 2, We introduce LUTNet, the first neural network architecture featuring K-LUTs as inference operators. Since each K-LUT is capable of performing an arbitrary Boolean operation on up to K binary inputs….., see page 5-6).
Regarding claim 3, Wang discloses:
wherein the network of LUTs represents a trained artificial neural network (see page 2-4, see Fig. 2, LUTNet’s fully automated training and FPGA implementation flow….), the method further comprising: selecting a subset of LUTs of the network of LUTs that produce output bits of neurons of the artificial neural network; wherein the pruning comprises pruning LUTs of the subset, (see page 4, In order to demonstrate the capabilities of specialized LUTs, we unrolled a subset of each network such that each node within that subset mapped….).
Allowable Subject Matter
Claims 16 and 18 are allowed over prior art of record, respectively.
Reasons for Allowance
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, the combination of the prior arts fail to disclose:
“replace the LUT with a constant logic state to provide a revised circuit design, optimize LUT usage of the revised circuit design to provide an optimized circuit design”.
Regarding claim 18, the combination of the prior arts fail to disclose:
“wherein the network of LUTs represents a trained artificial neural network; wherein the training data-based accuracies are based on training data used to train the artificial neural network; and wherein the validation data-based accuracies are based on validation data used to validate the artificial neural network”.
Claims 17 and 19-20 also allowed as being directly or indirectly dependent of the allowed independent base claims 16 and 18.
Claims 4-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest the limitation as in the claims.
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure listed on the PTO-982 form attached. None of cited/recorded prior arts stands alone of combination with others discloses all limitation required in claim invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/BRIAN NGO/ Primary Examiner, Art Unit 2851
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