DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Figs. 1D-1F (claims 1-11, 13-20) in the reply filed on 12/29/25 is acknowledged. However, the following claims will not be examined because:
claims 13-15 recite a width of the first through via and the second through via which is in Species B, Fig. 6 and Species C, Fig. 7, respectively;
claim 20 recites an extension part and a connection part which is in Species E, Fig. 9 and Species H, Fig. 12.
Accordingly claims 13-15 and 20 are withdrawn from consideration.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 5 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9, 11,13 of copending Application No. 18/236,501 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application includes additional claim details not included in this application. However, it would have been obvious to omit the features of the reference application where the function attributed to such features is not desired or required.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
This application 18/236,501
Claim 1:
a lower bonding structure that includes
a lower substrate,
a lower dielectric structure on the lower substrate, and
a transistor between the lower substrate and the lower dielectric structure
Claim 9:
a lower bonding structure that includes
a lower substrate,
a lower dielectric structure on the lower substrate,
a first transistor between the lower substrate and the lower dielectric structure, and
a first lower bonding pad in the lower dielectric structure
Claim 1:
an upper bonding structure that includes an upper dielectric structure on the lower dielectric structure,
an upper substrate on the upper dielectric structure, and
a memory cell structure between the upper substrate and the upper dielectric structure
Claim 9:
an upper bonding structure that includes an upper dielectric structure on the lower dielectric structure,
an upper substrate on the upper dielectric structure,
a memory cell structure between the upper substrate and the upper dielectric structure, and
a first upper bonding pad in the upper dielectric structure,
Claim 1:
a connection structure on the upper bonding structure
Claim 13:
a connection structure that includes a connection dielectric structure on the upper substrate and a connection conductive structure in the connection dielectric structure
Claim 1:
a first through via that electrically connects the transistor to the memory cell structure,
Claim 13:
a through via that electrically connects the connection conductive structure to the first transistor,
Claim 1:
wherein:
the transistor overlaps the memory cell structure, and
the first through via penetrates the upper substrate and the upper dielectric structure
Claim 9:
wherein the first transistor overlaps the memory cell structure
Claim 13:
the through via penetrating the upper substrate
Claim 9:
wherein the first lower bonding pad is in contact with the first upper bonding pad,
Claim 9:
wherein the first transistor is electrically connected to the memory cell structure through the first upper bonding pad and the first lower bonding pad
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2023/0180468 (Lee ‘468).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Lee ‘468 discloses
1. A semiconductor device, comprising:
a lower bonding structure PS that includes a lower substrate 200, a lower dielectric structure 210 / 220 on the lower substrate 200, and a transistor PTR between the lower substrate 200 and the lower dielectric structure 210 / 220;
an upper bonding structure CS that includes an upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170 on the lower dielectric structure 210 / 220, an upper substrate 100 on the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170, and a memory cell structure CAR between the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170;
a connection structure WCR / BCR on the upper bonding structure CS; and
a first through via IOPLG that electrically connects the transistor PTR to the memory cell structure CAR, wherein:
the transistor PTR overlaps the memory cell structure CAR, and the first through via IOPLG penetrates the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170.
Lee ‘468 discloses ([0052])
2. The semiconductor device as claimed in claim 1, wherein the transistor PTR constitutes a sense amplifier.
Lee ‘468 discloses
3. The semiconductor device as claimed in claim 1, wherein:
the lower bonding structure PS includes lower conductive structures PLP / BP1c / BP2c that electrically connect the first through via IOPLG to the transistor SWG, the lower conductive structures PLP / BP1c / BP2c include a pad at top of the lower conductive structures PLP / BP1c / BP2c, and a top surface of the pad is in contact with a bottom surface of the first through via IOPLG.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being obvious over Lee ‘468 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2024/0090228 (Choi).
Lee ‘468 fails to disclose
4. The semiconductor device as claimed in claim 1, wherein the upper bonding structure further includes a dielectric pattern that surrounds the first through via, and the dielectric pattern is in the upper substrate.
Choi teaches
A semiconductor device comprising:
wherein the upper bonding structure SC further includes a dielectric pattern 61 that surrounds the first through via OP1, and the dielectric pattern 61 is in the upper substrate 100.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a dielectric pattern in Lee ‘468. The motivation would be electrical isolation, signal integrity, and structural reliability as discussed in Choi ([0004], [0122]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being obvious over Lee ‘468 as applied to claim 5 above, and further in view of U.S. Patent Application Publication No. 2024/0164101 (Kim ‘101).
Lee ‘468 fails to teach
6. The semiconductor device as claimed in claim 5, wherein:
the connection structure includes a bit-line connection pattern in contact with a top surface of the first through via, the semiconductor device further includes a second through via in contact with the bit-line connection pattern and the bit line, and the second through via penetrates the upper substrate.
Kim ‘101 teaches
A semiconductor device comprising:
the connection structure includes a bit-line connection pattern 197 / CL4 in contact with a top surface of the first through via TCP
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to include a bit-line connection pattern and a second through via in Lee ‘468. The motivation would be a connection pattern and a via are well-known in three-dimension devices to improve reliability and electrical properties as discussed in Kim ‘101. See MPEP 2144.03.
Claim(s) 9, 10, 16-19 is/are rejected under 35 U.S.C. 103 as being obvious over Lee ‘468 in view Kim ‘101.
Lee ‘468 discloses
9. A semiconductor device, comprising:
a lower bonding structure PS that includes a lower substrate 200, a lower dielectric structure 210 / 220 on the lower substrate 200, a lower conductive structure PLP / BP1c / BP2c in the lower dielectric structure 210, and a first transistor PTR between the lower substrate 200 and the lower dielectric structure 210;
an upper bonding structure CS that includes an upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170 on the lower dielectric structure 210 / 220, an upper substrate 100 on the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170, and a memory cell structure CAR between the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170, the memory cell structure CAR including a bit line BL;
a first through via IOPLG that penetrates the upper substrate 100 and the upper dielectric structure 3 and is in contact with the lower conductive structure PLP / BP1c / BP2c; and
a second through via IOPLG that penetrates the upper substrate 100.
Lee ‘468 fails to disclose
a second through via that is in contact with the bit line; and
a bit-line connection pattern in contact with the first through via and the second through via.
Kim ‘101 teaches
A semiconductor device comprising:
a second through via 194 that is in contact with the bit line BL; and
a bit-line connection pattern 197 / CL4 in contact with the first through via TCP and the second through via 194.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a second through via and a bit-line connection pattern in Lee ‘468. The motivation would be routine engineering design considerations based on its suitability for the intended purpose as discussed in Kim ‘101. See MPEP 2144.07.
Lee ‘468 discloses
10. The semiconductor device as claimed in claim 9, wherein the first transistor PTR overlaps the memory cell structure CAR.
Lee ‘468 discloses
16. The semiconductor device as claimed in claim 9, wherein:
the lower bonding structure PS further includes a second transistor (unlabeled in PR2 section) between the upper substrate 100 and the lower dielectric structure 210 / 220, and the upper bonding structure CS further includes a power capacitor PC in the upper dielectric structure 210 / 220.
Lee ‘468 discloses
17. The semiconductor device as claimed in claim 16, further including a third through via (unlabeled) that electrically connects the second transistor (unlabeled in PR2 section) to the power capacitor PC.
Lee ‘468 discloses
18. The semiconductor device as claimed in claim 16, wherein:
the memory cell structure CAR further includes a cell capacitor DS ([0079]), and the power capacitor PC is at a level the same as a level of the cell capacitor DS.
Lee ‘468 discloses
19. A semiconductor device, comprising:
a lower substrate 200;
a lower dielectric structure 210 / 220 on the lower substrate 200;
a transistor PTR between the lower substrate 200 and the lower dielectric structure 210 / 220;
a lower conductive structure PLP / BP1c / BP2c in the lower dielectric structure 210 / 220 and connected to the transistor PTR;
an upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170 on the lower dielectric structure 210 / 220;
an upper substrate 100 on the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170;
a memory cell structure CAR between the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170, the memory cell structure CAR including a bit line BL;
a connection dielectric structure 300 / 310 on the upper substrate 100;
a bit-line connection pattern BCR in the connection dielectric structure 300 / 310;
a first through via IOPLG that connects the lower conductive structure PLP / BP1c / BP2c to the bit-line connection pattern BCR ([0048]) and penetrates the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170; and
a second through via IOPLG that penetrates the upper substrate 100,
wherein the transistor PTR overlaps the memory cell structure CAR.
Lee ‘468 fails to disclose
a second through via that connects the bit line to the bit-line connection pattern.
Kim ‘101 teaches
a second through via 194 that connects the bit line BL to the bit-line connection pattern 197 / CL4.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a second through via and a bit-line connection pattern in Lee ‘468. The motivation would be routine engineering design considerations based on its suitability for the intended purpose as discussed in Kim ‘101. See MPEP 2144.07.
Claim(s) 1-3, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2024/0098973 (Liu ‘973) in view of Lee ‘468.
Liu ‘973 discloses (Fig. 7)
1. A semiconductor device, comprising:
a lower bonding structure 102 that includes a lower substrate 710, a lower dielectric structure 716 on the lower substrate 710, and a transistor 714 between the lower substrate 710 and the lower dielectric structure 716;
an upper bonding structure 104 that includes an upper dielectric structure 722 on the lower dielectric structure 716, an upper substrate 762 on the upper dielectric structure 722, and a memory cell structure 724 / 728 between the upper substrate 762 and the upper dielectric structure 722;
a connection structure 760 on the upper bonding structure 104.
Liu ‘973 fails to disclose
a first through via that electrically connects the transistor to the memory cell structure, wherein:
the transistor overlaps the memory cell structure, and the first through via penetrates the upper substrate and the upper dielectric structure.
Lee ‘468 teaches
a first through via IOPLG that electrically connects the transistor PTR to the memory cell structure CAR, wherein:
the transistor PTR overlaps the memory cell structure CAR, and the first through via IOPLG penetrates the upper substrate 100 and the upper dielectric structure 110 / 120 / 130 / 140 / 150 / 160 / 170.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a first through via in Liu ‘973. The motivation would be a via is well-known in three-dimension devices to improve reliability and integration density as discussed in Lee ‘468. See MPEP 2144.03.
Liu ‘973 discloses ([0050])
2. The semiconductor device as claimed in claim 1, wherein the transistor 714 constitutes a sense amplifier.
Liu ‘973 discloses (Fig. 7)
3. The semiconductor device as claimed in claim 1, wherein:
the lower bonding structure 102 includes lower conductive structures that electrically connect the first through via (unlabeled in Fig. 7) to the transistor, 714 the lower conductive structures include a pad at top of the lower conductive structures, and a top surface of the pad is in contact with a bottom surface of the first through via.
Liu ‘973 discloses
5. The semiconductor device as claimed in claim 1, wherein:
the memory cell structure 724 / 728 includes a bit line 723, and the first through via (unlabeled in Fig. 7) electrically connects the bit line 723 to the transistor 714.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being obvious over Liu ‘973 in view of Lee ‘468 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2024/0090228 (Choi).
The combination of references fails to teach
4. The semiconductor device as claimed in claim 1, wherein the upper bonding structure further includes a dielectric pattern that surrounds the first through via, and the dielectric pattern is in the upper substrate.
Choi teaches
A semiconductor device comprising:
wherein the upper bonding structure SC further includes a dielectric pattern 61 that surrounds the first through via OP1, and the dielectric pattern 61 is in the upper substrate 100.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a dielectric pattern in the modified device of Liu ‘973. The motivation would be electrical isolation, signal integrity, and structural reliability as discussed in Choi ([0004], [0122]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu ‘973 in view of Lee ‘468 as applied to claim 5 above, and further in view of U.S. Patent Application Publication No. 2024/0164101 (Kim ‘101).
The combination of references fails to teach
6. The semiconductor device as claimed in claim 5, wherein:
the connection structure includes a bit-line connection pattern in contact with a top surface of the first through via, the semiconductor device further includes a second through via in contact with the bit-line connection pattern and the bit line, and the second through via penetrates the upper substrate.
Kim ‘101 teaches
A semiconductor device comprising:
the connection structure includes a bit-line connection pattern 197 / CL4 in contact with a top surface of the first through via TCP (circular) further includes a second through via 194 in contact with the bit-line connection pattern 197 / CL4 and the bit line BL, and the second through via 194 penetrates the upper substrate 100.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to include a bit-line connection pattern and a second through via in the modified device of Liu ‘973. The motivation would be a connection pattern and a via are well-known in three-dimension devices to improve reliability and electrical properties as discussed in Kim ‘101. See MPEP 2144.03.
Claim(s) 9, 10, 16-19 is/are rejected under 35 U.S.C. 103 as being obvious over Liu ‘973 in view of Kim ‘101.
Liu ‘973 discloses (Fig. 7)
9. A semiconductor device, comprising:
a lower bonding structure 102 that includes a lower substrate 710, a lower dielectric structure 716 on the lower substrate 710, a lower conductive structure (unlabeled in Fig. 7) in the lower dielectric structure 716, and a transistor 714 between the lower substrate 710 and the lower dielectric structure 716;
an upper bonding structure 104 that includes an upper dielectric structure 722 on the lower dielectric structure 716, an upper substrate 762 on the upper dielectric structure 722, and a memory cell structure 724 / 728 between the upper substrate 762 and the upper dielectric structure 722, the memory cell structure 724 / 728 including a bit line 723;
a first through via (unlabeled under 765) that penetrates the upper substrate 762 and the upper dielectric structure 722 and is in contact with the lower conductive structure (unlabeled); and
a second through via (unlabeled under 765) that penetrates the upper substrate 762.
Liu ‘973 fails to disclose
a second through via that is in contact with the bit line; and
a bit-line connection pattern in contact with the first through via and the second through via.
Kim ‘101 teaches
A semiconductor device comprising:
a second through via 194 that is in contact with the bit line BL; and
a bit-line connection pattern 197 / CL4 in contact with the first through via TCP and the second through via 194.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a second through via and a bit-line connection pattern in Liu ‘973. The motivation would be routine engineering design considerations based on its suitability for the intended purpose as discussed in Kim ‘101. See MPEP 2144.07.
Liu ‘973 discloses
10. The semiconductor device as claimed in claim 9, wherein the first 714 overlaps the memory cell structure 724 / 728.
Liu ‘973 discloses
16. The semiconductor device as claimed in claim 9, wherein:
the lower bonding structure 102 further includes a second transistor 726 between the upper substrate 762 and the lower dielectric structure 716, and the upper bonding structure 104 further includes a power capacitor 728 in the upper dielectric structure 722.
Liu ‘973 discloses
17. The semiconductor device as claimed in claim 16, further including a third through via that electrically connects the second transistor (unlabeled) to the power capacitor 728.
Lee ‘468 discloses
18. The semiconductor device as claimed in claim 16, wherein:
the memory cell structure 724 / 728 further includes a cell capacitor 728 ([0085]), and the power capacitor 728 is at a level the same as a level of the cell capacitor.
Liu ‘973 discloses
19. A semiconductor device, comprising:
a lower substrate 710;
a lower dielectric structure 716 on the lower substrate 710;
a transistor 714 between the lower substrate 710 and the lower dielectric structure 716;
a lower conductive structure (unlabeled in Fig. 7) in the lower dielectric structure 716 and connected to the transistor 714;
an upper dielectric structure 722 on the lower dielectric structure 716;
an upper substrate 762 on the upper dielectric structure 716;
a memory cell structure 724 / 728 between the upper substrate 762 and the upper dielectric structure 722, the memory cell structure 724 / 728 including a bit line 728;
a connection dielectric structure 760 on the upper substrate 722;
a bit-line connection pattern 765 in the connection dielectric structure 760;
a first through via 756 that connects the lower conductive structure (unlabeled in Fig. 7) to the bit-line connection pattern 765 and penetrates the upper substrate 762 and the upper dielectric structure 722; and
a second through via (unlabeled under 765) that penetrates the upper substrate 762,
wherein the transistor 714 overlaps the memory cell structure 724 / 718.
Liu ‘973 fails to disclose
a second through via that connects the bit line to the bit-line connection pattern.
Kim ‘101 teaches
a second through via 194 that connects the bit line BL to the bit-line connection pattern 197 / CL4.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to including a second through via and a bit-line connection pattern in Liu ‘973. The motivation would be routine engineering design considerations based on its suitability for the intended purpose as discussed in Kim ‘101. See MPEP 2144.07.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Allowable Subject Matter
Claims 7, 8, 11 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art discloses or teaches:
7. The semiconductor device as claimed in claim 6, wherein:
the connection structure includes a connection conductive structure at a level higher than a level of the bit-line connection pattern, and a thickness of the connection conductive structure is greater than a thickness of the bit-line connection pattern.
8. The semiconductor device as claimed in claim 7, further including a third through via that electrically connects the connection conductive structure to the transistor, wherein the third through via penetrates the upper substrate.
11. The semiconductor device as claimed in claim 9, further including a connection conductive line at a level higher than a level of the bit-line connection pattern, wherein a thickness of the connection conductive line is greater than a thickness of the bit-line connection pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2023/0307353 (Lee), 2023/0178505 (Lee), 2023/0147901 (Park), 2021/0408027 (Takaki) teach a 3-D semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893