DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF KOREA on 10/25/2022.
Election/Restrictions
Applicant's election without traverse of “Species A (claims 1-5, 10 and 20)” in the reply filed on February 06, 2026, is acknowledged.
Claims 6-9 and 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 10 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2021/0313274 A1; Park et al.; 10/2021; (“274”).
Regarding Claim 1. 274 teaches in Figs. 9 and 16 about a semiconductor package, comprising:
a chip-via composite substrate including a substrate (Figs. 9, item 240’), a semiconductor chip (Figs. 9, item 221), and a plurality of through vias (Figs. 9, items 215), wherein the substrate has a first surface (Figs. 9, bottom-side of item 240’) and a second surface (Figs. 9, top-side of item 240’) opposite to the first surface (Figs. 9, in item 240’ top-side is opposite to bottom side) and includes a first region and a second region around the first region (for first and second regions see annotated by Examiner Fig. 9), wherein the semiconductor chip is provided in the first region (Figs. 9, item 221 is provided in the first region) and has chip pads (Fig. 16e, items 124a), which are formed on the first surface (Fig. 16e, items 124a would be connected to a first surface or bottom-side surface of item 140’ when Fig. 16e is vertically mirrored), and circuit patterns (Fig. 16e, items 112) that are electrically connected to the chip pads (Fig. 16e, items 112 are electrically connected to items 124a), and wherein the plurality of through vias is provided in the second region and penetrate the substrate (Examiner annotated Fig. 9, items 215 are provided in the second region and penetrate item 240’);
a first redistribution wiring layer (Fig. 9, item 210’) provided on the first surface of the substrate (Fig. 9, item 210’ is provided on the first surface of item 240’) and having first redistribution wirings (Fig. 9, items 214 and 214”) that are electrically connected to the chip pads and the through vias (Fig. 9, items 214 and 214” are connected to items 221 and 215); and
a second redistribution wiring layer (Fig. 9, item 210, “redistributed layers 210'”, [0136], Ln. 5) provided on the second surface of the substrate (Fig. 9, item 210 is provided on the second surface of item 240’) and having second redistribution wirings (Fig. 9, items 212 and 211) that are electrically connected to the through vias (Fig. 9, items 212 and 211 are electrically connected to items 215).
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Fig. 9, annotated by Examiner from Park et al., “274”
Regarding Claim 2. 274 teaches in Figs. 9 and 16 about a semiconductor package, comprising:
wherein the first redistribution wirings include first uppermost redistribution wirings (Fig. 9, items 214”), which are electrically connected to the chip pads in the first region (Fig. 16e, items 112 are electrically connected to items 124a), and second uppermost redistribution wirings (Fig. 9, items 214), which are electrically connected to the through vias in the second region (Fig. 9, at least farthest-left item 214 is electrically connected to one of items 215).
Regarding Claim 10. 274 teaches in Fig. 9 about a semiconductor package, comprising:
external connection members (items 230) provided on an outer surface of the first redistribution wiring layer and electrically connected to the first redistribution wirings (items 230 are provided on an outer surface of item 210’ and electrically connected to items 214 and 214”).
Regarding Claim 20. 274 teaches in Figs. 9 and 16 about a semiconductor package, comprising:
a chip-via composite substrate (Figs. 9, item 240’) having a first surface (Figs. 9, bottom-side of item 240’) and a second surface (Figs. 9, top-side of item 240’) opposite to the first surface (Figs. 9, in item 240’ top-side is opposite to bottom side), and including a semiconductor chip (Figs. 9, item 221) and a plurality of through vias (Figs. 9, items 215), wherein the semiconductor chip is provided in a first region of the chip-via composite substrate (Figs. 9, item 221 is provided in the first region of item 240’) and has chip pads (Fig. 16e, items 124a) that are exposed from the first surface (Fig. 16e, items 124a would be connected to a first surface or bottom-side surface of item 140’ when Fig. 16e is vertically mirrored), and wherein the plurality of through vias (Figs. 9, items 215) are provided in a second region of the chip-via composite substrate (Examiner annotated Fig. 9, items 215 are provided in the second region) and extend from the first surface to the second surface (Fig. 9, items 215 extend from first surface to second surface of item 240’);
a first redistribution wiring layer (Fig. 9, item 210’) provided on the first surface of the chip-via composite substrate (Fig. 9, item 210’ is provided on the first surface of item 240’) and having first redistribution wirings (Fig. 9, item 214”) that are electrically connected to the chip pads and the through vias (Fig. 9, item 214” are connected to items 221 and 215); and
a second redistribution wiring layer (Fig. 9, item 210, “redistributed layers 210'”, [0136], Ln. 5) provided on the second surface of the chip-via composite substrate (Fig. 9, item 210 is provided on the second surface of item 240’) and having second redistribution wirings (Fig. 9, items 212 and 211) that are electrically connected to the through vias (Fig. 9, items 212 and 211 are electrically connected to items 215).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being obvious over US 2021/0313274 A1; Park et al.; 10/2021; (“274”).
Regarding Claim 3. 274 teaches in Fig. 9 about a semiconductor package, wherein the substrate includes an epoxy resin material.
274 does not teach about a semiconductor package, wherein the substrate includes a silicon material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a substrate that includes a silicon material since silicon serves as the base material for semiconductor manufacturing, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding Claim 4. 274 teaches in Fig. 9 about a semiconductor package, wherein a thickness of the substrate is not disclosed.
274 does not teach about a semiconductor package, wherein a thickness of the substrate is within a range of about 100 μm to about 800 μm.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have found a workable range for the thickness of the substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 5. 274 teaches in Fig. 9 about a semiconductor package, wherein a diameter of each of the through vias is not disclosed.
274 does not teach about a semiconductor package, wherein a diameter of each of the through vias is within a range of about 1 μm to about 50 μm.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have found a workable range for the diameter of each of the through vias, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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