Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/09/2023 was filed before the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al, US 2022/0093512 A1
Chiang teaches:
a transistor comprising an epi (figure 15A);
a substrate (10), wherein the epi (62f) is directly connected to the substrate; and
an isolation layer (60) directly connected to the epi (62) and the substrate (10). (para 14,15, 55-61, Figures 1, 2 and 15A)
2. The semiconductor structure of claim 1, wherein the isolation layer (60) is at a bottom area of a well (20) in the substrate (10). Figure 15 A
3. The semiconductor structure of claim 2, wherein the epi (62) is connected to the substrate at sidewalls of the well. Figure 15 A
4. The semiconductor structure of claim 1, wherein the isolation layer (60) is a crescent shape. Figure 15 A
5. The semiconductor structure of claim 1, wherein the isolation layer comprises at least one of SiN, SiBCN, SiOCN, SiC, and SiOC. (para 52)
6. The semiconductor structure of claim 1, wherein a first portion of the epi directly connected to the isolation layer is greater than a second portion of the epi directly connected to the substrate. Figure 15 A
7. The semiconductor structure of claim 1, wherein the transistor is a bottom transistor in a stacked transistor structure. Figure 15 A
8. The semiconductor structure of claim 1, wherein the transistor is a nanosheet FET. (para 07)
16. A method of forming a semiconductor structure, the method comprising:
forming an isolation layer (60) directly connected to a substrate (10); and
forming a first transistor, wherein forming the first transistor comprises:
growing a first epi (62), wherein the first epi is directly connected to the isolation layer (60) and the substrate (10). (para 14,15, 55-61, Figures 1, 2 and 15A)
17. The method of claim 16, wherein forming the isolation layer comprises: forming a well (20) within the substrate; depositing a dielectric in the well (60); and shaping the dielectric, resulting in the isolation layer. See Figure 15 A Para 48-51
18. The method of claim 17, wherein forming the well within the substrate comprises: recessing a portion of the substrate in a curved shape. Figure 15 A Para 48-51
19. The method of claim 17, wherein the isolation layer is a crescent shape. Figure 15 A
20. The method of claim 19, wherein shaping the dielectric comprises: shaping the dielectric into a crescent shape, wherein the shaping comprises:
etching the dielectric such that there is an exposed portion of the well of the
substrate that is not in direct contact with the dielectric. Figure 15 A Para 48-51
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al, US 20220093512 A1 and further in view of Lin et al, US 20240321646 A1.
Chang teaches:
9. A system, wherein the system comprises: a semiconductor structure, wherein the semiconductor structure comprises:
a first transistor comprising a first epi (62);
a substrate (10), wherein the first epi (62) is directly connected to the substrate (10); and
an isolation layer (60) directly connected to the first epi (62) and the substrate (10). (para 14,15, 55-61, Figures 1, 2 and 15A)
10. The system of claim 9, wherein the isolation layer (60) is at a bottom area of a well (20) in the substrate. Figure 15 A
11. The system of claim 10, wherein the first epi (62) is connected to the substrate at sidewalls of the well. Figure 15 A
12. The system of claim 9, wherein the isolation layer is a crescent shape. Figure 15A
13. The system of claim 9, wherein the isolation layer comprises at least one of SiN, SiBCN, SiOCN, SiC, and SiOC. (para 52)
14. The system of claim 9, wherein a first portion of the first epi directly connected to the isolation layer is greater than a second portion of the first epi directly connected to the substrate. Figure 15 A
But fails to teach:
a second transistor comprising a second epi;
15. The system of claim 9, wherein the first transistor is a bottom transistor and the second transistor is a top transistor in a stacked transistor structure.
Lin teaches:
a second transistor comprising a second epi (413); Figure (6)
And:
wherein the first transistor is a bottom transistor (208, 210, 213) and the second transistor is a top transistor (308, 310, 413) in a stacked transistor structure. Figure 9
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because [f]or enhanced performance and device flexibility, a tunable N-type dipole (such as lanthanum oxide) and a tunable P-type dipole (such as zinc oxide) are combined with multi patterning on CFET for continuously variable Vt Tuning. The combination of multi-patterning (dipole patterning) and multi-annealing (dipole loops) on CFET with n-type and p-type specific dipoles offer volume-less multi-Vt devices that satisfy critical dimension limitations and provide large range of threshold voltages. Para 33 Lin
Conclusion
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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