DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of “Species A (Claims 1-25)” in the reply filed on January 29, 2026, is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9,11,14-19 and 22-25 are rejected under 35 U.S.C. 103 as being obvious over US 2025/0006740 A1; Guler et al.; 01/2025; (“740”).
Regarding Claim 1. 740 teaches in Figs. 4,8 and 9 about a semiconductor structure comprising:
a nanosheet transistor (see Fig. 9, annotated by Examiner) comprising a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig. 4, spaced apart and vertically stacked items 410, “reference to nanowires herein can indicate … nanosheets”, [0031], Ln. 14-15), a gate structure (Fig. 8, item 804) wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig 8, item 804 wraps around items 410), a first source/drain region (Fig. 8, left-to-right the third item 812) located on a first side of the gate structure (Fig. 9, left-side of the gate structure of the transistor) and a second source/drain region (Fig. 8, left-to-right the fourth item 812) located on a second side of the gate structure (Fig. 9, right-side of the gate structure of the transistor), wherein the gate structure has a first gate thickness (see Fig. 9, annotated by Examiner) over a topmost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness (see Fig. 9, annotated by Examiner) that is located between the topmost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets; and
a backside source/drain contact structure (Fig. 9, left-to-right first item 902) electrically contacting the second source/drain region of the nanosheet transistor (Fig. 9, left-to-right the first item 902 electrically contacts left-to-right the fourth item 812).
740 does not teach about a semiconductor structure comprising:
wherein the gate structure has a first gate thickness under a bottommost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness that is located between the bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to vertically mirror the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and the gate structure wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (the drain structures could be also vertically mirrored to achieve the same result), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
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Fig. 9, annotated by Examiner from Guler et al., “740”
Regarding Claim 2. 740 teaches in Figs. 8 and 9 about a semiconductor structure comprising:
a bottom inner spacer structure (see Fig. 9, annotated by Examiner) located laterally adjacent to the first gate thickness of the gate structure (Fig. 9, bottom inner spacer is located laterally adjacent to first gate thickness of the gate structure), and an upper inner spacer (Fig. 8, inner spacer items 432B; see also Fig. 9, annotated by Examiner) located above the bottom inner spacer structure and positioned laterally adjacent to the second gate thickness of the gate structure (Fig. 9, upper inner spacer located above the bottom inner spacer and located laterally adjacent to first gate thickness of the gate structure).
Regarding Claim 3. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein the bottom inner spacer structure comprises a first inner spacer (see Fig. 9, annotated by Examiner) and a second inner spacer (see Fig. 9, annotated by Examiner), wherein the first inner spacer is vertically spaced apart from the second inner spacer by a semiconductor material liner (see Fig. 9, annotated by Examiner).
Regarding Claim 4. 740 teaches in Fig. 4 about a semiconductor structure comprising:
wherein each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner are composed of a semiconductor material not disclosed.
740 does not teach about a semiconductor structure comprising:
wherein each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner are composed of a compositionally same semiconductor material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment using the same semiconductor material for the semiconductor channel material nanosheet and the semiconductor material liner because these two applications of the same material would require a non-conductive material during non-bias conditions (channel not active), since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding Claim 5. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein the bottom inner spacer structure has a first vertical height (Fig. 9, height of the bottom inner spacer structure), and the upper inner spacer has a second vertical height (Fig. 9, height of the upper inner spacer structure), wherein the first vertical height is greater than the second vertical height (Fig. 9, height of the bottom inner spacer structure is greater that height of the upper inner spacer).
Regarding Claim 6. 740 teaches in Fig. 8 about a semiconductor structure comprising:
wherein the first source/drain region is located on a backside source/drain contact placeholder structure (first source/drain region is located on a backside source/drain placeholder item 428).
Regarding Claim 7. 740 teaches in Fig. 8 about a semiconductor structure comprising:
a semiconductor buffer layer (item 432A) located between the first source/drain region and the backside source/drain contact placeholder structure (item 432A is located between the first source/drain region and the backside source/drain contact placeholder structure).
Regarding Claim 8. 740 teaches in Fig. 8 about a semiconductor structure comprising:
a frontside back-end-of-the-line (BEOL) structure (item 802) electrically connected to the first source/drain region by a frontside source/drain contact structure (item 814 electrically connects items 812 and 802).
Regarding Claim 9. 740 teaches in Fig. 9 about a semiconductor structure comprising:
a semiconductor buffer layer (remains of layer of item 432A) located between the second source/drain region and the backside source/drain contact structure (backside contact item 902).
Regarding Claim 11. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein the backside source/drain contact structure has a first portion (portion of item 902 closest to the backside) and a second portion (portion of item 902 closest to the frontside), wherein the second portion of the backside source/drain contact structure is closest to the second source/drain region than the first portion (second portion of item 902 is closest to item 812), and wherein an uppermost segment of the second portion is confined by a protective liner (upper or top most segment of second portion is confined by remains of layer of item 432A).
Regarding Claim 14. 740 teaches in Figs. 4,8 and 9 about a semiconductor structure comprising:
a nanosheet transistor (see Fig. 9, annotated by Examiner) comprising a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig. 4, spaced apart and vertically stacked items 410, “reference to nanowires herein can indicate … nanosheets”, [0031], Ln. 14-15), a gate structure (Fig. 8, item 804) wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig 8, item 804 wraps around items 410), a first source/drain region (Fig. 8, left-to-right the third item 812) located on a first side of the gate structure (Fig. 9, left-side of the gate structure of the transistor) and a second source/drain region (Fig. 8, left-to-right the fourth item 812) located on a second side of the gate structure (Fig. 9, right-side of the gate structure of the transistor), wherein the gate structure has a first gate thickness (see Fig. 9, annotated by Examiner) over a topmost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness (see Fig. 9, annotated by Examiner) that is located between the topmost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets;
a bottom inner spacer structure (see Fig. 9, annotated by Examiner) located laterally adjacent to the first gate thickness of the gate structure (Fig. 9, bottom inner spacer is located laterally adjacent to first gate thickness of the gate structure);
an upper inner spacer (Fig. 8, inner spacer items 432B; see also Fig. 9, annotated by Examiner) located above the bottom inner spacer structure and positioned laterally adjacent to the second gate thickness of the gate structure (Fig. 9, upper inner spacer located above the bottom inner spacer and located laterally adjacent to first gate thickness of the gate structure);
a backside source/drain contact structure (Fig. 9, left-to-right first item 902) electrically contacting the second source/drain region of the nanosheet transistor (Fig. 9, left-to-right the first item 902 electrically contacts left-to-right the fourth item 812); and
backside source/drain contact placeholder structure located beneath the first source/drain region (Fig. 8, backside source/drain placeholder item 428 located beneath first source/drain region), wherein a semiconductor buffer layer (Fig. 8, item 432A) is located between the first source/drain region and the backside source/drain contact placeholder structure (Fig. 8, item 432A is located between the first source/drain region and the backside source/drain contact placeholder structure).
740 does not teach about a semiconductor structure comprising:
wherein the gate structure has a first gate thickness under a bottommost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness that is located between the bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to vertically mirror the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and the gate structure wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (the drain structures could be also vertically mirrored to achieve the same result), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 15. Same as rejection for claim 3.
Regarding Claim 16. Same as rejection for claim 4.
Regarding Claim 17. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein a topmost surface of the bottom inner spacer structure is at a first level, a topmost surface of the semiconductor buffer layer is at a second level, a topmost surface of the backside source/drain contact placeholder structure is located at a third level, and a bottommost surface of the bottom inner spacer structure is located at a fourth level, wherein first level is less than the second level, and the third level is less than fourth level.
740 does not teach about a semiconductor structure comprising:
wherein a topmost surface of the bottom inner spacer structure is at a first level, a topmost surface of the semiconductor buffer layer is at a second level, a topmost surface of the backside source/drain contact placeholder structure is located at a third level, and a bottommost surface of the bottom inner spacer structure is located at a fourth level, wherein first level is greater than the second level, and the third level is greater than fourth level.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to vertically mirror the plurality of semiconductor channel material nanosheets, inner spacers, and the gate structure to achieve the disclosed relations between first, second, third and fourth levels (the drain structures could be also vertically mirrored to achieve the same result), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 18. Same as rejection for claim 5.
Regarding Claim 19. Same as rejection for claim 11.
Regarding Claim 22. Same as rejection for claim 8.
Regarding Claim 23. 740 teaches in Figs. 4,8 and 9 about a semiconductor structure comprising:
a nanosheet transistor (see Fig. 9, annotated by Examiner) comprising a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig. 4, spaced apart and vertically stacked items 410, “reference to nanowires herein can indicate … nanosheets”, [0031], Ln. 14-15), a gate structure (Fig. 8, item 804) wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (Fig 8, item 804 wraps around items 410), a first source/drain region (Fig. 8, left-to-right the third item 812) located on a first side of the gate structure (Fig. 9, left-side of the gate structure of the transistor) and a second source/drain region (Fig. 8, left-to-right the fourth item 812) located on a second side of the gate structure (Fig. 9, right-side of the gate structure of the transistor), wherein the gate structure has a first gate thickness (see Fig. 9, annotated by Examiner) over a topmost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness (see Fig. 9, annotated by Examiner) that is located between the topmost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets;
a bottom inner spacer structure having a first vertical height (Fig. 9, height of the bottom inner spacer structure) and located laterally adjacent to the first gate thickness of the gate structure (Fig. 9, bottom inner spacer is located laterally adjacent to first gate thickness of the gate structure), the bottom inner spacer structure comprising a first inner spacer (see Fig. 9, annotated by Examiner) and a second inner spacer (see Fig. 9, annotated by Examiner) that are vertically spaced apart by a semiconductor material liner (see Fig. 9, annotated by Examiner); and
an upper inner spacer having a second vertical height (Fig. 9, height of the upper inner spacer structure) and located above the bottom inner spacer structure and positioned laterally adjacent to the second gate thickness of the gate structure (Fig. 9, upper inner spacer located above the bottom inner spacer and located laterally adjacent to first gate thickness of the gate structure), wherein the first vertical height is greater than the second vertical height (Fig. 9, height of the bottom inner spacer structure is greater that height of the upper inner spacer).
740 does not teach about a semiconductor structure comprising:
wherein the gate structure has a first gate thickness under a bottommost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets that is greater than a second gate thickness that is located between the bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to vertically mirror the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and the gate structure wrapped around the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets (the drain structures could be also vertically mirrored to achieve the same result), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 24. 740 teaches in Figs. 4,8 and 9 about a semiconductor structure comprising:
wherein the first vertical height is more than the first gate thickness and the second vertical height is more than the second gate thickness.
740 does not teach about a semiconductor structure comprising:
wherein the first vertical height is substantially equal to the first gate thickness and the second vertical height is substantially equal to the second gate thickness.
It would have been an obvious matter of design choice to slightly adjust the vertical height of the gates thickness to substantially match the first and second vertical heights, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 25. Same as rejection for claim 4.
Claims 10,12-13 and 20-21 are rejected under 35 U.S.C. 103 as being obvious over US 2025/0006740 A1; Guler et al.; 01/2025; (“740”) in view of US 2023/0352567 A1; Chung et al.; 11/2023; (“567”).
Regarding Claim 10. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets is rectangular shaped (Fig. 4, spaced apart and vertically stacked items 410 have a rectangular shape).
740 does not teach about a semiconductor structure comprising:
wherein each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets is dumb-bell shaped having a middle portion having a first thickness and two end portions having a second thickness that is greater than the first thickness.
567 teaches in Fig. 15D about a semiconductor structure comprising:
wherein each semiconductor channel material nanosheet (items 215e-215h) of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets is dumb-bell shaped (items 215e-215h have a dumb-bell shape) having a middle portion having a first thickness and two end portions having a second thickness that is greater than the first thickness (items 215e-215h have a middle portion thickness smaller than the thickness of the two end portions).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the dumb-bell shaped semiconductor channel material nanosheets of 567 to increase the contact surface area of the gate structure and the semiconductor channel material in 740 in order to provide greater “gate stack … wrapping around each of the channel
layers” as taught by 567 in at least Fig. 3A and [0029], Ln. 19-21.
Regarding Claim 12. 740 teaches in Fig. 9 about a semiconductor structure comprising:
wherein the first portion has a first critical dimension (left-to-right width of the first portion from item 902), and the second portion has a second critical dimension (left-to-right width of the second portion from item 902), wherein the second critical dimension is less than the first critical dimension (left-to-right width of the second portion is less than the width of the first portion from item 902).
Regarding Claim 13. 567 teaches in Fig. 15D about a semiconductor structure comprising:
wherein the first portion of the backside source/drain contact structure (backside of source/drain contact structure item 275) contacts a backside interconnect structure (item 275 contacts item 277).
Regarding Claim 20. Same as rejection for claim 12.
Regarding Claim 21. Same as rejection for claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897