DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(e) based upon provisional application PRO 63/412,250 filed on 09/30/2022.
Election/Restrictions
Applicant's election without traverse of “Group I, Species B (claims 1-3,6-9,11, and 13-17)” in the reply filed on November 25, 2025, is acknowledged.
Claims 4-5,10,12 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0359469 A1; Chung et al.; 11/2022; (“469”).
Regarding Claim 1. 469 teaches in Figs. 3 and 5 about a semiconductor device assembly, comprising:
a redistribution layer (RDL) (Fig. 3, item 180) including a top surface (Fig. 3, top surface of item 180, along a Z-direction) and a side surface (Fig. 3, side surface of item 180, along a X-direction) intersecting the top surface (Fig. 3, X-direction intersects Z-direction); and
a mold material (Fig. 3, material of mold items 170 and 370) encasing and directly coupled to at least a portion of the top surface and the side surface of the RDL (Fig. 3, material of mold items 170 and 370 are directly coupled to at least a portion of the top and side surfaces of item 180).
Regarding Claim 2. 469 teaches in Fig. 3 about a semiconductor device assembly, comprising:
a semiconductor device (item 100La) coupled to the top surface (item 100La is coupled to top surface of item 180), and wherein the mold material further encases the semiconductor device (item 100La is encased by mold item 170).
Regarding Claim 6. 469 teaches in Fig. 5 about a semiconductor device assembly, comprising:
wherein the mold material encases and is directly coupled to the entirety of the side surface of the RDL (mold material of item 370 is directly coupled to the entirety of the side surface of RDL item 180).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 15-17 are rejected under 35 U.S.C. 103 as being obvious over US 2022/0359469 A1; Chung et al.; 11/2022; (“469”).
Regarding Claim 7. 469 teaches in Fig. 5 about a semiconductor device assembly, comprising:
wherein a bottom surface of the RDL does not defines a bottom surface of the assembly (assembly item 1000a), and wherein the mold material extends past the bottom surface of the assembly at the side surface of the RDL.
469 does not teach about a semiconductor device assembly, comprising:
wherein a bottom surface of the RDL defines a bottom surface of the assembly, and wherein the mold material extends to the bottom surface of the assembly at the side surface of the RDL.
Thus, it would have been an obvious matter of design choice to extend the mold material past the bottom surface of the RDL to increase, if needed, the electrical insulation of the device assembly, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 8. 469 teaches in Figs. 3 and 5 about a semiconductor device assembly, comprising:
a redistribution layer (RDL) (Fig. 3, item 180) including a top surface (Fig. 3, top surface of item 180, along a Z-direction), a bottom surface (Fig. 3, bottom surface of item 180, along a Z-direction) opposite the top (Fig. 3, the bottom surface of item 180 is opposite to the top surface of item 180, along a Z-direction), and a side surface extending between the top surface and the bottom surface (Fig. 3, side surface of item 180 extends between top and bottom surfaces of item 180), wherein the side surface is perpendicular relative to the top surface and the bottom surfaces;
a semiconductor device (Fig. 3A, item 100La) coupled to the top surface (Fig. 3A, item 100La is coupled to top surface of item 180); and
a mold material (Fig. 3, material of mold items 170 and 370) encasing the semiconductor device and directly coupled to at least a portion of the top surface and the side surface of the RDL (Fig. 3, material of mold items 170 and 370 are directly coupled to at least a portion of the top and side surfaces of item 180).
469 does not teach about a semiconductor device assembly, comprising:
wherein the side surface is sloped relative to the top surface and the bottom surfaces.
Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have sloped a vertical side or not to accommodate for specific design requirements (shape change from rectangular to trapezoidal), since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding Claim 9. 469 teaches in Fig. 3 about a semiconductor device assembly, comprising:
wherein the RDL includes a RDL layer (item 182), and wherein the RDL layer has a side surface (side surface of item 182).
469 does not teach about a semiconductor device assembly, comprising:
wherein the RDL includes a bottom RDL layer, a middle RDL layer, and a top RDL layer, and wherein each of the bottom, the middle, and the top RDL layers has a side surface.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate a RDL layer to accommodate for as much redistribution as required by the given design, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 15. 469 teaches in Fig. 3 about a semiconductor device assembly, comprising:
wherein the RDL includes a single RDL layer (item 182).
469 does not teach about a semiconductor device assembly, comprising:
wherein the RDL further includes a plurality of additional RDL layers.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate a RDL layer to accommodate for as much redistribution as required by the given design, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 16. 469 teaches in Fig. 3 about a semiconductor device assembly, comprising:
wherein the RDL layer includes a conductive material (item 182) and a dielectric material (item 186).
469 does not teach about a semiconductor device assembly, comprising:
wherein each of the top, middle, and bottom RDL layers includes a conductive material and a dielectric material.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the conductive and dielectric materials of the single RDL layer to accommodate for as much redistribution as required by the given design, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 17. Same as rejection for claim 7.
Allowable Subject Matter
Claims 3,11 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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