DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20220262751) in view of PARK et al. (US 20220199577 ).
Regarding claim 1, Zhang discloses that an Application Specific Integrated Circuit (ASIC) for mining cryptocurrency, the ASIC comprising:
a plurality of dies arranged to perform application-specific processing;
a first die 34 arranged to control the plurality of second dies 33 or 32, wherein the control die 34 uses a larger node 20 size than the plurality of hash dies 31;
one or more interconnectors electrically that couple the first die to the plurality of second dies; and
an integrated circuit package enclosing the first die and the plurality of second dies 33 or 32 (Fig. 2B-2C).
Zhang fails to specify that the first die is control die and the second dies are hash (a cryptographic processor or ASIC) die.
However, PARK suggests that the first die is control die 61 and the second dies are hash (crypto die) die 62 (para. 0047, Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Zhang with the first die is control die and the second dies are hash (crypto die) die as taught by PARK in order to enhance Application specified IC to using different types of integrated circuits (para. 0047) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Zhang & Park disclose that an interposer 100 on which the plurality of hash dies 62 and the control die 61 (Park, para. 0047) are mounted and through which the plurality of hash dies are electrically coupled to the control die; or a plurality of interconnection elements on which the plurality of hash dies are mounted and through which the plurality of hash dies are electrically coupled to the control die (para. 0047, Fig. 1).
Reclaim 3, Zhang & Park disclose that the plurality of hash dies 62 include one or more sensor probes arranged to monitor one or more characteristics of the plurality of hash dies, wherein the one or more characteristics include at least one of a process, a voltage, or a temperature; wherein the plurality of hash dies provide one or more sensor signals to the control die relating to the one or more characteristics monitored by the one or more sensor probes; and wherein the control die includes measurement logic arranged to monitor the one or more characteristics based on the one or more sensor signals (Park, Fig. 1).
Reclaim 4, Zhang & Park disclose that an Application Specific Integrated Circuit (ASIC) for application-specific circuitry, the ASIC comprising:
one or more hash dies 62 (Para. 0047, Fig. 1) arranged to perform application-specific processing; and
a control die 61 that is arranged to control the one or more hash dies (Zhang’s Fig. 2B-C in view of Park’s Fig. 1).
Reclaim 5, Zhang & Park disclose that the control die 61 uses a larger node size than the one or more hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 6, Zhang & Park disclose that one or more interconnectors electrically coupling the control die and the one or more hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 7, Zhang & Park disclose that the one or more interconnectors include an interposer 100 (Park, Fig. 1), wherein the one or more hash dies 62 and the control die 61 are mounted on the interposer, and wherein the one or more hash dies are electrically coupled to the control die through the one or more interconnectors (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 8, Zhang & Park disclose that the one or more hash dies 62 and the control die 61 are mounted on a surface of the interposer 110 (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 9, Zhang & Park disclose that at least one through silicon via (TSV) 120 (Park, Fig. 1) that passes through the interposer 110 from a first point on the surface of the interposer to a second point on a second surface of the interposer, wherein the second point of the TSV is a connector configured to communicate with an external device, wherein the first point of the TSV is coupled to at least one of the one or more hash dies or the control die (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 10, Zhang & Park disclose that the one or more hash dies 62 and the control die 61 are physically coupled and communicatively coupled to the interposer via 120 at least one interconnector of the one or more interconnectors 130, wherein the at least one interconnector includes at least one of a microbump 43 or a hybrid bond 131 (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 11, Zhang & Park disclose that the one or more interconnectors connect 132 the one or more hash dies 62 and the control die 61 directly, physically, and electrically (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 12, Zhang & Park disclose that the one or more interconnectors include at least one of microbumps 43 or hybrid bonds 131 (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 13, Zhang & Park disclose that the one or more hash dies 62 are mounted on a surface of the control die 61 via the one or more interconnectors 131 (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 14, Zhang & Park disclose that at least one through silicon via (TSV) 120 that passes through the control die 61 from a first point on the surface of the control die to a second point on a second surface of the control die, wherein the second point of the TSV is a connector configured to communicate with an external device, wherein the first point of the TSV is coupled to the one or more hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park, note variation of TSVs).
Reclaim 15, Zhang & Park disclose that the control die 61 includes measurement logic arranged to monitor one or more characteristics of the one or more hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 16, Zhang & Park disclose that one or more sensor probes are incorporated into the one or more hash dies, wherein the one or more sensor probes are arranged to sense the one or more characteristics(Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 17, Zhang & Park disclose that the one or more characteristics include at least one of temperature or voltage (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 18 , Zhang & Park disclose that the one or more hash dies 62 are a plurality of hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Reclaim 19, Zhang & Park disclose that the one or more hash dies include a plurality of hash cores 62 (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Regarding claim 20, Zhang & Park disclose that a hash board for mining cryptocurrency comprising:
a plurality of Application Specific Integrated Circuits (ASICs) 62;
a circuit board 100 or 11, wherein the plurality of ASICs 62 are mounted on the circuit board, wherein the plurality of ASICs are electrically coupled through the circuit board 11; and
a controller 61 arranged to control the plurality of ASICs, wherein the plurality of ASICs includes:
one or more hash dies 62 arranged to perform application-specific processing; and a
control die 61 that is arranged to control the one or more hash dies (Zhang’s Fig. 2B-C in view of Fig. 1, Park).
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899