DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20220199577) in view of Kakkireni et al. (US 20220413593).
Regarding claim 1, Park discloses that an Application Specific Integrated Circuit (ASIC) for mining cryptocurrency, the ASIC comprising:
a plurality of hash dies 62 (para. 0047) arranged to perform application-specific processing;
a control die 61 (para. 0047, note: CPU GPU cryptographic processor ASIC) arranged to control the plurality of hash dies, wherein the control die 61 uses a larger node size than the plurality of hash dies (Fig. 3);
one or more interconnectors 102, 130, 120, 110 electrically coupling the control die 61 to the plurality of hash dies; and
an integrated circuit package enclosing the control die and the plurality of hash dies (Fig. 3).
Park fails to specify that the control die includes a phase-locked loop to provide one or more clock signals to the hash dies via the interconnectors, wherein the plurality of hash dies include one or more sensor probes to provide sensor signals to the control die, and wherein the control die apportions the application-specific processing among the plurality of hash dies based on a comparison between a monitored characteristic indicated by the sensor signals and a threshold .
However, Kakkireni suggests that the control die includes a phase-locked loop to provide one or more clock signals to the hash dies via the interconnectors, wherein the plurality of hash dies include one or more sensor probes to provide sensor signals to the control die, and wherein the control die apportions the application-specific processing among the plurality of hash dies based on a comparison between a monitored characteristic indicated by the sensor signals and a threshold (para. 0046 ,note “- - chiplets 110a, 110b, 110c, and 110d may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components used to support the processors and software clients running within the SIP 104” & para. 0255, note: “sensors located throughout the second chiplet may measure sensory parameters. Sensors (e.g., sensors 116b) may be positioned throughout a second chiplet (e.g., slave chiplet 110b) die, and may measure and relay sensory parameters including power, voltage, current, and/or temperature information to the second chiplet power controller (e.g., slave chiplet power controller 112b”, Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Park with the control die includes a phase-locked loop to provide one or more clock signals to the hash dies via the interconnectors, wherein the plurality of hash dies include one or more sensor probes to provide sensor signals to the control die, and wherein the control die apportions the application-specific processing among the plurality of hash dies based on a comparison between a monitored characteristic indicated by the sensor signals and a threshold as taught by Kakkireni in order to enhance producing variety of system with different chips and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Park & Kakkireni disclose that the one or more interconnectors include at least one of:
an interposer 120 on which the plurality of hash dies 62 and the control die 61 are mounted and through which the plurality of hash dies are electrically coupled to the control die; or a plurality of interconnection elements on which the plurality of hash dies are mounted and through which the plurality of hash dies are electrically coupled to the control die (Park ,Fig. 3).
Reclaim 3, Park & Kakkireni disclose that one or more sensor probes are arranged to monitor one or more characteristics of the plurality of hash dies, wherein the one or more characteristics include at least one of a process, a voltage, or a temperature; and wherein the control die includes measurement logic arranged to monitor the one or more characteristics based on the one or more sensor signals (Kakkireni, para. 0046 & 0225).
Regarding claim 4, Park & Kakkireni disclose that an Application Specific Integrated Circuit (ASIC) for application-specific circuitry, the ASIC comprising:
one or more hash dies 62 arranged to perform application-specific processing; and
a control die 61 arranged to control the one or more hash dies 62 (Park, Fig. 3), wherein the control die includes a phase-locked loop to provide one or more clock signals to the one or more hash dies, wherein the one or more hash dies include one or more sensor probes to provide sensor signals to the control die, and wherein the control die apportions the application-specific processing among the one or more hash dies based on a comparison between a monitored characteristic indicated by the sensor signals and a threshold Kakkireni, para. 0046 & 0225).
Reclaim 5, Park & Kakkireni disclose that the control die uses a larger node size than the one or more hash dies (Park, Fig. 3).
Reclaim 6, Park & Kakkireni disclose that one or more interconnectors electrically coupling the control die and the one or more hash dies, wherein the control die provides the one or more clock signals to the one or more hash dies via the one or more interconnectors (Park, Fig. 3).
Reclaim 7, Park & Kakkireni disclose that the one or more interconnectors include an interposer, wherein the one or more hash dies and the control die are mounted on the interposer, and wherein the one or more hash dies are electrically coupled to the control die through the one or more interconnectors (Park, Fig. 3).
Reclaim 8, Park & Kakkireni disclose that the one or more hash dies and the control die are mounted on a surface of the interposer 120 (Fig. 3, Park).
Reclaim 9, Park & Kakkireni disclose that at least one through silicon via (TSV) 120 that passes through the interposer from a first point on the surface of the interposer to a second point on a second surface of the interposer, wherein the second point of the TSV is a connector configured to communicate with an external device, wherein the first point of the TSV is coupled to at least one of the one or more hash dies or the control die (Fig. 3, Park).
Reclaim 10, Park & Kakkireni disclose that the one or more hash dies and the control die are physically coupled and communicatively coupled to the interposer via at least one interconnector of the one or more interconnectors, wherein the at least one interconnector includes at least one of a microbump or a hybrid bond (Park, Fig. 3).
Reclaim 11, Park & Kakkireni disclose that the one or more interconnectors connect the one or more hash dies and the control die directly, physically, and electrically (Park, Fig. 3).
Reclaim 12, Park & Kakkireni disclose that the one or more interconnectors include at least one of microbumps or hybrid bonds (Fig. 3, Park).
Reclaim 13, Park & Kakkireni disclose that the one or more hash dies are mounted on a surface of the control die via the one or more interconnectors (Park, Fig. 4).
Reclaim 14, Park & Kakkireni disclose that at least one through silicon via (TSV) 120 that passes through the control die from a first point on the surface of the control die to a second point on a second surface of the control die, wherein the second point of the TSV is a connector configured to communicate with an external device, wherein the first point of the TSV is coupled to the one or more hash dies (Park, Fig. 3-4).
Reclaim 15, Park & Kakkireni disclose that the control die includes measurement logic arranged to monitor one or more characteristics of the one or more hash dies (Park, Fig. 3-4).
Reclaim 16, Park & Kakkireni disclose that one or more sensor probes are incorporated into the one or more hash dies, wherein the one or more sensor probes are arranged to sense the one or more characteristics (Park, Fig. 3-4).
Reclaim 17, Park & Kakkireni disclose that the one or more characteristics include at least one of temperature or voltage (Park, Fig. 3-4).
Reclaim 18, Park & Kakkireni disclose that the one or more hash dies are a plurality of hash dies (Park, Fig. 3-4).
Reclaim 19, Park & Kakkireni disclose that the one or more hash dies include a plurality of hash cores (Park, Fig. 3-4).
Regarding claim 20, Park & Kakkireni disclose that a hash board for mining cryptocurrency comprising:
a plurality of Application Specific Integrated Circuits (ASICs);
a circuit board 11, wherein the plurality of ASICs 1000F are mounted on the circuit board, wherein the plurality of ASICs are electrically coupled through the circuit board (Park. Fig. 3 & 4); and
a controller 61 & 62 arranged to control the plurality of ASICs, wherein each of the plurality of ASICs includes: one or more hash dies 62 arranged to perform application-specific processing; and
a control die 61 arranged to control the one or more hash dies; and
one or more interconnectors 120, 132, 102 electrically coupling the control die 61 and the one or more hash dies 62; wherein
the control die 61 includes a phase-locked loop to provide one or more clock signals to the one or more hash dies via the one or more interconnectors, wherein the one or more hash dies include one or more sensor probes to provide sensor signals to the control die, and wherein the control die apportions the application-specific processing among the one or more hash dies based on a comparison between a monitored characteristic indicated by the sensor signals and a threshold (Park in view of Kakkireni’s Fig. 1).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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