DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(e) based upon provisional application PRO 63/522,522 filed on 06/22/2023.
Election/Restrictions
Applicant's election without traverse of “Invention I (Claims 1-15)” in the reply filed on 02/06/2026 (including an amendment to claims filed on 03/24/2026), is acknowledged. Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The object “isolation layer” is claimed to “comprise a plurality of vertcially stacked isolation layers; therefore, it is unclear how a part could comprise of a plurality of itself. Also, the term “vertcially” is believed to be a typographical error.
Application will be examined with Claim 3 being best interpreted by the Examiner in the following manner:
The semiconductor device of claim 2, wherein the isolation stack comprises a plurality of vertically stacked isolation layers, and the substrate layer is disposed between two adjacent isolation layers among the isolation layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 11-12 are rejected under 35 U.S.C. 103 as being obvious over US 2024/0128333 A1; Xie et al.; 04/2024; (“333”) in view of US 11,615,987 B2; Huang et al.; 03/2023; (“987”).
Regarding Claim 1. 333 teaches in Figs. 10A and 10B about a semiconductor device comprising:
a 1st source/drain region (Fig. 10A, left-side item 36);
a 2nd source/drain region (Fig. 10A, right-side item 36);
a channel structure (Fig. 10A, items 20NS) connecting the 1st source/drain region to the 2nd source/drain region (Fig. 10A, items 20NS connect left-side and right-side items 36);
a gate structure surrounding the channel structure (Fig. 10B, item 42 surrounds items 20NS);
333 does not teach about a semiconductor device comprising:
a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region; and
a 1st backside spacer at a lateral side of the backside contact structure.
987 teaches in Fig. 23 about a semiconductor device comprising:
a backside contact structure (items 266), below the 1st source/drain region (in the negative Z-direction from item 232S), connected to the 1st source/drain region (item 266 is electrically connected to item 232S); and
a 1st backside spacer (item 262) at a lateral side of the backside contact structure (item 262 at lateral sides of item 266).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the backside spacer at lateral sides of the backside contact structure of 987 to provide a surrounding dielectric barrier layer for the backside contact structure in 333 as taught by 987 in the cross-sectional XY-plane view of Fig. 22.
Regarding Claim 2. 333 teaches in Fig. 10A about a semiconductor device comprising:
an isolation stack (composed of items 26,28 and 41), below the gate structure (items 26,28 and 41 are below item 42), comprising at least one isolation layer (item 26 or 28) and a substrate layer (item 41) which are vertically stacked (items 26,28 and 41 are vertically stacked); and
a backside isolation structure (item 14) below the isolation stack.
Regarding Claim 3. 333 teaches in Fig. 10A about a semiconductor device comprising:
wherein the isolation stack comprises a plurality of vertically stacked isolation layers (items 26 and 28), and the substrate layer is disposed between two adjacent isolation layers among the isolation layers (item 41 is disposed between items 26 and 28).
Regarding Claim 11. 333 teaches in Figs. 10A and 10B about a semiconductor device comprising:
a 1st source/drain region (Fig. 10A, left-side item 36);
a 2nd source/drain region (Fig. 10A, right-side item 36);
a channel structure (Fig. 10A, items 20NS) connecting the 1st source/drain region to the 2nd source/drain region (Fig. 10A, items 20NS connect left-side and right-side items 36);
a gate structure surrounding the channel structure (Fig. 10B, item 42 surrounds items 20NS);
an isolation stack (Fig. 10A, composed of items 26,28 and 41), below the gate structure (Fig. 10A, items 26,28 and 41 are below item 42), comprising a plurality of isolation layers (Fig. 10A, items 26 and 28) and a substrate layer (Fig. 10A, item 41) disposed between two adjacent isolation layers among the isolation layers (Fig. 10A, item 41 disposed between two adjacent isolation layer items 26 and 28).
333 does not teach about a semiconductor device comprising:
a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region
987 teaches in Fig. 23 about a semiconductor device comprising:
a backside contact structure (items 266), below the 1st source/drain region (in the negative Z-direction from item 232S), connected to the 1st source/drain region (item 266 is electrically connected to item 232S).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the backside contact structure of 987 to provide a backside contact structure for the 1st source/drain region in 333 as taught by 987 in Fig. 23.
Regarding Claim 12. 987 teaches in Fig. 23 about a semiconductor device comprising:
a 1st backside spacer (item 262) at a lateral side of the backside contact structure (item 262 at lateral sides of item 266).
Allowable Subject Matter
Claims 4-10 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/ Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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