DETAILED ACTION
Contents
I. Notice of Pre-AIA or AIA Status 4
II. Priority 4
III. Pertinent Prosecution History 5
IV. Claim Status 5
V. Reissue Requirements 6
VI. Reissue Oath/Declaration 7
VII. Specification Objections 9
VIII. Claim Interpretation 11
A. Lexicographic Definitions 11
B. 35 U.S.C. § 112 6th Paragraph 12
IX. Claim Rejections - 35 USC § 251 12
A. Oath/Declaration 12
X. Claim Rejections – 35 USC § 103 12
A. Claims 1-3, 5-13, 18-23 and 53 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”). 13
B. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Shinohara et al. (U.S. Publication No. 2009/0200680) (“Shinohara”). 28
C. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Itoh et al. (U.S. Publication No. 20080122064) (“Itoh”). 30
D. Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Kodama et al. (U.S. Publication No. 2008/0157393) (“Kodama”). 32
E. Claims 51 and 52 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Leedy (U.S. Publication No. 20140043883). 34
XI. Response to Arguments 37
A. Oath/Declaration 37
B. Specification Objection(s) 37
C. Drawings Objection(s) 38
D. 35 U.S.C. § 112, Second Paragraph, Rejections 38
E. 35 U.S.C. § 251 Original Patent Requirement 38
F. 35 U.S.C. § 103 Rejections 39
XII. Conclusion 40
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant filed the instant reissue application 18/375,197 (“‘197 Reissue Application”) on 29 September 2023 for U.S. Application No. 16/533,003 (“‘003 Application”), filed 06 August 2019, now U.S. Patent No. 11,139,283 (“‘283 Patent”), issued 05 October 2021, which claims domestic priority to Provisional Application No. 62/784,426 (“‘426 Prov Application”), filed 22 December 2018. However, in examination of the entirety of the ‘426 Prov Application submission, the Examiner finds insufficient disclosure to any direct bonding of various chiplet driver faces to one another at approximately room temperature.
Thus, the Examiner concludes that for examination purposes the instant ‘197 Reissue Application has an effective filing data of 06 August 2019, which is the filing date of the ‘003 Application.
Pertinent Prosecution History
As set forth supra, Applicant filed the application for the instant ‘197 Reissue Application on 29 September 2023. The Examiner finds that the instant ‘197 Reissue Application included a preliminary amendment (“Sept 2023 Preliminary Amendment”) to the claims (“Sept 2023 Claim Amendment”). The Sept 2023 Claim Amendment includes an amendment: Adding new claims 24-50.
The Office issued a Non-Final Office action on 24 January 2025 (“Jan 2025 Non-Final Office Action”). In particular, the Jan 2025 Non-Final Office Action provided rejections for claims 1-50 (“Rejected Claims”) under 35 U.S.C. §§ 112(b), 103 and 251. 1
On 24 June 2025, Applicant filed a Reply to Non-Final Office Action (“June 2025 Applicant Response”). The June 2025 Applicant Response contained: “Remarks,” a new Oath/Declaration (“June 2025 Declaration”), “Amendments to the Specification” (“June 2025 Spec Amendment”), and “Amendments to the Claims” (“June 2025 Claim Amendment”) including: once2 amended original claims 1, 17, 18 and 21-23; original claims 2-16, 19 and 20; new3 claims 51-53; and canceled new4 claims 24-50.
Claim Status
The Examiner finds that the claim status in the instant ‘197 Reissue Application is as follows:
Claim(s) 1, 17, 18 and 21-23 (Original and once amended)
Claim(s) 2-16, 19 and 20 (Original)
Claim(s) 51-53 (New)
Claim(s) 24-50 (New and canceled)
Thus, the Examiner concludes that claims 1-23 and 51-53 are pending in the instant ‘197 Reissue Application. Claims 1-23 and 51-53 are examined (“Examined Claims”).
Reissue Requirements
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the ‘283 Patent is or was involved. These proceedings would include interferences, reissues, reexaminations, post-grant proceedings and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
The Examiner notes that Amendment practice for Reissue Applications is NOT the same as for non-provisional applications. See MPEP §§ 1413 and 1453. Reissue application amendments must comply with 37 CFR 1.173, while non-provisional application amendments must comply with 37 CFR 1.121. Particularly,
Manner of making amendments under 37 CFR 1.173:
All markings (underlining and bracketing) are made relative to the original patent text, 37 CFR 1.173(g) (and not relative to the prior amendment).
For amendments to the abstract, specification and claims, the deleted matter must be enclosed in brackets, and the added matter must be underlined. See 37 CFR 1.173(d).
For amendments to the drawings, any changes to a patent drawing must be submitted as a replacement sheet of drawings which shall be an attachment to the amendment document. Any replacement sheet of drawings must be in compliance with § 1.84 and shall include all of the figures appearing on the original version of the sheet, even if only one figure is amended. Amended figures must be identified as "Amended," and any added figure must be identified as "New." In the event that a figure is canceled, the figure must be surrounded by brackets and identified as "Canceled." All changes to the drawing(s) shall be explained, in detail, beginning on a separate sheet accompanying the papers including the amendment to the drawings. See 37 CFR 1.173(d)(3).
The Examiner further notes that all amendments to the instant ‘197 Reissue Application must comply with 37 CFR 1.173(b)-(g).
Reissue Oath/Declaration
The Examiner finds that the June 2025 Declaration filed by Applicant is defective. The Examiner finds that the June 2025 Declaration filed by Applicant states,
Patentee claimed less than they had a right to claim, in particular, without omitting the features of “a NAND wafer having a memory storage array therein, the NAND wafer having element contacts electrically connected with electrically conductive structure of the substrate, the NAND wafer being coupled to the first surface of the substrate,” “a bitline driver chiplet configured to function as a bitline driver for the NAND wafer, the bitline driver chiplet being elongated along the first direction and mounted to a front surface of the NAND wafer,” “a wordline driver chiplet configured to function as a wordline driver for the NAND wafer, the wordline driver chiplet being elongated along the second direction and mounted to the front surface of the NAND wafer,” and “front surfaces of the bitline driver chiplet and the wordline driver chiplet are arranged in a single common plane and are entirely contained within an outer periphery of the front surface of the NAND wafer,” from original patent claim 1, original patent claim 1 was unduly narrow.
(June 2025 Declaration).
However, the June 2025 Claim Amendment includes an amendment that: (1) amends the “mount[ing]” claim requirement in original independent claims 1, 21 and 23; (2) cancels new claims 24-50; and (3) added new claims 51-53. With respect to the amendments to original independent claims 1, 21 and 23, : (a) original claim 1 now requires the “mounting of the bitline/wordline drivers to the front surface of the NAND wafer” to instead require “a front surface of the bitline/wordline driver chiplet[s] [being] directly bonded at approximately room temperature to the front surface of the NAND wafer;” (2) original claim 21 now requires “a front surface of at least one of the plurality of chipsets [being] directly bonded to a front surface of at least one microelectronic element of the plurality of microelectronic elements;” and (3) original claim 23 now requires the “mounting [of] a bitline/wordline driver chiplet[s]s to the front surface of the NAND wafer” to instead require “directly bonding a bitline/wordline driver chiplet[s]s to the front surface of the NAND wafer.”
From this perspective, since claims 24-50 have been canceled and claims 1, 21 and 23 have been materially narrowed, the Examiner first finds that the instant ‘197 Reissue Application is no longer deemed a broadening reissue application. Thus, the statement of “Patentee claimed less than they had a right to claim….” in the June 2025 Declaration is deemed incorrect and should be –… claimed more than…–.
Similarly, in light of the June 2025 Claim Amendment, the Examiner finds that the June 2025 Declaration is further defective because it does not correctly identify at least one error which is relied upon to support the reissue application (i.e., a single word, phrase, or expression in the specification or in an original claim, and how it renders the original patent wholly or partly inoperative or invalid). See 37 CFR 1.175 and MPEP § 1414.
The Examiner further notes that a new oath or declaration is required where all errors previously identified in the reissue oath/declaration are no longer being relied upon as the basis for reissue. In this case, “Applicant must explicitly identify on the record an error being relied upon as the basis for reissue.” (See MPEP § 1414.03(1); emphasis added).
Specification Objections
The disclosure is objected to because of the following informalities:
In col. 12, ln. 65, change “Fig. 49” to - - Fig. 9 - -.
In col. 13, ln. 7, change “Fig. 49” to - - Fig. 9 - -.
In col. 13, ln. 21, change “Fig. 49” to - - Fig. 9 - -.
In col. 13, ln. 38, change “Fig. 49” to - - Fig. 9 - -.5
Appropriate correction is required.
Drawing Objections
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the:
[claim 51] a plurality of electrical connections between the bitline driver chiplet and the NAND wafer, wherein a first electrical connection of the plurality of electrical connections is adjacent to a second electrical connection of the plurality of electrical connections and a pitch between the first electrical connection and the second electrical connection may be approximately 1 micrometer to 10 micrometers; and
[claim 52] an additional plurality of electrical connections between the wordline driver chiplet and the NAND wafer, wherein a third electrical connection of the additional plurality of electrical connections is adjacent to a fourth electrical connection of the additional plurality of electrical connections and a second pitch between the third electrical connection and the fourth electrical connection may be approximately 1 micrometer to 10 micrometers.
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.173(b)(3), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.173(b)(1) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure of an amended drawing should be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be surrounded by brackets and identified as "Canceled," and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.173(b)(3). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Appropriate correction is required.
Claim Interpretation
During examination, claims are given the broadest reasonable interpretation consistent with the specification and limitations in the specification are not read into the claims. See MPEP § 2111, MPEP § 2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP § 2111.01(I). It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP § 2111.01(II). Therefore, unless one of the exceptions applies below, Examiners will interpret the limitations of the pending and examined claims using the broadest reasonable interpretation (“BRI”).
Lexicographic Definitions
A first exception to the prohibition of reading limitations from the specification into the claims is when the Applicant for patent has provided a lexicographic definition for the term. (See MPEP § 2111.01(IV)). After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiner, the Examiner finds that he is unable to locate any lexicographic definitions (either express or implied) with reasonable clarity, deliberateness, and precision. Because the Examiner is unable to locate any lexicographic definitions with reasonable clarity, deliberateness, and precision, the Examiner concludes that Applicant is not his/her own lexicographer. (Id.)
35 U.S.C. § 112 6th Paragraph
A second exception to giving words in the claims their ordinary and customary meaning is when a claimed phrase is interpreted in accordance with 35 U.S.C. § 112 6th paragraph. See MPEP § 2181 et seq.
The Examiner finds that because the Examined Claims do not recite “step,” “means” or a claim term used as a substitution for “means” (i.e. a generic placeholder for “means”), the Examined Claims fail Prong (A) as set forth in MPEP §2181. Because the twenty-six (26) Examined Claims fail Prong (A) as set forth in MPEP §2181 I., the Examiner concludes that all Examined Claims do not invoke 35 U.S.C. §112, 6th paragraph. See also Ex parte Miyazaki, 89 USPQ2d 1207, 1215-16 (B.P.A.I. 2008)(precedential).
Claim Rejections - 35 USC § 251
Oath/Declaration
Claims 1-23 and 51-53 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251 as set forth above. See 37 CFR 1.175.
The nature of the defect(s) in the declaration is set forth in the discussion above in this Office action. (See § VI supra).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-13, 18-23 and 53 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”).
[1] With respect to the limitations of claim 1,
Ramachandra teaches a microelectronic package, comprising: a substrate (Ramachandra; see #20 in Figure 2 and in ¶ [0018]) having first and second opposite surfaces (bottom and top surfaces) each extending in first and second orthogonal directions (into the page and left to right); a NAND wafer (id.; see #24 in Figure 2 and in ¶ [0020], “NAND” in [0029]) having a memory storage array (id.; see #126 in Figure 2 and in ¶ [0029]) therein, the NAND wafer having element contacts (id.; see #66 in Figure 3 and in ¶ [0025]) electrically connected with electrically conductive structure of the substrate (id.; via #42 or #44 in Figure 2 and 3 and in ¶ [AltContent: textbox (Ramachandra Figure 4)]
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[0021-0022]), the NAND wafer being coupled to the first surface of the substrate (id.; via spacer #22 in Figure 2A or without spacer in Figure 2D and in ¶¶ [0018], [0024]); a bitline driver (id.; see #132 and/or #128 in Figure 4 and in ¶ [0030, [0032], [0039]) configured to function as a bitline driver for the NAND wafer, the bitline driver being elongated along the first direction and mounted to a front surface of the NAND wafer (id.; see Figure 4 showing #132 and/or #128 elongated in the first direction); and a wordline driver (id.; see #124 and/or #110 in Figure 4 and in ¶¶ [0030, [0031], [0039]) configured to function as a wordline driver for the NAND wafer, the wordline driver being elongated along the second direction and mounted to the front surface of the NAND wafer (id.; see Figure 4 showing #124 and/or #110 being elongated in the second direction), wherein front surfaces of the bitline driver and the wordline driver are arranged in a single common plane and are entirely contained within an outer periphery of the front surface of the NAND wafer (id.; everything in the plane of and contained within the rectangle #108 in Figure 4, #108 is a memory die representing those in Figure 2, ¶ [0028]).
Ramachandra is clear to teach that the mounting layout of Figure 4 can be configured such that one or more components alone or in combination can be thought of as particular control circuits (id. at ¶ [0039]). However, Ramachandra does not specify that respective control circuits can be mounted on the NAND wafer as chiplets.
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[AltContent: textbox (Hirano Figure 14)]In the same field or endeavor, Hirano teaches mounting memory control circuitry on top of NAND wafers as chiplets (Hirano; see #112 on #120 in Figure 14). Hirano teaches the chips to contain drivers for at least word line layers (id. at ¶ [0048]) in one chip and another chip with drivers to perform tasks such as controlling and allocating memory (id. at ¶ [0051]). Finally, Hirano even teaches that other control structure on the NAND wafer could also be moved between the different dies (id. at ¶ [0049]). Hirano teaches removing the logic circuit from the first die (NAND wafer itself) to free up valuable space for additional memory cells (on the NAND wafer). It also allows for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the drivers of Ramachandra as chiplets as taught by Hirano in order to free up valuable space for additional memory cells (on the NAND wafer) and allow for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]).
Moreover, as set forth above, Ramachandra teaches both the bitline and wordline drivers being mounted to a front surface of the NAND wafer. However, Ramachandra and Hirano is silent to the surfaces of the bitline and wordline drivers being specifically mounted to the NAND wafer by direct bonding at approximately room temperature, without the utilization of adhesives.
However, in the same field of endeavor, Tao teaches vertically mounting memory modules 1400 onto silicon sidewalls 104 utilizing a Direct Bonding Interconnect (DBI®) bonding technique at low temperature (i.e., room temperature). (Tao at ¶¶ [0019], [0055]; see Figure 14). Tao further teaches the direct bonding technique does not utilize any adhesives whatsoever. (Id. at ¶ [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives as described in Tao to the microelectronic package of Ramachandra and Hirano.
A person of ordinary skill in the art would be motivated to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives, since it provides a mechanism to; (1) offer some of the finest pitches of electrical interconnects available; and (2) significantly reduce equipment and process cost for high volume manufacturing. (Id.) In other words, such a modification would provide a microelectronic package which can take advantage of integrating a lowest cost-of-ownership 3D interconnect platform, thereby increasing the overall efficiency of the microelectronic package. (Id.)
[2] With respect to the limitations of claim 2,
both the layouts of Ramachandra (Ramachandra; see Figure 4) and Hirano (id.; see Figure 8) suggest general locations for a bitline driver chiplet and the wordline chiplet. They show bitline structure along a first peripheral edge of the NAND wafer and wordline structure perpendicular to the bitline structure. While neither reference specifically discloses the wordline driver chiplet being disposed along a centerline of the front surface that bisects the first peripheral edge, such a placement or orientation would have been obvious to one of ordinary skill in the art since such a layout appears to be no more than a rearrangement of parts which would have been obvious to one of ordinary skill in the art based on a desired wiring layout of which would not have modified the operation of the device (MPEP § 2144 VI).
[3] With respect to the limitations of claim 3,
Tao teaches and/or renders obvious incorporating the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives. (See § XI.A.(1), supra).
[5] With respect to the limitations of claim 5,
Ramachandra teaches a plurality of wire bonds (id.; see #42 in Figure 2 and in ¶ [0021]) extending above the front surface of the NAND wafer, the plurality of wire bonds extending between the element contacts and substrate contacts at the first surface of the substrate (id.; see Figure 2).
[6] With respect to the limitations of claim 6,
Ramachandra teaches the NAND wafer is a first NAND wafer, the microelectronic package further comprising a plurality of NAND wafers including the first NAND wafer, the plurality of NAND wafers being arranged in a vertical stack and coupled to the first surface of the substrate (id.; see Figure 2, stacked memory 24, 26, 28…).
[7] With respect to the limitations of claim 7,
Ramachandra is silent about a device wherein the bitline driver chiplet is configured to function as a bitline driver that is shared by each of the plurality of NAND wafers, and the wordline driver chiplet is configured to function as a wordline driver that is shared by each of the plurality of NAND wafers.
However, Hirano teaches that a device wherein a plurality of NAND wafers can be driven by a driver on or near a first of the plurality of NAND wafers (Hirano; see Figure 15, ¶ [0069]). Hirano discloses a device wherein each NAND wafer is driven by respective sets of drivers or a plurality of NAND wafers are driven by a single set of drivers, thus exemplifying art-recognized equivalent driver structure.
Therefore, because these two driver structures were art-recognized equivalents at the time the invention was made, a person of ordinary skill in the art would have found it obvious to substitute respective sets of bitline and wordline driver chiplets in Ramachandra, Hirano and Tao with a single set of bitline and wordline driver chiplets.
Moreover, the Examiner finds that simple substitution of one known element for another would obtain predictable results. That is, the substitution of one known element (respective sets of bitline and wordline drivers for each NAND wafer) for another (a single set of bitline and wordline driver chiplets controlling multiple NAND wafers) would have been obvious to one of ordinary skill in the art at the time of the invention since the substitution of multiple driver chiplet sets for a single driver chiplet set would have yielded predictable results, namely, driving the NAND wafers in the device while saving space and cost in the device.
[8] With respect to the limitations of claim 8,
Ramachandra teaches comprising a plurality of wire bonds extending above the front surface of the first NAND wafer, the plurality of wire bonds extending between the element contacts of the first NAND wafer and substrate contacts at the first surface of the substrate, the plurality of wire bonds being configured to carry address information and data signals to each of the plurality of NAND wafers (Ramachandra; see #42a-i in Figure 2 allowing connection between a controller and the wafers in ¶¶ [0021]-[0022]).
[9] With respect to the limitations of claim 9,
Tao teaches and/or renders obvious incorporating the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives. (See § XI.A.(1), supra).
[10] With respect to the limitations of claim 10,
Ramachandra teaches the bitline driver is a first bitline driver and the wordline driver is a first wordline driver, the microelectronic package further comprising a plurality of bitline drivers including the first bitline driver and a plurality of wordline drivers including the first wordline driver, each of the bitline drivers and each of the wordline driver being mounted to a corresponding one of the plurality of NAND wafers (Ramachandra; each of the NAND wafers of Figure 2 having the structure of Figure 4 as discussed in ¶ [0028]). Hirano teaches the drivers can be chiplets. The motivation to combine is the same as in claim 1. (See § XI.A.(1), supra).
[11] With respect to the limitations of claim 11,
Ramachandra teaches a plurality of groups of wire bonds, each group of wire bonds extending above the front surface of a respective one of the NAND wafers (Ramachandra; different groups and combinations shown throughout Figure 2), each group of wire bonds extending between element contacts of the respective one of the NAND wafers and substrate contacts at the first surface of the substrate (id.; see Figure 2). Examiner notes that this structure appears met by at least Figure 2B which shows at least two groups (id.; see 44a and 44c, or 44b and 44c). Further, Hirano also teaches different wire bond configurations for conducting signals such as Figure 13 which shows two distinct groups (Hirano; see left and right #192) which extend from different wafers all the way to the substrate. Hirano also teaches wire bonds for signal transfer (id. at ¶ [0059]). It would have been obvious to one of ordinary skill in the art to use any of the layouts or similar layouts to those described in Ramachandra and Hirano since such a layout appears to be no more than a rearrangement of parts which would have been obvious to one of ordinary skill in the art based on a desired wiring layout of which would not have modified the operation of the device (MPEP 2144 VI).
[12] With respect to the limitations of claim 12,
Ramachandra teaches a device wherein plurality of NAND wafers are arranged in a staircase configuration, such that each of the plurality of NAND wafers that is below the first NAND wafer is horizontally offset from the NAND wafer that is directly thereabove in the stack by an offset distance in either the first direction or the second direction (Ramachandra; see Figure 2).
[13] With respect to the limitations of claim 13,
Ramachandra teaches a plurality of groups of wire bonds, each group of wire bonds extending above the front surface of a respective one of the NAND wafers, element contacts of each of the plurality of NAND wafers that is below the first NAND wafer being connected to element contacts of the NAND wafer that is directly thereabove in the stack by one of the groups of wire bonds (id.; see Figure 2).
[18] With respect to the limitations of claim 18,
Ramachandra teaches microelectronic assembly including the microelectronic package of claim 1, further comprising a circuit panel having panel contacts, wherein terminals at the second surface of the substrate (as interpreted in light of the 112 rejection above) are bonded to the panel contacts (id. at ¶ [0019] discussing the substrate electrically connected to a controller).
[19] With respect to the limitations of claim 19,
Ramachandra teaches system comprising a microelectronic package according to claim 1 and one or more other electronic components electrically connected to the microelectronic package (id. at ¶ [0019] for connected to a host device or a controller).
[20] With respect to the limitations of claim 20,
Ramachandra teaches a housing, the microelectronic package and the other electronic components being mounted to the housing (id. at ¶ [0019] for at least a molding compound to serve as a housing).
[21] With respect to the limitations of claim 21,
Ramachandra teaches a microelectronic package, comprising: a substrate (Id.; see #20 in Figure 2 and in ¶ [0018]) having first and second opposite surfaces (bottom and top surfaces) each extending in first and second orthogonal directions (into the page and left to right); a plurality of microelectronic elements (id.; see #24 in Figure 2 and in ¶ [0020], “NAND” in ¶ [0029]) arranged in a vertical stack and coupled to the first surface of the substrate (id.; via spacer #22 in Figure 2A or without spacer in Figure 2D and in ¶¶ [0018], [0024]); the plurality of microelectronic elements each having element contacts (id.; see #66 in Figure 3 and in ¶ [0025]) electrically connected with electrically conductive structure of the substrate (id.; via #42 or #44 in Figures 2 and 3 and in ¶¶ [0021-0022]); and a plurality of drivers (id.; see #132 and/or #128, #124 and/or #110 in Figure 4 and in ¶¶ [0030-0032], [0039]) arranged within the vertical stack and coupled to the plurality of microelectronic elements, the plurality of drivers being alternatingly interleaved with the plurality of microelectronic elements within the vertical stack such that at least one of the plurality of microelectronic elements is directly coupled to multiple drivers, circuitry of each of the plurality of drivers being electrically connected with circuitry of at least one of the plurality of microelectronic elements, wherein front surfaces of each of the drivers of the plurality of drivers are entirely contained within an outer periphery of the front surfaces of each of the plurality of microelectronic elements (id.; everything in the plane of and contained within the rectangle #108 in Figure 4, #108 is a memory die representing those in Figure 2, ¶ [0028]) and at least one driver of the plurality of drivers (id.; see #132 and/or #128, #124 and/or #110 in Figure 4 and in ¶¶ [0030-0032], [0039]) being mounted to at least one microelectronic element of the plurality of microelectronic elements (id.; see #24 in Figure 2 and in ¶ [0020], “NAND” in [0029]).
Ramachandra is clear to teach that the mounting layout of Figure 4 can be configured such that one or more components alone or in combination can be thought of as particular control circuits (id. at ¶ [0039]). However, Ramachandra does not specify that respective control circuits/drivers can be mounted on the NAND wafer (microelectronic elements) as chiplets.
In the same field or endeavor, Hirano teaches mounting memory control circuitry on top of NAND wafers as chiplets. Hirano teaches the chips to contain drivers for at least word line layers (Hirano at ¶ [0048]) in one chip and another chip with drivers to perform tasks such as controlling and allocating memory (id. at ¶ [0051]). Finally, Hirano even teaches that other control structure on the NAND wafer could also be moved between the different dies (id. at ¶ [0049]). Hirano teaches removing the logic circuit from the first die (NAND wafer itself) to free up valuable space for additional memory cells (on the NAND wafer). It also allows for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]). Finally, Hirano even teaches that the chiplets can be interleaved between the NAND wafers (microelectronic elements) in Figure 14.
It would have been obvious to one of ordinary skill in the art to form the drivers of Ramachandra as chiplets as taught by Hirano in order to free up valuable space for additional memory cells (on the NAND wafer) and allow for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]).
Moreover, as set forth above, Ramachandra teaches the drivers being mounted to a front surface of the NAND wafer (microelectronic elements). However, Ramachandra and Hirano is silent to the surfaces of the drivers being specifically mounted to the NAND wafer (microelectronic elements)by direct bonding at approximately room temperature, without the utilization of adhesives.
However, in the same field of endeavor, Tao teaches vertically mounting memory modules 1400 onto silicon sidewalls 104 utilizing a Direct Bonding Interconnect (DBI®) bonding technique at low temperature (i.e., room temperature). (Tao at ¶¶ [0019], [0055]; see Figure 14). Tao further teaches the direct bonding technique does not utilize any adhesives whatsoever. (Id. at ¶ [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives as described in Tao to the microelectronic package of Ramachandra and Hirano.
A person of ordinary skill in the art would be motivated to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives, since it provides a mechanism to; (1) offer some of the finest pitches of electrical interconnects available; and (2) significantly reduce equipment and process cost for high volume manufacturing. (Id.) In other words, such a modification would provide a microelectronic package which can take advantage of integrating a lowest cost-of-ownership 3D interconnect platform, thereby increasing the overall efficiency of the microelectronic package. (Id.)
[22] With respect to the limitations of claim 22,
the rejection of claim 21 addresses how the plurality of drivers in Ramachandra can be replaced with multiple chiplets. (See § XI.A.(16), supra). The motivation to combine is the same as in claim 21. (Id.)
[23] With respect to the limitations of claim 23,
Ramachandra teaches a method of assembling a microelectronic package, the method comprising: providing a substrate (Ramachandra; see #20 in Figure 2 and in ¶ [0018]) having first and second opposite surfaces (bottom and top surfaces) each extending in first and second orthogonal directions (into the page and left to right); coupling a NAND wafer (id.; see #24 in Figure 2 and in ¶ [0020], “NAND” in ¶ [0029]) to the first surface of the substrate, the NAND wafer having a memory storage array (id.; see #126 in Figure 2 and in ¶ [0029]) therein; electrically connecting element contacts (id.; see #66 in Figure 3 and in ¶ [0025]) of the NAND wafer with electrically conductive structure of the substrate (id.; via #42 or #44 in Figures 2 and 3 and in ¶¶ [0021-0022]); mounting a bitline driver (id.; see #132 and/or #128 in Figure 4 and in ¶¶ [0030, [0032], [0039]) to a front surface of the NAND wafer, the bitline driver configured to function as a bitline driver for the NAND wafer, the bitline driver being elongated along the first direction (id.; see Figure 4 showing #132 and/or #128 elongated in the first direction); and mounting a wordline driver (id.; see #124 and/or #110 in Figure 4 and in ¶¶ [0030, [0031], [0039]) to the front surface of the NAND wafer, the wordline driver configured to function as a wordline driver for the NAND wafer, the wordline driver being elongated along the second direction (id.; see Figure 4 showing #124 and/or #110 being elongated in the second direction), wherein front surfaces of the bitline driver and the wordline driver are arranged in a single common plane and are entirely contained within an outer periphery of the front surface of the NAND wafer (id.; everything in the plane of and contained within the rectangle #108 in Figure 4, #108 is a memory die representing those in Figure 2, ¶ [0028]).
Ramachandra is clear to teach that the mounting layout of Figure 4 can be configured such that one or more components alone or in combination can be thought of as particular control circuits (id. at ¶ [0039]). However, Ramachandra does not specify that respective control circuits can be mounted on the NAND wafer as chiplets.
In the same field or endeavor, Hirano teaches mounting memory control circuitry on top of NAND wafers as chiplets. Hirano teaches the chips to contain drivers for at least word line layers (Hirano at ¶ [0048]) in one chip and another chip with drivers to perform tasks such as controlling and allocating memory (id. at ¶ [0051]). Finally, Hirano even teaches that other control structure on the NAND wafer could also be moved between the different dies (id. at ¶ [0049]). Hirano teaches removing the logic circuit from the first die (NAND wafer itself) to free up valuable space for additional memory cells (on the NAND wafer). It also allows for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]).
It would have been obvious to one of ordinary skill in the art to form the drivers of Ramachandra as chiplets as taught by Hirano in order to free up valuable space for additional memory cells (on the NAND wafer) and allow for customized and optimized fabrication processes for the separate wafers (id. at ¶¶ [0032]-[0033]).
Moreover, as set forth above, Ramachandra teaches both the bitline and wordline drivers being mounted to a front surface of the NAND wafer. However, Ramachandra and Hirano is silent to the surfaces of the bitline and wordline drivers being specifically mounted to the NAND wafer by direct bonding at approximately room temperature, without the utilization of adhesives.
However, in the same field of endeavor, Tao teaches vertically mounting memory modules 1400 onto silicon sidewalls 104 utilizing a Direct Bonding Interconnect (DBI®) bonding technique at low temperature (i.e., room temperature). (Tao at ¶¶ [0019], [0055]; see Figure 14). Tao further teaches the direct bonding technique does not utilize any adhesives whatsoever. (Id. at ¶ [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives as described in Tao to the microelectronic package of Ramachandra and Hirano.
A person of ordinary skill in the art would be motivated to incorporate the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives, since it provides a mechanism to; (1) offer some of the finest pitches of electrical interconnects available; and (2) significantly reduce equipment and process cost for high volume manufacturing. (Id.) In other words, such a modification would provide a microelectronic package which can take advantage of integrating a lowest cost-of-ownership 3D interconnect platform, thereby increasing the overall efficiency of the microelectronic package. (Id.)
[53] With respect to the limitations of claim 53,
Tao teaches and/or renders obvious incorporating the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives. (See § XI.A.(18), supra).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Shinohara et al. (U.S. Publication No. 2009/0200680) (“Shinohara”).
[4] With respect to the limitations of claim 4,
Ramachandra, Hirano and Tao teaches and/or renders obvious bitline driver chiplet is a first bitline driver chiplet and the wordline driver chiplet is a first wordline driver chiplet, as well as their orientation while being mounted to the front surface of the NAND wafer (See § XI.A.(1), rejection of claim 1 above). Ramachandra, Hirano and Tao is silent about the microelectronic package further comprising a plurality of bitline driver chiplets including the first bitline driver chiplet and a plurality of wordline driver chiplets including the first wordline driver chiplet, each of the bitline driver chiplets being spaced apart from one another, and each of the wordline driver chiplets being spaced apart from one another.
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[AltContent: textbox (Shinohara Figure 40)]However, in the same field or endeavor, Shinohara teaches the use of multiple control chiplets mounted on top of the memory wafer (Shinohara; see #3 in Figures 39 and 40, note also multiple interposers #4). Shinohara teaches the use of extra chiplets spaced from one another in order to prevent the decrease in access rate between memory chips and the controller chip (id. at ¶ [0194]). Shinohara recognizes a problem with access rate when using multiple memory chips and solves it by multiplying the driver chips.
Thus, it would have been obvious to one of ordinary skill in the art to utilize a plurality of bitline and wordline driver chiplets in the device of Ramachandra, Hirano and Tao as taught by Shinohara in order to maintain access rate when stacking multiple memory chips together. Finally for any placement or orientation limitation deemed not to be met above, such a placement or orientation would have been obvious to one of ordinary skill in the art since such a layout appears to be no more than a rearrangement of parts which would have been obvious to one of ordinary skill in the art based on a desired wiring layout of which would not have modified the operation of the device (MPEP 2144 VI).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Itoh et al. (U.S. Publication No. 20080122064) (“Itoh”).
[14] With respect to the limitations of claim 14,
Ramachandra teaches a plurality of NAND wafers are arranged in a staircase configuration, such that each of the plurality of NAND wafers that is below the first NAND wafer is horizontally offset from the NAND wafer that is directly thereabove in the stack by a first offset distance in the first direction (Ramachandra; see Figure 2). Ramachandra, Hirano and Tao is silent about the NAND wafers also being offset by a second offset distance in the second direction.
However, in the same field or endeavor, Itoh teaches a similar staircase memory stack wherein the subsequent memory chips are offset by both a first and a second distance (Itoh; see Figure 3). Itoh teaches this structure in order to allow for easier or optimal wiring. In particular, it allows power supply pads to be diagonally placed in order to avoid a reduction in performance due to internal wiring resistance. It also suppresses an increase in ground voltage (id. at ¶ [0067]).
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Itoh Figure 3
It would have been obvious to one of ordinary skill in the art to form the memory chip staircase of Ramachandra, Hirano and Tao to be offset in both a first and second distance as taught by Itoh in order to avoid a reduction in performance due to internal wiring resistance as well as suppress an increase in ground voltage in the staircase.
[15] With respect to the limitations of claim 15,
Ramachandra teaches a plurality of groups of wire bonds, each group of wire bonds extending above the front surface of a respective one of the NAND wafers, element contacts of each of the plurality of NAND wafers that is below the first NAND wafer being connected to element contacts of the NAND wafer that is directly thereabove in the stack by one of the groups of wire bonds, each group of wire bonds having a first subset that extends over a first edge of the respective one of the NAND wafers (Ramachandra; see Figures 2 and 3 showing multiple groups of wire bonds). Itoh teaches a second subset that extends over a second edge of the respective one of the NAND wafers adjacent to the first edge (Itoh; see Figure 3 showing two subsets of wire bonds). The motivation to combine is the same as in claim 14. (See § XI.C.(1), supra).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Kodama et al. (U.S. Publication No. 2008/0157393) (“Kodama”).
[16] With respect to the limitations of claim 16,
Ramachandra and Hirano teaches NAND wafers. However, Ramachandra, Hirano and Tao is silent about the plurality of NAND wafers being arranged in an alternating orthogonal configuration, such that long sides of each of the plurality of NAND wafers that is below the first NAND wafer are rotated 90 degrees relative to long sides of the NAND wafer that is directly thereabove in the stack.
However, in the same field or endeavor, Kodama teaches the plurality of NAND wafers are arranged in an alternating orthogonal configuration, such that long sides of each of the plurality of NAND wafers that is below the first NAND wafer are rotated 90 degrees relative to long sides of the NAND wafer that is directly thereabove in the stack (Kodama; see Figures 23-25; and ¶¶ [0179]-[0205]). Kodama teaches this configuration in order to secure space in the [AltContent: textbox (Kodama Figure 23)]
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direction of thickness for wire bonding of the underlying semiconductor (id. at ¶ [0202]) and simplify the leading of board interconnections (id. at ¶ [0204]). It would have been obvious to one of ordinary skill in the art to stack the NAND wafers of Ramachandra in view of Hirano in a manner taught by Kodama in order to secure space in the direction of thickness for wire bonding of the underlying semiconductor (id. at ¶ [0202]) and simplify the leading of board interconnections (id. at ¶ [0204]).
[17] With respect to the limitations of claim 17,
Kodama teaches a plurality of groups of wire bonds, each group of wire bonds extending above the front surface of a respective one of the NAND wafers, each group of wire bonds extending between element contacts of the respective one of the NAND wafers and substrate contacts at the first surface of the substrate, each group of wire bonds having a first subset that extends over a first short edge of the respective one of the NAND wafers and a second subset that extends over a second edge of the respective one of the NAND wafers opposite from the first edge (Kodama; see Figures 23-25 showing wire bonds coming off both short sides of each wafer). The motivation to combine is the same as in claim 16. (See § XI.D.(1), supra).
Claims 51 and 52 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S. Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Leedy (U.S. Publication No. 20140043883).
[51] With respect to the limitations of claim 51,
Ramachandra teaches the bitline driver (Ramachandra; see #132 and/or #128 in Figure 4 and in ¶ [0030, [0032], [0039]) being configured to function as a bitline driver for the NAND wafer and the bitline driver being mounted to a front surface of the NAND wafer (id.; see Figure 4 showing #132 and/or #128 mounted on top of the NAND wafer). In addition, as set forth above, Tao teaches and/or renders obvious incorporating the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives. (See § XI.A.(1), supra). From this perspective, the Examiner finds that the bitline driver (id.; see #132 and/or #128 in Figure 4 and in ¶¶ [0030, [0032], [0039]) mounted by direct bonding, as described by Tao, would have a plurality of electrical connection between the respective bitline drive and NAND wafer providing the required management/communication of data (id.) However, Ramachandra, Hirano and Tao is silent about the plurality of electrical connections specifically comprising a first electrical connection adjacent a second electrical connection in which a pitch between the first electrical connection and the second electrical connection may be approximately 1 micrometer to 10 micrometers.
However, in the same field or endeavor, Leedy teaches a memory structure being a stack of integrated circuit layers with a fine-grain vertical interconnect between them. (Leedy at ¶¶ [0024]-[0027]; see Figures 1A, 2A, 4). Specifically, the Examiner finds that Leedy teaches the pitch of the fine-grain vertical interconnect having first and second electrical connections adjacent one another typically being less than 10 microns, but not limited to a pitch of less than 2 microns. (Id. at ¶¶ [0024]-[0027], [0030], [0032]-[0034], [0049], [0052]-[0053; see Figures 1A, 2A, 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the plurality of electrical connections to specifically have a first electrical connection adjacent a second electrical connection in which a pitch between the first electrical connection and the second electrical connection may be approximately 1 micrometer to 10 micrometers as described in Leedy to the microelectronic package of Ramachandra, Hirano and Tao.
A person of ordinary skill in the art would be motivated to incorporate the plurality of electrical connections to specifically have a first electrical connection adjacent a second electrical connection in which a pitch between the first electrical connection and the second electrical connection may be approximately 1 micrometer to 10 micrometers, since it provides a mechanism to provide: (1) effective bonding of the various circuit layers together (id. at ¶ [0024]); and (2) reduce the conventional footprint and reduces cost of the memory cell (id. at Abstract; ¶¶ [0035]-[0037]). (Id.) In other words, such a modification would provide a microelectronic package which can take advantage of a Three-Dimensional Structure (3DS), thereby increasing the overall efficiency of the microelectronic package. (Id.)
[52] With respect to the limitations of claim 52,
Ramachandra teaches the wordline driver (Ramachandra; see #124 and/or #110 in Figure 4 and in ¶ [0030, [0031], [0039]) being configured to function as a wordline driver for the NAND wafer and the wordline driver being elongated along the second direction and mounted to the front surface of the NAND wafer (id.; see Figure 4 showing #124 and/or #110 mounted on top of the NAND wafer). In addition, as set forth above, Tao teaches and/or renders obvious incorporating the utilization of direct bonding techniques, at approximately room temperature, to effectively mount separate module faces to wafers, without the utilization of adhesives. (See § XI.A.(1), supra). From this perspective, the Examiner finds that the wordline driver (id.; see #124 and/or #110 in Figure 4 and in ¶¶ [0030, [0031], [0039]) would have a plurality of electrical connection between the respective wordline drive and NAND wafer providing the required management/communication of data (id.) However, Ramachandra, Hirano and Tao is silent about the plurality of electrical connections specifically comprising a third electrical connection adjacent a fourth electrical connection in which a pitch between the third electrical connection and the fourth electrical connection may be approximately 1 micrometer to 10 micrometers.
However, in the same field or endeavor, Leedy teaches a memory structure being a stack of integrated circuit layers with a fine-grain vertical interconnect between them. (Leedy at ¶¶ [0024]-[0027]; see Figures 1A, 2A, 4). Specifically, the Examiner finds that Leedy teaches the pitch of the fine-grain vertical interconnect having third and fourth electrical connections adjacent one another typically being less than 10 microns, but not limited to a pitch of less than 2 microns. (Id. at ¶¶ [0024]-[0027], [0030], [0032]-[0034], [0049], [0052]-[0053; see Figures 1A, 2A, 4). The motivation to combine is the same as in claim 51. (See § XI.E.(1), supra).
Response to Arguments
Oath/Declaration
As asserted above, the Examiner finds that the June 2025 Declaration is deemed defective because the error which is relied upon to support the reissue application is not an error upon which the instant ‘572 Reissue Application can be based. (See § VI, supra))
Thus, the objection and rejection based upon a defective reissue declaration under 35 U.S.C. 251 is still present and maintained in the instant ‘572 Reissue Application. (See §§ VI, IX.A, supra).
Specification Objection(s)
With respect to the Specification Objections provided in the Jan 2025 Non-Final Office Action, the June 2025 Applicant Response, including the June 2025 Spec Amendment and “Remarks,” has been fully considered and is not deemed persuasive. (See June 2025 Applicant Response at 13).
Specifically, the June 2025 Spec Amendment indicates that the last substitute paragraph as beginning at “column 13, line 37” instead of -- column 13, line 27 --. (See § VII, supra; emphasis at footnote 5).
Thus, the Examiner finds that there are outstanding Specification Objections issues still present. (Id.)
Drawings Objection(s)
With respect to the Drawings Objections, the June 2025 Applicant Response, including the June 2025 Claim Amendment and “Remarks,” has been fully considered and is persuasive. (See June 2025 Applicant Response at 13). Thus, the objection to Drawings provided in the Jan 2025 Non-Final Office Action are withdrawn, accordingly.
However, based upon the June 2025 Claim Amendment, the Examiner finds that the instant ‘197 Reissue Application still has outstanding Drawings Objection issues present. (See § VIII, supra).
35 U.S.C. § 112, Second Paragraph, Rejections
With respect to the 35 U.S.C. § 112 (b) rejections, the June 2025 Applicant Response, including the June 2025 Claim Amendment and “Remarks,” has been fully considered and is persuasive. (See June 2025 Applicant Response at 13. Thus, the 35 U.S.C. 35 U.S.C. § 112 (b) rejections provided in the Jan 2025 Non-Final Office Action are moot, overcome and withdrawn.
35 U.S.C. § 251 Original Patent Requirement
With respect to the 35 U.S.C. § 251 original patent requirement rejection, the June 2025 Applicant Response, including the June 2025 Claim Amendment and “Remarks,” has been fully considered and is persuasive. (See June 2025 Applicant Response at 13). Thus, the 35 U.S.C. 35 U.S.C. § 251 original patent requirement rejection provided in the Jan 2025 Non-Final Office Action is moot, overcome and withdrawn.
35 U.S.C. § 103 Rejections
Applicant’s arguments, with respect to: (1) the rejection(s) of claim(s) 1-2, 5-8, 10-13, 18-29, 34-37, 39-44 and 49 under 35 U.S.C. 103 as being unpatentable over Ramachandra and Hirano; and (2) Huneke (U.S. Patent 8,399,974) not satisfying the new claim requirements, have been fully considered and persuasive. (June 2024 Applicant Response at 13-14). Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”). In this regard, the Examiner finds that Tao teaches an apparatus comprising vertically mounting memory modules onto silicon sidewalls utilizing a Direct Bonding Interconnect (DBI®) bonding technique at low temperature (i.e., room temperature). (See §§ XI.A.(1), (16), (18), supra).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Because this application is now final, Applicant are reminded of the USPTO’s after final practice as discussed in MPEP §714.12 and §714.13 and that entry of amendments after final is not a matter of right. “The refusal of an examiner to enter an amendment after final rejection of claims is a matter of discretion.” In re Berger, 279 F.3d 975, 984, 61 USPQ2d 1523, 1529 (Fed. Cir. 2002) (citations omitted). Furthermore, suggestions or examples of claim language provided by the Examiner are just that—suggestions or examples—and do not constitute a formal requirement mandated by the Examiner. Unless stated otherwise by an express indication that a claim is “allowed,” exemplary claim language provided by the Examiner to overcome a particular rejection or to change claim interpretation has not been addressed with respect to other aspects of patentability (e.g. §101 patentable subject matter, §112(a) written description and enablement, §112(b) indefiniteness, and §102 and §103, prior art). Therefore, any claim amendment submitted under 37 C.F.R. §1.116 that incorporates an Examiner suggestion or example or simply changes claim interpretation will nevertheless require further consideration and/or search and a patentability determination as noted above.
Applicant is respectfully reminded that any suggestions or examples of claim language provided by the Examiner are just that—suggestions or examples—and do not constitute a formal requirement mandated by the Examiner. To be especially clear, any suggestion or example provided in this Office Action (or in any future office action) does not constitute a formal requirement mandated by the Examiner.
Should Applicant decide to amend the claims, Applicant is also reminded that—like always—no new matter is allowed. The Examiner therefore leaves it up to Applicant to choose the precise claim language of the amendment in order to ensure that the amended language complies with 35 U.S.C. § 112 1st paragraph.
Independent of the requirements under 35 U.S.C. § 112(a), Applicant is also respectfully reminded that when amending a particular claim, all claim terms must have clear support or antecedent basis in the specification. See 37 C.F.R. § 1.75(d)(1) and MPEP § 608.01(o). Should Applicant amend the claims such that the claim language no longer has clear support or antecedent basis in the specification, an objection to the specification may result. Therefore, in these situations where the amended claim language does not have clear support or antecedent basis in the specification and to prevent a subsequent ‘Objection to the Specification’ in the next office action, Applicant is encouraged to either (1) re-evaluate the amendment and change the claim language so the claims do have clear support or antecedent basis or, (2) amend the specification to ensure that the claim language does have clear support or antecedent basis. See again MPEP § 608.01(o) (¶3). Should Applicant choose to amend the specification, Applicant is reminded that—like always—no new matter in the specification is allowed. See 35 U.S.C. § 132(a). If Applicant has any questions on this matter, Applicant is encouraged to contact the Examiner via the telephone number listed below.
Applicant is reminded of the obligation to apprise the Office of any prior or concurrent proceedings in which the ‘283 Patent is or was involved, such as interferences or trials before the Patent Trial and Appeal Board, other reissues, reexaminations, or litigations and the results of such proceedings.
Applicant is further reminded of the continuing obligation under 37 C.F.R. §1.56 to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN J RALIS whose telephone number is (571)272-6227. The examiner can normally be reached Monday-Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on 571-272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-9900.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Stephen J. Ralis/Primary Examiner, Art Unit 3992 Conferees:
/Ovidio Escalante/Primary Examiner, Art Unit 3992 /H.B.P/Hetul B. PatelSupervisory Patent Examiner, Art Unit 3992 SJR
07/30/2025
1 The Examiner notes that all of the Rejected Claims stood rejected under 251 and 103; and claims 18, 21 and 29 stood rejected under 112(b).
2 Claims 1, 17, 18 and 21-23 amended in the instant June 2025 Claim Amendment.
3 Claims 51-53 added in the instant June 2025 Claim Amendment.
4 Claims 24-50 canceled in the instant June 2025 Claim Amendment.
5 The Examiner finds that the June 2025 Spec Amendment is not entered in lieu of the last substitute paragraph being indicated as beginning at “column 13, line 37” instead of -- column 13, line 27 --.
Prosecution Insights