Prosecution Insights
Prosecution Insights
2 pending office actions • 1 art units • 2 examiners • 0 of 2 (0%) have an AI response strategy ready • 3 patents granted in the last 365 days
Adeia Semiconductor Inc. has 2 pending office actions assigned to 2 distinct examiners. These actions are located within 1 distinct art unit, indicating that the office has grouped the company's current filings under a single technical classification. This grouping can lead to more consistent technical feedback across the portfolio.
ASSOUMAN, HERVE-LOUIS Y is the busiest examiner with 1 busiest examiner pending action. This examiner is responsible for a portion of the 2 pending office actions. Because the actions are split between different examiners, the company must adapt to different individual examination styles even within the same art unit.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| Double-patenting only | 1 (50%) |
| Multi-statute (no §101) | 1 (50%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| ASSOUMAN, HERVE-LOUIS Y | 1 | 91.4% | +4.1% |
| RALIS, STEPHEN J | 1 | 33.5% | +42.3% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18783034 | HARD IP BLOCKS WITH PHYSICALLY BIDIRECTIONAL PASSAGEWAYS | ASSOUMAN, HERVE-LOUIS Y | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18375197 | ABSTRACTED NAND LOGIC IN STACKS | RALIS, STEPHEN J | 202d overdue |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18375197 | ABSTRACTED NAND LOGIC IN STACKS | RALIS, STEPHEN J | 202d overdue |
| Art Unit | Apps |
|---|---|
| 3992 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18783034 | HARD IP BLOCKS WITH PHYSICALLY BIDIRECTIONAL PASSAGEWAYS | ASSOUMAN, HERVE-LOUIS Y | — | DP | Non-Final OA | — | Pending | Jul 24, 2024 |
| 18375197 | ABSTRACTED NAND LOGIC IN STACKS | RALIS, STEPHEN J | 3992 | §103§112 | Final Rejection | 202d overdue | Pending | Sep 29, 2023 |
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