DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate,” as claimed in independent claims 1, 17, 32, and 48, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Figure 18 of the claimed invention does not show the third pin segment, or the pin of the surface-mount electronic device for that matter, contacting the substrate surface of the aluminum substrate. The contact is to the copper conductive layer.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 17, 32, and 48 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The feature “the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate,” as claimed in amended independent claims 1, 17, 32, and 48, is not disclosed in the specification as originally filed, and thus is new matter. For example, Figure 18 of the claimed invention does not show the third pin segment, or the pin of the surface-mount electronic device for that matter, contacting the substrate surface of the aluminum substrate. The contact is to the copper conductive layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 16 and 32 - 47 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kashino et al. (U.S. Patent Publication No. 2023/0018491).
Regarding claim 1, in Figure 2, Kashino discloses a printed circuit board assembly, the printed circuit board assembly comprising: an aluminum substrate (101, paragraph [0149]) including a substrate surface; an insulating layer (102) on the aluminum substrate; a conductive layer (103) on the insulating layer; and one or more surface-mount electronic devices (201) on the aluminum substrate through the conductive layer and the insulating layer; wherein: the one or more surface-mount electronic devices include at least one converted surface-mount electronic device (201), the one converted surface-mount electronic device being converted from a through-hole electronic device (semiconductor element 201 can be configured as a through-hole electronic device as well); and the one converted surface-mount electronic device is on the aluminum substrate through the conductive layer and the insulating layer (Figure 2);
wherein: the one converted surface-mount electronic device includes one or more pins: each pin of the one or more pins includes a first pin segment, a second pin segment, and a third pin segment, the second pin segment being located between the first pin segment and the third pin segment; the first pin segment extends in a first orientation; the second pin segment extends in a second orientation; the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate (see 112 rejection); wherein: the first orientation is parallel to the substrate surface; and the second orientation is different from the first orientation; wherein the aluminum substrate is made of aluminum (paragraph [0149]).
Regarding claim 2, Kashino discloses wherein: the aluminum substrate includes a first surface and a second surface; the insulating layer includes a third surface and a fourth surface; and the conductive layer includes a fifth surface and a sixth surface; wherein: the second surface of the aluminum substrate is in direct or indirect contact with the third surface of the insulating layer; and the fourth surface of the insulating layer is in direct or indirect contact with the fifth surface of the conductive layer (Figure 2).
Regarding claim 3, Kashino discloses wherein the one converted surface-mount electronic device is on the sixth surface of the conductive layer (Figure 2).
Regarding claim 4, Kashino discloses that the printed circuit board assembly of claim 1 does not include any through-hole electronic device (Figure 2).
Regarding claim 5, Kashino discloses one or more through-hole electronic devices (Figure 2).
Regarding claim 6, Kashino discloses wherein the one converted surface-mount electronic device is not a power electronic device (Figure 2).
Regarding claim 7, Kashino discloses wherein: the one converted surface-mount electronic device is a power electronic device (paragraph [0020]); and the power electronic device is not in direct contact with any heat sink (Figure 2).
Regarding claim 8, Kashino discloses that the printed circuit board assembly of claim 1 does not include any heat sink (Figure 2).
Regarding claim 9, Kashino discloses a heat sink (207; Figure 2).
Regarding claim 10, Kashino discloses wherein the heat sink is not in direct contact with any of the one or more surface-mount electronic devices (Figure 2).
Regarding claim 11, Kashino discloses wherein: the one converted surface-mount electronic device is a power electronic device; and the power electronic device is in contact with the heat sink (Figure 2).
Regarding claim 12, Kashino discloses wherein: the aluminum substrate includes a first surface and a second surface; the insulating layer includes a third surface and a fourth surface; and the conductive layer includes a fifth surface and a sixth surface; wherein: the second surface of the aluminum substrate is in direct or indirect contact with the third surface of the insulating layer; and-D-the fourth surface of the insulating layer is in direct or indirect contact with the fifth surface of the conductive layer (Figure 2).
Regarding claim 13, Kashino discloses wherein the heat sink is attached to the second surface of the aluminum substrate through the conductive layer and the insulating layer (Figure 2).
Regarding claim 14, Kashino discloses wherein the heat sink is attached to the first surface of the aluminum substrate (Figure 2).
Regarding claim 15, Kashino discloses wherein the one converted surface-mount electronic device is an insulated-gate bipolar transistor that has been converted from being a through-hole electronic device (Figure 2).
Regarding claim 16, Kashino discloses wherein the one converted surface-mount electronic device is an inductive winding that has been converted from being a through-hole electronic device (Figure 2).
Regarding claim 32, in Figure 2, Kashino discloses an induction cooker comprising: a printed circuit board assembly (200); wherein the printed circuit board assembly includes: an aluminum substrate (101; paragraph [0149]) including a substrate surface; an insulating layer (102) on the aluminum substrate; a conductive layer (103) on the insulating layer; and one or more surface-mount electronic devices (201) on the aluminum substrate through the conductive layer and the insulating layer; wherein: the one or more surface-mount electronic devices include at least one converted surface-mount electronic device (201), the one converted surface-mount electronic device being converted from a through-hole electronic device (semiconductor element 201 can be configured as a through-hole electronic device as well); and the one converted surface-mount electronic device is on the aluminum substrate through the conductive layer and the insulating layer (Figure 2); wherein: the one converted surface-mount electronic device includes one or more pins: each pin of the one or more pins includes a first pin segment, a second pin segment, and a third pin segment, the second pin segment being located between the first pin segment and the third pin segment; the first pin segment extends in a first orientation; the second pin segment extends in a second orientation; the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate (see 112 rejection); wherein: the first orientation is parallel to the substrate surface; and the second orientation is different from the first orientation; wherein the aluminum substrate is made of aluminum (paragraph [0149]).
Regarding claim 33, Kashino discloses wherein: the aluminum substrate includes a first surface and a second surface; the insulating layer includes a third surface and a fourth surface; and the conductive layer includes a fifth surface and a sixth surface; wherein: the second surface of the aluminum substrate is in direct or indirect contact with the third surface of the insulating layer; and the fourth surface of the insulating layer is in direct or indirect contact with the fifth surface of the conductive layer (Figure 2).
Regarding claim 34, Kashino discloses wherein the one converted surface-mount electronic device is on the sixth surface of the conductive layer (Figure 2).
Regarding claim 35, Kashino discloses wherein the printed circuit board assembly does not include any through-hole electronic device (Figure 2).
Regarding claim 36, Kashino discloses wherein the printed circuit board assembly further includes one or more through-hole electronic devices (Figure 2).
Regarding claim 37, Kashino discloses wherein the one converted surface-mount electronic device is not a power electronic device (Figure 2).
Regarding claim 38, Kashino discloses wherein: the one converted surface-mount electronic device is a power electronic device; and the power electronic device is not in direct contact with any heat sink (Figure 2).
Regarding claim 39, Kashino discloses wherein the printed circuit board assembly does not include any heat sink (Figure 2).
Regarding claim 40, Kashino discloses wherein the printed circuit board assembly further includes a heat sink (Figure 2).
Regarding claim 41, Kashino discloses wherein the heat sink is not in direct contact with any of the one or more surface-mount electronic devices (Figure 2).
Regarding claim 42, Kashino discloses wherein: the one converted surface-mount electronic device is a power electronic device; and the power electronic device is in contact with the heat sink (Figure 2).
Regarding claim 43, Kashino discloses wherein: the aluminum substrate includes a first surface and a second surface; the insulating layer includes a third surface and a fourth surface; and the conductive layer includes a fifth surface and a sixth surface; wherein: the second surface of the aluminum substrate is in direct or indirect contact with the third surface of the insulating layer; and the fourth surface of the insulating layer is in direct or indirect contact with the fifth surface of the conductive layer (Figure 2).
Regarding claim 44, Kashino discloses wherein the heat sink is attached to the second surface of the aluminum substrate through the conductive layer and the insulating layer (Figure 2).
Regarding claim 45, Kashino discloses wherein the heat sink is attached to the first surface of the aluminum substrate (Figure 2).
Regarding claim 46, Kashino discloses wherein the one converted surface-mount electronic device is an insulated-gate bipolar transistor that has been converted from being a through-hole electronic device (Figure 2).
Regarding claim 47, Kashino discloses wherein the one converted surface-mount electronic device is an inductive winding that has been converted from being a through-hole electronic device (Figure 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 17 – 31 and 48 – 60 are rejected under 35 U.S.C. 103 as being unpatentable over Kashino.
Regarding claim 17, in Figure 2, Kashino discloses a printed circuit board assembly of a home appliance, the printed circuit board assembly comprising: an aluminum substrate (101; paragraph [0149]) including a first substrate surface and a second substrate surface, the first substrate surface and the second substrate surface being opposite to each other; one or more converted surface-mount electronic devices (201) on the first substrate surface of the aluminum substrate, the one or more converted surface-mount electronic devices being converted from one or more first through-hole electronic devices (semiconductor element 201 can be configured as a through-hole electronic device as well); and one or more additional surface-mount electronic devices on the first substrate surface of the aluminum substrate; wherein: the one or more converted surface-mount electronic devices include one or more pins: each pin of the one or more pins includes a first pin segment, a second pin segment, and a third pin segment, the second pin segment being located between the first pin segment and the third pin segment; the first pin segment extends in a first orientation; the second pin segment extends in a second orientation; the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate (see 112 rejection); wherein: the first orientation is parallel to the first substrate surface; and the second orientation is different from the first orientation; wherein the aluminum substrate is made of aluminum (paragraph [0149]). Kashino does not specifically disclose one or more additional surface-mount electronic devices on the first substrate surface of the aluminum substrate. However, providing multiple electronic devices, such as surface-mount electronic devices, on the substrate of a printed circuit board is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill.
Regarding claim 18, Kashino discloses that the printed circuit board assembly of claim 17 does not include any through-hole electronic device (Figure 2).
Regarding claim 19, Kashino discloses one or more second through-hole electronic devices (Figure 2).
Regarding claim 20, Kashino discloses wherein: the one or more converted surface-mount electronic devices include one or more power electronic devices; and the one or more power electronic devices are not in direct contact with any heat sink (Figure 2).
Regarding claim 21, Kashino discloses that the printed circuit board assembly of claim 17 does not include any heat sink (Figure 2).
Regarding claim 22, Kashino discloses one or more heat sinks (Figure 2).
Regarding claim 23, Kashino discloses wherein the one or more heat sinks are not in direct contact with any of the one or more converted surface-mount electronic devices and are not in direct contact with any of the one or more additional surface-mount electronic devices (Figure 2).
Regarding claim 24, Kashino discloses wherein the one or more heat sinks are located on the first substrate surface of the aluminum substrate (Figure 2).
Regarding claim 25, Kashino discloses wherein the one or more heat sinks are attached to the second substrate surface of the aluminum substrate (Figure 2).
Regarding claim 26, Kashino discloses wherein the one or more heat sinks are in direct contact with the second substrate surface of the aluminum substrate (Figure 2).
Regarding claim 27, Kashino discloses wherein: the one or more converted surface-mount electronic devices include one or more power electronic devices; and one or more devices of the one or more power electronic devices are in contact with one or more heat sinks (Figure 2).
Regarding claim 28, Kashino discloses wherein the one or more converted surface-mount electronic devices include an insulated-gate bipolar transistor that has been converted from being a through-hole electronic device to being a converted surface-mount electronic device (Figure 2).
Regarding claim 29, Kashino discloses wherein the one or more converted surface-mount electronic devices include an inductive winding that has been converted from being a through-hole electronic device to being a converted surface-mount electronic device (Figure 2).
Regarding claim 30, Kashino discloses wherein the home appliance is an induction cooker (Figure 2).
Regarding claim 31, Kashino discloses wherein the home appliance is an electric water heater (Figure 2).
Regarding claim 48, in Figure 2, Kashino discloses an induction cooker comprising: a printed circuit board assembly (200); wherein the printed circuit board assembly includes: an aluminum substrate (101; paragraph [0149]) including a first substrate surface and a second substrate surface, the first substrate surface and the second substrate surface being opposite to each other; one or more converted surface-mount electronic devices (201) on the first substrate surface of the aluminum substrate, the one or more converted surface-mount electronic devices being converted from one or more first through-hole electronic devices (semiconductor element 201 can be configured as a through-hole electronic device as well); and one or more additional surface-mount electronic devices on the first substrate surface of the aluminum substrate; wherein: the one or more converted surface-mount electronic devices include one or more pins: each pin of the one or more pins includes a first pin segment, a second pin segment, and a third pin segment, the second pin segment being located between the first pin segment and the third pin segment; the first pin segment extends in a first orientation; the second pin segment extends in a second orientation; the third pin segment extends in the first orientation and is contact with the substrate surface of the aluminum substrate (see 112 rejection); wherein: the first orientation is parallel to the first substrate surface; and the second orientation is different from the first orientation; wherein the aluminum substrate is made of aluminum (paragraph [0149]). Kashino does not specifically disclose one or more additional surface-mount electronic devices on the first substrate surface of the aluminum substrate. However, providing multiple electronic devices, such as surface-mount electronic devices, on the substrate of a printed circuit board is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill.
Regarding claim 49, Kashino discloses wherein the printed circuit board assembly does not include any through-hole electronic device (Figure 2).
Regarding claim 50, Kashino discloses wherein the printed circuit board assembly further includes one or more second through-hole electronic devices (Figure 2).
Regarding claim 51, Kashino discloses wherein: the one or more converted surface-mount electronic devices include one or more power electronic devices; and the one or more power electronic devices are not in direct contact with any heat sink (Figure 2).
Regarding claim 52, Kashino discloses wherein the printed circuit board assembly does not include any heat sink (Figure 2).
Regarding claim 53, Kashino discloses wherein the printed circuit board assembly further includes one or more heat sinks (Figure 2).
Regarding claim 54, Kashino discloses wherein the one or more heat sinks are not in direct contact with any of the one or more converted surface-mount electronic devices and are not in direct contact with any of the one or more additional surface-mount electronic devices (Figure 2).
Regarding claim 55, Kashino discloses wherein the one or more heat sinks are located on the first substrate surface of the aluminum substrate (Figure 2).
Regarding claim 56, Kashino discloses wherein the one or more heat sinks are attached to the second substrate surface of the aluminum substrate (Figure 2).
Regarding claim 57, Kashino discloses wherein the one or more heat sinks are in direct contact with the second substrate surface of the aluminum substrate (Figure 2).
Regarding claim 58, Kashino discloses wherein: the one or more converted surface-mount electronic devices include one or more power electronic devices; and one or more devices of the one or more power electronic devices are in contact with one or more heat sinks (Figure 2).
Regarding claim 59, Kashino discloses wherein the one or more converted surface-mount electronic devices include an insulated-gate bipolar transistor that has been converted from being a through-hole electronic device to being a converted surface- mount electronic device (Figure 2).
Regarding claim 60, Kashino discloses wherein the one or more converted surface-mount electronic devices include an inductive winding that has been converted from being a through-hole electronic device to being a converted surface-mount electronic device (Figure 2).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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