DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
As of the amendment filed December 09, 2025, new claim 16 has been added which depends indirectly on independent claim 1. Therefore, claims 1-16 remain pending, with claim 1 being independent. All new matter was originally described in the specification, drawings, or claims as filed; therefore, no new matter has been added.
Election/Restrictions
Applicant's election with traverse of “Species B (Claims 1-11 and 15-16)” in the reply filed on December 09, 2025, is acknowledged. Applicant’s arguments are persuasive and restriction is hereby withdrawn. Claims 1-16 remain pending, with claim 1 being independent
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being obvious over US 2010/0133670 A1; Liu et al.; 06/2010; (“670”) in view of US 10,204,845 B2; Otremba et al.; 02/2019; (“845”) in further view of US 2020/0273838 A1; Williams et al.; 08/2020; (“838”).
Regarding Claim 1. 670 teaches in Figs. 9A and 9B about a semiconductor package (Fig. 9B, item 1000) comprising:
a lead frame (Fig. 9A, item 1002) comprising
a top plate (Fig. 9A, 1028) comprising:
a thicker region (Fig. 9A, thicker region of item 1028, not including the ledge items 1028k); and
a thinner region (Fig. 9A, ledge items 1028k of item 1028);
wherein a top surface of the thicker region of the top plate of the lead frame is exposed from the top surface of the molding encapsulation (Fig. 9B, top surface of thicker region of item 1028 is exposed from top surface of molding encapsulation item 1030);
670 does not teach about a semiconductor package comprising:
a lead frame comprising
a plurality of drain pads;
a plurality of slanted sections, each slanted section of the plurality of slanted sections connecting a respective drain pad of the plurality of drain pads to the top plate;
a gate pad; and
a plurality of source pads;
a chip attached to the lead frame, the chip comprising:
a source electrode and a gate electrode on a top surface of the chip; and
a drain electrode on a bottom surface of the chip;
a molding encapsulation enclosing the chip and a majority portion of the lead frame, the molding encapsulation comprises:
a top surface;
a first side surface;
a second side surface opposite the first side surface; and
a bottom surface;
wherein a respective side surface of each drain pad of the plurality of drain pads is exposed from the first side surface of the molding encapsulation;
wherein a respective bottom surface of each drain pad of the plurality of drain pads is exposed from the bottom surface of the molding encapsulation;
wherein a side surface of the gate pad is exposed from the second side surface of the molding encapsulation;
wherein a bottom surface of the gate pad is exposed from the bottom surface of the molding encapsulation;
wherein a respective side surface of each source pad of the plurality of source pads is exposed from the second side surface of the molding encapsulation; and
wherein a respective bottom surface of each source pad of the plurality of source pads is exposed from the bottom surface of the molding encapsulation.
845 teaches in Figs. 2 and 11 about a semiconductor package comprising:
a lead frame (Fig. 2, embodied by items 110,150,160, 250 and 260) comprising
a plurality of drain pads (Fig. 11, items 150D);
a plurality of slanted sections (Fig. 2, slanted sections of items 150 and 160), each slanted section of the plurality of slanted sections connecting a respective drain pad of the plurality of drain pads to the top plate (Fig. 2, each drain slanted section of the plurality of the plurality of slanted sections connects the drain pad items to the top plate item 110);
a gate pad (Fig. 11, item 160G); and
a plurality of source pads (Fig. 11, item 160S);
a chip attached to the lead frame (Fig. 2, item 120), the chip comprising:
a source electrode (Fig. 11, main top surface of item 1120.1) and a gate electrode (Fig. 11, smaller bottom-left squared partition of main top surface of item 1120.1) on a top surface of the chip; and
a drain electrode (Fig. 11, main lower surface of item 1120.1 contacting item 1110.1) on a bottom surface of the chip (Fig. 11, on a bottom surface of item 1120.1);
a molding encapsulation (Fig. 2, item 140) enclosing the chip and a majority portion of the lead frame (Fig. 2, item 140 encloses item 120 and a majority portion of the lead frame), the molding encapsulation comprises:
a top surface (Fig. 2, item 140b);
a first side surface (Fig. 2, right-side of item 140);
a second side surface (Fig. 2, left-side of item 140) opposite the first side surface; and
a bottom surface (Fig. 2, item 140a);
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Fig. 11, annotated by Examiner from Otremba et al., “845”
670 in view of 845 does not teach about a semiconductor package comprising:
wherein a respective side surface of each drain pad of the plurality of drain pads is exposed from the first side surface of the molding encapsulation;
wherein a respective bottom surface of each drain pad of the plurality of drain pads is exposed from the bottom surface of the molding encapsulation;
wherein a side surface of the gate pad is exposed from the second side surface of the molding encapsulation;
wherein a bottom surface of the gate pad is exposed from the bottom surface of the molding encapsulation;
wherein a respective side surface of each source pad of the plurality of source pads is exposed from the second side surface of the molding encapsulation; and
wherein a respective bottom surface of each source pad of the plurality of source pads is exposed from the bottom surface of the molding encapsulation.
838 teaches in Figs. 17D and 6G about a semiconductor package comprising:
wherein a respective side surface of each drain pad of the plurality of drain pads is exposed from the first side surface of the molding encapsulation (Fig 17D, side view for all pad items 277; Fig. 6G, side view for all pad items 76N);
wherein a respective bottom surface of each drain pad of the plurality of drain pads is exposed from the bottom surface of the molding encapsulation (Fig 17D, bottom view for all pad items 277; Fig. 6G, bottom view for all pad items 76N);
wherein a side surface of the gate pad is exposed from the second side surface of the molding encapsulation (Fig 17D, side view for all pad items 277; Fig. 6G, side view for all pad items 76N);
wherein a bottom surface of the gate pad is exposed from the bottom surface of the molding encapsulation (Fig 17D, bottom view for all pad items 277; Fig. 6G, bottom view for all pad items 76N);
wherein a respective side surface of each source pad of the plurality of source pads is exposed from the second side surface of the molding encapsulation (Fig 17D, side view for all pad items 277; Fig. 6G, side view for all pad items 76N); and
wherein a respective bottom surface of each source pad of the plurality of source pads is exposed from the bottom surface of the molding encapsulation (Fig 17D, bottom view for all pad items 277; Fig. 6G, bottom view for all pad items 76N).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the plurality of pads with slanted sections, chip, and molding encapsulation of 845 to arrange the distribution of pads connecting the internal chip within the molding encapsulation to the outside surfaces of the semiconductor package in 670 so “First electrical contact
elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face” as taught by 845 within the Abstract paragraph, Ln. 3-7.
It would have been also obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the Dual-sided Flat No-lead (DFN) packaging type of 838 to arrange the distribution of pads and the pads side and bottom profiles in relation to the encapsulation body in 670 so a “leadless packages can … be manufactured without any exposed die pad” as taught by 838 in [0046], Ln. 1-2.
Regarding Claim 2. 845 teaches in Figs. 8A and 8B about a semiconductor package, wherein
the drain electrode of the chip is attached to a bottom surface of the top plate of the lead frame (“drain (D) electrodes of semiconductor chips 820.1, 820.2, wherein the drain electrodes are bonded to the (single) die pad 810”, Col. 14, Ln. 54-56; wherein, the top plate is embodied by the die pad item 810 in Fig. 8A).
Regarding Claim 3. 845 teaches in Fig. 11 about a semiconductor package, wherein
a gate connection bond wire connecting the gate electrode of the chip to a gate connection plate of the lead frame (not labeled, horizontal connector between item 160G and lower left square area of item 1120.1); and
a plurality bond wires connecting the source electrode of the chip to a source connection plate of the lead frame (not labeled, horizontal connectors between items 160S and main area of item 1120.1).
Regarding Claim 4. 670 teaches in Fig. 9B about a semiconductor package, wherein
a top surface of the thinner region of the top plate of the lead frame is not exposed from the top surface of the molding encapsulation (thinner region of item 1028 is not exposed from trop surface of item 1030).
Regarding Claim 5. 845 teaches in Figs. 2 and 11 about a semiconductor package, wherein the lead frame further comprises:
a source connection plate (Fig. 11, shared source connection plate by a plurality of items 160S, better viewed in above Examiner annotated Fig. 11); and
a plurality of source connection slanted sections (Fig. 2, source slanted section of item 160, and plurality better viewed as items 160S in Fig. 11);
wherein each of the plurality of source connection slanted sections connects a respective source pad of the plurality of source pads to the source connection plate (Fig. 2, each slanted section of an item 160 connects their respective (lower) pad to the (upper) end source connecting plate).
Regarding Claim 6. 838 teaches in [0054] about a semiconductor package, wherein
a respective height between the respective bottom surface of each source pad of the plurality of source pads and a top surface of a DFN type molding encapsulation is <0.08 mm.
838 teaches does not teach about a semiconductor package, wherein
a respective height between the respective bottom surface of each source pad of the plurality of source pads and a bottom surface of the source connection plate is in a range from 0.3 millimeter to 1.0 millimeter.
It would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider different heights between the bottom surface of each of source pad of the plurality of source pads and a bottom surface of the source connection plate, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 7. 845 teaches in Figs. 2 and 11 about a semiconductor package, wherein the lead frame further comprises:
a gate connection plate (Fig. 11, gate connection plate embodied by lower left square area of item 1120.1, better viewed in above Examiner annotated Fig. 11); and
a gate connection slanted section (Fig. 2, gate slanted section of item 160, better viewed as items 160G in Fig. 11);
wherein the gate connection slanted section connects the gate pad to the gate connection plate (Fig. 2, slanted section of an item 160 connects their respective (lower) pad to the (upper) end gate connecting plate).
Regarding Claim 8. 838 teaches in [0054] about a semiconductor package, wherein
a respective height between the respective bottom surface of each drain pad of the plurality of drain pads and a top surface of a DFN type molding encapsulation is <0.08 mm.
838 teaches does not teach about a semiconductor package, wherein
a respective height between the respective bottom surface of each drain pad of the plurality of drain pads and a bottom surface of the top plate of the lead frame is in a range from 0.5 millimeter to 1.2 millimeters.
It would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider different heights between the bottom surface of each of drain pad of the plurality of drain pads and a bottom surface of the top plate of the lead frame, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 9. 838 teaches in [0312] about a semiconductor package, wherein
a thickness of the top plate of the lead frame is in a range from 0.2 millimeter to 0.4 millimeter (“a thickness of 200 μm or 500 μm, used to form the USMP leadframe”, [0312], Ln. 3-4; wherein USMP stands for "universal surface mount package").
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding Claim 10. 670 teaches in Fig. 9A about a semiconductor package, wherein
a thickness of the thinner region of the top plate of the lead frame is about 70% of a thickness of the thicker region of the top plate of the lead frame (thickness of item 1028 below hollow ledge items 1028k is about 70% of a thickness of the thicker region of item 1028).
670 does not teach about a semiconductor package, wherein
a thickness of the thinner region of the top plate of the lead frame is 50% of a thickness of the thicker region of the top plate of the lead frame.
It would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider different thicknesses of the thinner region of the top plate when compared to the thicker region of the top plate, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 11. 670 teaches in Fig. 9A about a semiconductor package, wherein
the thinner region of the top plate of the lead frame is disposed at a peripheral region of the top plate of the lead frame (thinner region of item 1028 below hollow ledge item 1028k is disposed at a peripheral region of item 1028).
Regarding Claim 12. 670 teaches in Fig. 9A about a semiconductor package, wherein
an entirety of the thicker region of the top plate of the lead frame is surrounded by the thinner region of the top plate of the lead frame (item 1028 is surrounded by thinner region of item 1028 below hollow ledge item 1028k).
Regarding Claim 13. 670 teaches in Fig. 9A about a semiconductor package, wherein
a top surface of the thinner region of the top plate of the lead frame is of a hollow rectangle shape (top surface of thinner region of item 1028 is a hollow rectangle shape or rectangular void area).
Regarding Claim 14. 670 teaches in Fig. 9B about a semiconductor package, wherein
a top surface of the thinner region of the top plate of the lead frame directly contacts the molding encapsulation (molding encapsulant item 1030 directly contacts and covers thinner region item 1028k).
Regarding Claim 15. 670 teaches in Fig. 9A about a semiconductor package, wherein
an entirety of the thicker region of the top plate of the lead frame is surrounded by the thinner region of the top plate of the lead frame (item 1028 is surrounded by thinner region of item 1028 below hollow ledge item 1028k).
670 does not teach about a semiconductor package, wherein
an entirety of the thicker region of the top plate of the lead frame is surrounded by the thinner region of the top plate of the lead frame except for a plurality of horizontal regions connected to the plurality of slanted sections of the lead frame.
it would have been also obvious to try by one of ordinary skill in the art, at the time the invention was made, to experiment rearranging thinner and thicker regions of the top plate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 16. 670 teaches in Fig. 9A about a semiconductor package, wherein
a top surface of the thinner region of the top plate of the lead frame is of a hollow rectangle shape (top surface of thinner region of item 1028 is a hollow rectangle shape or rectangular void area).
670 does not teach about a semiconductor package, wherein
a top surface of the thinner region of the top plate of the lead frame is of a hollow rectangle shape except for a plurality of horizontal areas connected to the plurality of slanted sections of the lead frame.
it would have been also obvious to try by one of ordinary skill in the art, at the time the invention was made, to experiment rearranging thinner and thicker regions of the top plate in horizontal areas connected to the plurality of slanted sections of the lead frame, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897