DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 01/05/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election with traverse of Species A, claims 1-5 and 9-20, in the reply filed on 01/05/2026 is acknowledged. The traversal is on the ground that there will be no additional burden for the examiner to examine different Species. The examiner already stated the reason for the restriction requirements in the office action of 12/08/2025. The examiner is required to make a rigorous search strategy and implementation of that search strategy for different Species in several different platforms available to the examination system. As such, it would be a serious search burden for the examiner. Thus, the restriction requirement is FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/03/2023 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193640 A1 (Song) and further in view of US 2024/0030126 A1 (Costa).
Regarding claim 1, Song discloses, a semiconductor package, comprising:
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a first semiconductor structure (300; logic chip; Fig. 1; [0024]) including a first semiconductor layer (301 and 320; Fig. 1; [0024]) having a first active surface (as annotated on Fig. 1) and a first inactive surface (as annotated on Fig. 1) opposing the first active surface (as annotated on Fig. 1), and a first bonding layer (as annotated on Fig. 1) on the first active surface of the first semiconductor layer (301 and 320);
at least one second semiconductor structure (100; integrated voltage regulator chip; Fig. 1; [0019]) on the first semiconductor structure (300), the at least one second semiconductor structure (100) respectively including a second semiconductor layer (101; body) having a second active surface (as annotated on Fig. 1) and a second inactive surface (as annotated on Fig. 1) opposing the second active surface, a second frontside bonding layer (105; lower pad; Fig. 1; [0035]) on the second active surface of the second semiconductor layer (100), and a second backside bonding layer (122; chip pad; Fig. 1; [0035]) on the second inactive surface of the second semiconductor layer (100); and
a third semiconductor structure (200; passive element chip; Fig. 1; [0019]) on the at least one second semiconductor structure (100), the third semiconductor structure (200) including a third semiconductor layer (201) having a third active surface (as annotated on Fig. 1) and a third inactive surface (as annotated on Fig. 1) opposing the third active surface, and a third bonding layer (222) on the third active surface of the third semiconductor layer (200),
wherein: the first bonding layer is bonded to the second frontside bonding layer (105), and
the third bonding layer (222) is bonded to the second backside bonding layer (122).
But Song fails to teach explicitly, a first circuit device is disposed on the first active surface, a second circuit device is disposed on the second active surface, a third circuit device is disposed on the third active surface.
However, in analogous art, Costa discloses, a first circuit device is disposed on the first active surface, a second circuit device is disposed on the second active surface, a third circuit device is disposed on the third active surface (as annotated on Fig. 2; [0079] – [0081]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Song and Costa before him/her, to modify the teachings of a semiconductor package as taught by Song and to include the teachings of circuit devices disposed on the active surfaces as taught by Costa since active devices are part of the chips although Song did not show in order to simplify the drawings and illustrations. Absent this important teaching in Song, a person with ordinary skill in the art would be motivated to reach out to Costa while forming a semiconductor package of Song.
Regarding claim 2, Song discloses, the semiconductor package as claimed in claim 1, wherein the at least one second semiconductor structure is between the first semiconductor structure and the third semiconductor structure (Fig. 1; [0024]),
In the embodiment of Fig. 4, Song discloses, the second semiconductor structure (100) having a planar area smaller than a planar area of the first semiconductor structure (300); and
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of two embodiments of Song, to modify the teachings of a semiconductor package as taught in Fig. 1 and to include the teachings of a semiconductor package as taught in Fig. 4 since in MPEP 2144.04 (IV) (A), it is stated that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
With the teaching of Song’s two embodiments and MPEP 2144.04 (IV) (A), it is well within the purview of a person with ordinary skill in the art to have a planar area of the at least one second semiconductor structure being smaller than a planar area of the first semiconductor structure and a planar area of the third semiconductor structure.
Regarding claim 3, Song discloses, the semiconductor package as claimed in claim 1, further comprising an encapsulant (500) surrounding side surfaces of the at least one second semiconductor structure (100), wherein the encapsulant (500) is between the first semiconductor structure (300) and the third semiconductor structure (200) (including intervening second semiconductor structure 100; Fig. 1; [0020]).
Claims 12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193640 A1 (Song) and further in view of US 2024/0030126 A1 (Costa).
Regarding claim 12, Song discloses, a semiconductor package, comprising:
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a first semiconductor structure (300; logic chip; Fig. 1; [0024]) including a first semiconductor layer (301 and 320; Fig. 1; [0024]) having a first active surface (as annotated on Fig. 1) and a first inactive surface (as annotated on Fig. 1) opposing the first active surface (as annotated on Fig. 1), and a first bonding layer (as annotated on Fig. 1) on the first active surface of the first semiconductor layer (301 and 320);
a plurality (see MPEP 2144.04 (VI) (B)) of second semiconductor structure (100; integrated voltage regulator chip; Fig. 1; [0019]) on the first semiconductor structure (300), the at least one second semiconductor structure (100) respectively including a second semiconductor layer (101; body) having a second active surface (as annotated on Fig. 1) and a second inactive surface (as annotated on Fig. 1) opposing the second active surface, a second frontside bonding layer (105; lower pad; Fig. 1; [0035]) on the second active surface of the second semiconductor layer (100), and a second backside bonding layer (122; chip pad; Fig. 1; [0035]) on the second inactive surface of the second semiconductor layer (100), and
Note: In MPEP 2144.04 (VI) (B), it is stated that the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
a through-structure (110; through electrode; Fig. 1; [0033]) passing through the second semiconductor layer (101) to connect the second semiconductor layer (101) and the second backside bonding layer (122) to each other;
a third semiconductor structure (200; passive element chip; Fig. 1; [0019]) on the at least one second semiconductor structure (100), the third semiconductor structure (200) including a third semiconductor layer (201) having a third active surface (as annotated on Fig. 1) and a third inactive surface (as annotated on Fig. 1) opposing the third active surface, and a third bonding layer (222) on the third active surface of the third semiconductor layer (200); and
an encapsulant (500; sealing material; Fig. 1; [0020]) surrounding outer surfaces of the plurality of second semiconductor structures (100) between the first semiconductor structure (300) and the second semiconductor structure(100).
But Song fails to teach explicitly, a first device layer on the first active surface, the first device layer including a first circuit device, a second device layer on the second active surface, the second device layer including a second circuit device, a second frontside bonding layer on the second device layer, a third device layer including a third circuit device on the third active surface,
However, in analogous art, Costa discloses, a first device layer (54T) on the first active surface, the first device layer including a first circuit device (first active device), a second device layer (54S) on the second active surface, the second device layer including a second circuit device (second active device), a third device layer (54) including a third circuit device (third active device) on the third active surface (as annotated on Fig. 2; [0079] – [0081]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Song and Costa before him/her, to modify the teachings of a semiconductor package as taught by Song and to include the teachings of circuit devices disposed on the active surfaces as taught by Costa since active devices are part of the chips although Song did not show in order to simplify the drawings and illustrations. Absent this important teaching in Song, a person with ordinary skill in the art would be motivated to reach out to Costa while forming a semiconductor package of Song.
With the teaching of Song and Costa, the second frontside bonding layer (105; lower pad; Fig. 1; [0035]; Song Ref.) is on the second device layer (Costa Ref.).
Regarding claim 16, Song discloses, the semiconductor package as claimed in claim 12, wherein: the first semiconductor structure is face-to-face bonded to a lowermost second semiconductor structure among the plurality of second semiconductor structures, and the third semiconductor structure is back-to-face bonded to an uppermost second semiconductor structure among the plurality of second semiconductor structures (Fig. 3A; [0039]).
Note: Song teaches face-to-back between first and second structures and face-to-face between second and third structures. With this teaching, it is well within the purview of a person with ordinary skill in the art to make the bonding as stated in claim 16. In MPEP 2144.04 (C), it is stated that Rearrangement of parts is held to be an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
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Regarding claim 17, Song discloses, the semiconductor package as claimed in claim 16, wherein the face-to- face bonding or the back-to-face bonding is a structure in which semiconductor structures are directly bonded to each other (Fig. 3A; [0039]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Song and Costa as applied to claim 12 and further in view of US 2023/0395481 A1 (Liu).
Regarding claim 15, the combination of Song and Costa fails to teach explicitly, the semiconductor package as claimed in claim 12, wherein: the first semiconductor structure includes a buffer chip or an interposer chip, and the plurality of second semiconductor structures includes a memory chip.
However, in analogous art, Liu discloses, the semiconductor package as claimed in claim 12, wherein: the first semiconductor structure (as annotated on Fig. 1H) includes a buffer chip or an interposer chip (interposer), and the plurality of second semiconductor structures (700 and 800, as annotated on Fig. 1H) includes a memory chip (700) (Fig. 1H; [0049]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Song, Costa and Liu before him/her, to modify the teachings of a semiconductor package including logic and IVR chips as taught by Song and to include the teachings of semiconductor package structures including interposer and memory chip as taught by Liu since in MPEP 2143 (I) (B), it is stated that Simple substitution of one known element for another to obtain predictable results is obvious. Absent this important teaching in Song, a person with ordinary skill in the art would be motivated to reach out to Liu while forming a semiconductor package of Song.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193640 A1 (Song) and further in view of US 2024/0030126 A1 (Costa).
Regarding claim 18, Song discloses, a semiconductor package, comprising:
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a first semiconductor structure (300; logic chip; Fig. 1; [0024]) including a first semiconductor layer (301 and 320; Fig. 1; [0024]) having a first active surface (as annotated on Fig. 1) and a first inactive surface (as annotated on Fig. 1) opposing the first active surface (as annotated on Fig. 1), and a first bonding layer (as annotated on Fig. 1) on the first active surface of the first semiconductor layer (301 and 320);
a second semiconductor structure (100; integrated voltage regulator chip; Fig. 1; [0019]) on the first semiconductor structure (300),
an encapsulant (500; sealing material; Fig. 1; [0020]) covering a side surface of the second semiconductor structure (100) on the first semiconductor structure (300),
wherein the second semiconductor structure (100) includes: a second semiconductor layer (101; body) having a second active surface (as annotated on Fig. 1) and a second inactive surface (as annotated on Fig. 1) opposing the second active surface; and
a second frontside bonding layer (105; lower pad; Fig. 1; [0035]) on the second active surface of the second semiconductor layer (101; body) and directly bonded to the first bonding layer (as annotated on Fig. 1).
In the embodiment of Fig. 4, Song discloses, the second semiconductor structure (100) having a planar area smaller than a planar area of the first semiconductor structure (300); and
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of two embodiments of Song, to modify the teachings of a semiconductor package as taught in Fig. 1 and to include the teachings of a semiconductor package as taught in Fig. 4 since in MPEP 2144.04 (IV) (A), it is stated that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
But Song fails to teach explicitly, a second semiconductor layer having a second active surface on which a second circuit device is disposed.
However, in analogous art, Costa discloses, a second semiconductor layer (as annotated on Fig. 2) having a second active surface (as annotated on Fig. 2) on which a second circuit device is disposed (as annotated on Fig. 2; [0079] – [0081]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Song and Costa before him/her, to modify the teachings of a semiconductor package as taught by Song and to include the teachings of circuit devices disposed on the active surfaces as taught by Costa since active devices are part of the chips although Song did not show in order to simplify the drawings and illustrations. Absent this important teaching in Song, a person with ordinary skill in the art would be motivated to reach out to Costa while forming a semiconductor package of Song.
Regarding claim 19, the combination of Song and Costa discloses, the semiconductor package as claimed in claim 18, wherein the second semiconductor structure further includes: an interconnection layer (as annotated on Fig. 2) between the second semiconductor layer (as annotated on Fig. 2) and the second frontside bonding layer (30B) (Fig. 2; [0065]);
a second backside bonding layer (72B) on the second inactive surface (as annotated on Fig. 2) of the second semiconductor layer (as annotated on Fig. 2; [0082]); and
a through-electrode (72A) passing through the second semiconductor layer (as annotated on Fig. 2; [0080]; Costa Reference).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Song and Costa as applied to claim 19 and further in view of US 2024/0413274 A1 (Li).
Regarding claim 20, the combination of Song and Costa fails to teach explicitly, the semiconductor package as claimed in claim 19, wherein a thickness of the second frontside bonding layer is greater than a thickness of the second backside bonding layer.
However, in analogous art, Li discloses, the semiconductor package as claimed in claim 19, wherein a thickness of the second frontside bonding layer is greater than a thickness of the second backside bonding layer ([0013]).
Note: Li teaches in para. [0013] that the thickness of two bonding layers could be different or the same. Therefore, it is well within the purview of a person with ordinary skill in the art to make the thickness of the second frontside bonding layer greater than the thickness of the second backside bonding layer. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0045] that the claimed thicknesses are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thicknesses). Also, the applicant has not shown that the claimed thicknesses produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Song, Costa and Li before him/her, to modify the teachings of a semiconductor package including the bonding layers as taught by Song and to include the teachings of the thickness of two bonding layers could be different or the same as taught by Li since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Song, a person with ordinary skill in the art would be motivated to reach out to Li while forming a semiconductor package of Song.
Allowable Subject Matter
Claims 4-5 and 9-11 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 4, the closest prior art, US 2021/0193640 A1 (Song), in combination with US 2024/0030126 A1 (Costa), US 2023/0395481 A1 (Liu) and US 2024/0413274 A1 (Li), fails to disclose, “the semiconductor package as claimed in claim 3, wherein an outer surface of the encapsulant is coplanar with an outer surface of the first semiconductor structure and an outer surface of the third semiconductor structure”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 5, the closest prior art, US 2021/0193640 A1 (Song), in combination with US 2024/0030126 A1 (Costa), US 2023/0395481 A1 (Liu) and US 2024/0413274 A1 (Li), fails to disclose, “the semiconductor package as claimed in claim 3, wherein an upper surface of the encapsulant is in contact with the third bonding layer of the third semiconductor structure, and a lower surface of the encapsulant is in contact with a second frontside bonding layer of a lowermost second semiconductor structure among the at least one second semiconductor structure”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 9, the closest prior art, US 2021/0193640 A1 (Song), in combination with US 2024/0030126 A1 (Costa), US 2023/0395481 A1 (Liu) and US 2024/0413274 A1 (Li), fails to disclose, “the semiconductor package as claimed in claim 1, wherein the first bonding layer, the second frontside bonding layer, or the third bonding layer includes: an interconnection pad connected to circuit devices, a passivation layer covering the interconnection pad, a bonding insulating layer on the passivation layer, and a bonding pad passing through the bonding insulating layer to be in contact with the interconnection pad”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 13, the closest prior art, US 2021/0193640 A1 (Song), in combination with US 2024/0030126 A1 (Costa), US 2023/0395481 A1 (Liu) and US 2024/0413274 A1 (Li), fails to disclose, “the semiconductor package as claimed in claim 12, wherein: an upper surface of the encapsulant is covered by the third bonding layer, and a lower surface of the encapsulant is covered by the second frontside bonding layer of a lowermost second semiconductor structure among the plurality of second semiconductor structures”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 10-11 and 14 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2024/0113006 A1 (Marin) - A microelectronic assembly is disclosed comprising an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.
US 2023/0031430 A1 (Liu) - A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die.
US 2022/0157732 A1 (Tsai) - A semiconductor package is disclosed including a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
02/18/2026