Prosecution Insights
Last updated: April 18, 2026
Application No. 18/376,359

MULTI-MATERIAL CHUCK

Non-Final OA §102§103
Filed
Oct 03, 2023
Examiner
ABEL, GARY ROBERT
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
31 granted / 35 resolved
+20.6% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
46 currently pending
Career history
81
Total Applications
across all art units

Statute-Specific Performance

§103
77.8%
+37.8% vs TC avg
§102
14.7%
-25.3% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending and have been examined. Claim Rejections - 35 USC § 102 The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— (2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20180370210 A1 – hereinafter Kim). Regarding independent Claim 16, Kim teaches: A wafer chuck (110 – Fig. 1B – [0021] – “upper supporting plate 110 is a structure on which a first wafer 210 to be bonded is disposed and fixed and may be referred to as an upper chuck”) comprising: a first portion (Fig. 1B annotated, see below – [0022] – “The vacuum grooves 112 may have an annular shape and may include an inner vacuum groove 112in formed adjacent to a center portion of the upper supporting plate 110 and an outer vacuum groove 112out formed adjacent to an outer portion of the upper supporting plate 110” – hereinafter ‘1P’) comprising a first vacuum pad (112 – Fig. 1B – [0022] – “The vacuum grooves 112” – these are interpreted as pads); PNG media_image1.png 692 792 media_image1.png Greyscale a second portion (Fig. 1B annotated, see above, hereinafter ‘2P’) which does not comprise a vacuum pad (112), the second portion (2P) exhibiting greater compliance (Fig. 3B shows this) than either of the first portion (1P) or a third portion (Fig. 1B annotated, see above, hereinafter ‘3P’); and the third portion (3P) comprising a second vacuum pad (112 – Fig. 1B annotated shows this). Regarding claim 17, Kim teaches claim 16 from which claim 17 depends. Kim further teaches the first portion (1P) second wafer holder, the second portion (2P), and the third portion (3P) are concentric (Fig. 1B shows this); and the second portion (2P) intermediates the first portion (1P) from the second portion (2P). Regarding claim 18, Kim teaches claim 16 from which claim 18 depends. Kim further teaches wherein the first portion (1P) and the third portion (3P) are respective portions of a same monolithic structure ([0035] – “the structure of a vacuum groove 112a formed in the upper supporting plate 110” – ‘formed in’ describes one monolithic structure). Regarding claim 19, Kim teaches claim 16 from which claim 19 depends. Kim further teaches a fourth portion ([0022] – “although two vacuum grooves 112 are formed on the bottom surface Fs1 of the upper supporting plate 110, the number of the vacuum grooves 112 is not limited thereto. For example, only one vacuum groove 112 may be formed on the bottom surface Fs1 of the upper supporting plate 110, or three or more vacuum grooves 112 may be formed in some embodiments” – hereinafter ‘4P’) concentrically intermediating the second portion (2P) from a fifth portion ([0022] – “although two vacuum grooves 112 are formed on the bottom surface Fs1 of the upper supporting plate 110, the number of the vacuum grooves 112 is not limited thereto. For example, only one vacuum groove 112 may be formed on the bottom surface Fs1 of the upper supporting plate 110, or three or more vacuum grooves 112 may be formed in some embodiments” – hereinafter ‘5P’), the third portion (3P) being a portion of a same monolithic structure ([0035] – “the structure of a vacuum groove 112a formed in the upper supporting plate 110” – ‘formed in’ describes one monolithic structure) as the first portion (1P) and the third portion (3P); and the fifth portion (5P) concentrically intermediating the fourth portion (4P) from the third portion (3P), the fifth portion (5P) being a portion of a same monolithic structure ([0035] – “the structure of a vacuum groove 112a formed in the upper supporting plate 110” – ‘formed in’ describes one monolithic structure) as the second portion (2P). Regarding claim 20, Kim teaches claim 16 from which claim 20 depends. Kim further teaches wherein the second portion (2P) comprises a plurality of segments mechanically decoupled ([0023] – “inner vacuum groove 112in and the outer vacuum groove 112out may be connected to each other through the inside pipeline and may be connected to the vacuum pump 300 together or may be connected to the vacuum pump 300 independently without being connected to each other”) from each other along a facing of the wafer chuck (110 – Fig. 3A shows this). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. Claims 1, 3-7, and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hurley et al. (US 20110198817 A1 – hereinafter Hurley) and Ip (WO 2022225705 A1 – hereinafter Ip). Regarding independent claim 1, Kim teaches: A system (100 – fig. – [0020] – “wafer bonding apparatus 100 according to the present embodiment includes an upper supporting plate 110, a lower supporting plate 120, a bonding initiator 130, and an area sensor 140” – this describes a system) for fabricating semiconductor devices, comprising: a first portion (Fig. 1B annotated, see below – [0022] – “The vacuum grooves 112 may have an annular shape and may include an inner vacuum groove 112in formed adjacent to a center portion of the upper supporting plate 110 and an outer vacuum groove 112out formed adjacent to an outer portion of the upper supporting plate 110” – hereinafter ‘1P1’) of a semiconductor chuck (110 – Fig. 1B – [0021] – “upper supporting plate 110 is a structure on which a first wafer 210 to be bonded is disposed and fixed and may be referred to as an upper chuck”) comprising a first material along a facing thereof; a second portion (Fig. 1B annotated, see below, hereinafter ‘2P1’) of the semiconductor chuck (110) circumscribed about the first portion (110 – Fig. 1B shows this) along the facing (Fs1 – Fig. 3A – [0021] – “surface Fs1”), the second portion (kim (2P1) configured to exhibit greater (Fig. 3B shows this) compliance than the first material; a third portion (Fig. 1B annotated, see below, hereinafter ‘3P1’) of the semiconductor chuck (110) circumscribed about the first portion (1P1) along the facing (Fs1), the third portion (3P1) configured to exhibit greater (Fig. 3B annotated, see below, shows this) than the first material; and a plurality of wafer holders disposed along the facing, the wafer holders configured to selectively couple a to a semiconductor wafer along the facing. Kim does not expressly disclose the other limitations of claim 1. PNG media_image2.png 692 792 media_image2.png Greyscale However, in an analogous art, Hurley teaches a first material (130 – Fig. 3 – [0030] – “support structures 124 are also coated with a protective coating layer or covered with a compliant membrane 130”) along a facing thereof (Fig. 3 shows 130 along a face of 120). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first material structure as taught by Hurley into Kim. An ordinary artisan would have been motivated to use the known technique of Hurley in the manner set forth above to produce the predictable result of [0016] – “a structural design that does not interfere with, smear, shear off, or contaminate wafer surface structures such as micro bumping, metal post or studs or bond pads.” Kim and Hurley do not expressly disclose the other limitations of claim 1. However, in an analogous art, Ip teaches compliance ([0067] – “the upper chuck 120 may be implemented with some elastic compliance” – Fig. 4B shows greater compliance of the outer areas than the inner areas) than the first material; and a plurality of wafer holders (165 – Fig. 4B – [0053] – “a vacuum pressure 165 provided by the vacuum pump 160” – these are wafer holders) disposed along the facing (122 – Fig. 4B – [0053] – “mounting surface 122 of the upper chuck 120” – this is a facing), the wafer holders (165) configured to selectively couple a to a semiconductor wafer (W1 – Fig. 4B – [0053] – “upper wafer W1”) along the facing (122). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the compliance and wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result [Abstract] – “of wafer bonding apparatuses and methods to reduce post-bond wafer distortion that occurs primarily within the center and/or the edge of the post-bonded wafer pair.” Regarding claim 3, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 3 depends. Kim further teaches further comprising one or more processors (500 – Fig. 8 – [0087] – “the controller 500 may be implemented in the form of a circuit, an electronic component, a microprocessor, or a program capable of applying a movement control signal to the bonding initiator 130, the vertical moving apparatus 200, and/or the horizontal moving apparatus 400, and/or also applying a vacuum control signal to the vacuum pump 300. Furthermore, the controller 500 may also be connected to the area sensor 140 and control the operation of the area sensor 140”) to configured to. Kim and Hurley do not expressly disclose the other limitations of claim 3. However, in an analogous art, Ip teaches cause a striker (140 – Fig. 4B – [0068] – “striker 140”) to displace a first semiconductor wafer (W1 – Fig. 4B – [0068] – “striker 140 used to initiate bonding between the upper wafer (W1)”) from the facing (122 – Fig. 4B – [0053] – “mounting surface 122 of the upper chuck 120”); and cause an actuation of the wafer holders (165 – Fig. 4B – [0053] – “a vacuum pressure 165 provided by the vacuum pump 160” – these are wafer holders) to decouple from the semiconductor wafer subsequent to the displacement of the first semiconductor wafer at the striker ([0067] – “the variable height wafer chuck 210/220 shown in FIGS. 6A and 6B may be alternatively used to implement an upper chuck in an alternative wafer bonding apparatus, in which a striker is provided within a lower chuck to push the lower wafer upward to initiate bonding with the upper wafer” – this describes this limitation), and prior to an arrival of a propagation wave (bonding front – [0054] – “This contact initiates a bonding front that spontaneously propagates radially outward from the center of the upper and lower wafers” – hereinafter ‘BF’) at the wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the configuration as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 4, Kim as modified by Hurley and Ip, teaches claim 3 from which claim 4 depends. Kim further teaches wherein the system further comprises: a sensor (140 – Fig. 1B – [0030] – “area sensor 140”) to detect the propagation wave ([0030] – “area sensor 140 detects a separation of the first wafer 210 are not limited to the mechanisms described above. In other words, as long as a separation of the first wafer 210 from the bottom surface Fs1 of the upper supporting plate 110 may be two-dimensionally detected, any detecting mechanism may be applied to the area sensor 140 of the wafer bonding apparatus 100 according to some embodiments. For example, a distance sensor” – hereinafter ‘PW’), wherein the actuation of the wafer holders is responsive ([0031] – “The propagation of the bonding and the stopping of the vacuum adsorption”) to a signal detected by the sensor (140). Kim and Hurley do not expressly disclose the other limitations of claim 4. However, in an analogous art, Ip teaches the wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 5, Kim as modified by Hurley and Ip, teaches claim 4 from which claim 5 depends. Kim further teaches wherein the signal is based on a vertical distance ([0030] – “area sensor 140 detects a separation of the first wafer 210 are not limited to the mechanisms described above. In other words, as long as a separation of the first wafer 210 from the bottom surface Fs1 of the upper supporting plate 110 may be two-dimensionally detected, any detecting mechanism may be applied to the area sensor 140 of the wafer bonding apparatus 100 according to some embodiments. For example, a distance sensor”) between the semiconductor chuck (110) and the first semiconductor wafer (210 – Fig. 3C – [0030] – “first wafer 210”). Regarding claim 6, Kim as modified by Hurley and Ip, teaches claim 4 from which claim 6 depends. Kim further teaches further comprising a second sensor (140out – Fig. 3C – [0037] – “area sensor 140 has a structure separated into the inner portion 140in and the outer portion 140out”), wherein: the sensor (140in – Fig. 3C – [0037] – “area sensor 140 has a structure separated into the inner portion 140in and the outer portion 140out”) is configured to detect a first indication of the propagation wave (PW) at a first point ([0088] – “the area sensor 140 detects a pressure change, an electrical change, or a distance change in determining areas at a set time point, the determiner 600 may determine that the propagation of the bonding between the first wafer 210 and the second wafer 220 is normal” – Fig. 3C shows this) along the first semiconductor wafer (210); the second sensor (140out) is configured to detect a second indication of the propagation wave (PW) at a second point (the area where 140out is located) along the first semiconductor wafer (210); and the one or more processors (500) are configured to determine a propagation speed, based on an elapsed time between the first indication and the second indication, the actuation of the wafer holders being based on the propagation speed ([0062] – “The first determining area DA1 and the second determining area DA2 may also be defined so as to check whether the bonding of the first wafer 210 and the second wafer 220 or the separation of the first wafer 210 from the bottom surface Fs1 of the upper supporting plate 110 is propagating normally in terms of time and/or location” – time and distance determine speed, this describes this limitation). Kim and Hurley do not expressly disclose the other limitations of claim 6. However, in an analogous art, Ip teaches the wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 7, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 7 depends. Kim further teaches wherein the semiconductor chuck (110) further comprises: a fourth portion ([0022] – “although two vacuum grooves 112 are formed on the bottom surface Fs1 of the upper supporting plate 110, the number of the vacuum grooves 112 is not limited thereto. For example, only one vacuum groove 112 may be formed on the bottom surface Fs1 of the upper supporting plate 110, or three or more vacuum grooves 112 may be formed in some embodiments” – hereinafter ‘4P1’) of the semiconductor chuck (110) circumscribed about the second portion (2P1) along the facing, the fourth portion (4P1) comprising the first material (112 is a monolithic structure so it is the same material); and a fifth portion ([0022] – “although two vacuum grooves 112 are formed on the bottom surface Fs1 of the upper supporting plate 110, the number of the vacuum grooves 112 is not limited thereto. For example, only one vacuum groove 112 may be formed on the bottom surface Fs1 of the upper supporting plate 110, or three or more vacuum grooves 112 may be formed in some embodiments” – hereinafter ‘5P1’) of the semiconductor chuck (110) circumscribed about the fourth portion (4P1) along the facing, the fifth portion (5P1) configured to exhibit greater compliance than the first material (112 is a monolithic structure so it is the same material), wherein the third portion (3P1) is circumscribed about the fifth portion (5P1). Regarding claim 9, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 9 depends. Kim and Ip do not expressly disclose the limitations of claim 9. However, in an analogous art, Hurley teaches wherein the first material compromises silicon carbide (SiC), silicon dioxide (SiO2), silicon oxynitride (SiOxNy), silicon oxy-carbonitride (SiOCN), silicon carbonitride (SiCN), silicon nitride (SiN), alumina (A1203), or aluminum nitride (AIN) ([0015] – “top and bottom components are made of silicon, alumina, or ceramic materials”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the material structure as taught by Hurley into Kim and Ip. An ordinary artisan would have been motivated to use the known technique of Hurley in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 10, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 10 depends. Kim and Ip do not expressly disclose the limitations of claim 10. However, in an analogous art, Hurley teaches wherein the first material compromises silicon carbide (SiC), silicon dioxide (SiO2), silicon oxynitride (SiOxNy), silicon oxy-carbonitride (SiOCN), silicon carbonitride (SiCN), silicon nitride (SiN), alumina (A1203), or aluminum nitride (AIN) ([0015] – “top and bottom components are made of silicon, alumina, or ceramic materials”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the material structure as taught by Hurley into Kim and Ip. An ordinary artisan would have been motivated to use the known technique of Hurley in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding independent claim 11, Kim teaches: A method ([0003] – “wafer bonding process may be performed by using a direct bonding method in which two wafers are directly bonded without a separate medium”), comprising: actuating a plurality of wafer holders (165 – Fig. 4B – [0053] – “a vacuum pressure 165 provided by the vacuum pump 160” – these are wafer holders) to couple a first wafer (210) to a wafer chuck (110 – Fig. 1B – [0021] – “upper supporting plate 110 is a structure on which a first wafer 210 to be bonded is disposed and fixed and may be referred to as an upper chuck”); instantiating, at an instantiation point, wafer bonding between the first wafer (210) and a second wafer (220 – [0047] – “second wafer 220”), wherein the first wafer (210) is coupled to a plurality of portions of the wafer chuck (110 – [0047] – “the center portion of the first wafer 210 is pressed downward by using the bonding initiator 130, thereby separating the center portion of the first wafer 210 from the bottom surface Fs1 of the upper supporting plate 110. A separation distance by which the first wafer 210 is separated from the bottom surface Fs1 of the upper supporting plate 110 may vary according to a location of the inner vacuum groove 112in” – this describes this limitation), the plurality of portions comprising: a first portion (Fig. 1B annotated, see below – [0022] – “The vacuum grooves 112 may have an annular shape and may include an inner vacuum groove 112in formed adjacent to a center portion of the upper supporting plate 110 and an outer vacuum groove 112out formed adjacent to an outer portion of the upper supporting plate 110” – hereinafter ‘1P1’) comprising a first material; a second portion (Fig. 1B annotated, see below, hereinafter ‘2P1’) circumscribing first portion (1P1), the second portion (2P1) configured to exhibit greater (Fig. 3B shows this) compliance than the first portion (1P1); and a third portion (Fig. 1B annotated, see below, hereinafter ‘3P1’) circumscribing the first portion (1P1), the third portion (3P1) comprising the plurality of wafer holders. PNG media_image2.png 692 792 media_image2.png Greyscale Kim does not expressly disclose the other limitations of claim 11. However, in an analogous art, Hurley teaches a first material (130 – Fig. 3 – [0030] – “support structures 124 are also coated with a protective coating layer or covered with a compliant membrane 130”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first material structure as taught by Hurley into Kim. An ordinary artisan would have been motivated to use the known technique of Hurley in the manner set forth above to produce the predictable result of [0016] – “a structural design that does not interfere with, smear, shear off, or contaminate wafer surface structures such as micro bumping, metal post or studs or bond pads.” Kim and Hurley do not expressly disclose the other limitations of claim 11. However, in an analogous art, Ip teaches compliance ([0067] – “the upper chuck 120 may be implemented with some elastic compliance” – Fig. 4B shows greater compliance of the outer areas than the inner areas), the plurality of wafer holders (165 – Fig. 4B – [0053] – “a vacuum pressure 165 provided by the vacuum pump 160” – these are wafer holders). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the compliance and wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result [Abstract] – “of wafer bonding apparatuses and methods to reduce post-bond wafer distortion that occurs primarily within the center and/or the edge of the post-bonded wafer pair.” Regarding claim 12, Kim as modified by Hurley and Ip, teaches claim 11 from which claim 12 depends. Kim further teaches an outer portion (112out – Fig. 1B – [0022] – “an outer vacuum groove 112out formed adjacent to an outer portion of the upper supporting plate 110”) of the first wafer (210 – Fig. 1A – [0021] – “first wafer 210”) from the third portion (Fig. 1B annotated, see above, hereinafter ‘3P’) of the wafer chuck. Kim and Hurley do not expressly disclose the other limitations of claim 12. However, in an analogous art, Ip teaches further comprising: actuating the plurality of wafer holders (165) to decouple an outer portion of the first wafer from the third portion of the wafer chuck ([0067] – “the variable height wafer chuck 210/220 shown in FIGS. 6A and 6B may be alternatively used to implement an upper chuck in an alternative wafer bonding apparatus, in which a striker is provided within a lower chuck to push the lower wafer upward to initiate bonding with the upper wafer” – this describes this limitation), subsequent to the instantiation of the wafer bonding and prior to an arrival of a propagation wave (bonding front – [0054] – “This contact initiates a bonding front that spontaneously propagates radially outward from the center of the upper and lower wafers” – hereinafter ‘BF’) to a point of the wafer laterally aligned with the plurality of wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the actuation of the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 11. Regarding claim 13, Kim as modified by Hurley and Ip, teaches claim 12 from which claim 13 depends. Kim and Hurley do not expressly disclose the other limitations of claim 13. However, in an analogous art, Ip teaches further comprising; actuating a second wafer holder (165) of the first portion (Fig. 4B annotated – see below – hereinafter ‘1P’) of the wafer chuck (120 – fig. 4B – [0067] – “the upper chuck 120”), to decouple an inner portion (Fig. 4B annotated – see below – hereinafter ‘InP’) of the first wafer (W1 – Fig. 4B – [0068] – “striker 140 used to initiate bonding between the upper wafer (W1)”) from the first portion (1P) of the wafer chuck (120), prior to actuating the plurality of wafer holders to decouple the outer portion (Fig. 4B annotated – see below – hereinafter ‘OutP’) of the first wafer (W1). PNG media_image3.png 306 822 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the actuation of the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 11. Regarding claim 14, Kim as modified by Hurley and Ip, teaches claim 11 from which claim 14 depends. Kim further teaches further comprising: detecting, via one or more propagation sensors (140 – Fig. 1B – [0030] – “area sensor 140”), a position of a propagation wave ([0088] – “the area sensor 140 detects a pressure change, an electrical change, or a distance change in determining areas at a set time point, the determiner 600 may determine that the propagation of the bonding between the first wafer 210 and the second wafer 220 is normal” – this describes a propagation wave – hereinafter ‘PW’, Fig. 3C shows this); and actuating the plurality of wafer holders to decouple the first wafer (210 – Fig. 3C – [0030] – “first wafer 210”) from the wafer chuck, subsequent to the instantiation of the wafer bonding and prior to an arrival of a propagation wave to a point of the wafer laterally aligned with the plurality of wafer holders. Kim and Hurley do not expressly disclose the other limitations of claim 14. However, in an analogous art, Ip teaches actuating the plurality of wafer holders (165 – Fig. 4B – [0053] – “a vacuum pressure 165 provided by the vacuum pump 160” – these are wafer holders) to decouple the first wafer from the wafer chuck ([0067] – “the variable height wafer chuck 210/220 shown in FIGS. 6A and 6B may be alternatively used to implement an upper chuck in an alternative wafer bonding apparatus, in which a striker is provided within a lower chuck to push the lower wafer upward to initiate bonding with the upper wafer” – this describes this limitation), subsequent to the instantiation of the wafer bonding and prior to an arrival of a propagation wave (bonding front – [0054] – “This contact initiates a bonding front that spontaneously propagates radially outward from the center of the upper and lower wafers” – hereinafter ‘BF’) to a point of the wafer laterally aligned with the plurality of wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the actuation of the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 11. Regarding claim 15, Kim as modified by Hurley and Ip, teaches claim 11 from which claim 15 depends. Kim further teaches wherein the position of the propagation wave (PW) comprises a plurality of positions disposed around a circumference of the wafer chuck; and the actuation of the plurality of wafer holders to decouple the first wafer from the wafer chuck comprises: decoupling a first wafer holder of the plurality of wafer holders responsive to a first detection of the propagation wave (PW) at a first chordal point (140in (Fig. 1B – [0028] – “The area sensor 140 may include an inner portion 140in and an outer portion 140out”); and decoupling a second wafer holder of the plurality of wafer holders responsive to a second detection of the propagation wave (PW) at a second chordal point (140out (Fig. 1B – [0028] – “The area sensor 140 may include an inner portion 140in and an outer portion 140out”). Kim and Hurley do not expressly disclose the other limitations of claim 14. However, in an analogous art, Ip teaches wherein the position of the propagation wave (PW) comprises a plurality of positions (R1-R5 – Fig. 5 – [0059] – “radial rib (R1-R5)”) disposed around a circumference of the wafer chuck (200 – Fig. 5 – [0059] – “wafer chuck 200” – Fig. 5 shows this); and the actuation of the plurality of wafer holders (165) to decouple the first wafer (302 – Fig. 8B – [0078] – “upper wafer 302”) from the wafer chuck (200) comprises: decoupling a first wafer holder of the plurality of wafer holders (165), decoupling a second wafer holder of the plurality of wafer holders (165). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the actuation of the wafer holder structure as taught by Ip into Kim and Hurley. An ordinary artisan would have been motivated to use the known technique of Ip in the manner set forth above to produce the predictable result as stated above in claim 11. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hurley, Ip, and Tsai et al. (US 20250079228 A1 – hereinafter Tsai). Regarding claim 2, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 2 depends. Kim, Hurley, and Ip do not expressly disclose the limitations of claim 2. However, in an analogous art, Tsai teaches wherein the wafer holders comprise vacuum pads (252 – [0036] – “vacuum pumping manifolds (252 …” – these are vacuum pads). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the wafer pads structure as taught by Tsai into Kim, Hurley, and Ip. An ordinary artisan would have been motivated to use the known technique of Tsai in the manner set forth above to produce the predictable result of providing support for the wafer structure while applying vacuum pressure to hold the wafer in place. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hurley, Ip, and Mizuta (US 20230091517 A1 – hereinafter Mizuta). Regarding claim 8, Kim as modified by Hurley and Ip, teaches claim 1 from which claim 2 depends. Kim, Hurley, and Ip do not expressly disclose the limitations of claim 2. However, in an analogous art, Mizuta teaches wherein the semiconductor chuck further comprises: a backing layer (20 – Fig. 3 – [0028] – “the upper chuck UC includes a body part 20. The diameter of the body part 20 is larger than that of the upper wafer UW in the plane view. In the body part 20, ribs 21, 22, 23, and 24, a plurality of pins 25, a plurality of suction ports 26, 27, and 28, and a through hole” – this describes a backing layer) along a second facing of the semiconductor chuck ({[0006] – “configuration of an upper chuck”}, {[0007 – “configuration of a lower chuck”} – these are a chuck – hereinafter ‘102’), opposite the facing, the backing layer (20) and the second portion of the semiconductor chuck (UC) comprise a monolithic structure (UC – Fig. 3 – [0028] – “the upper chuck UC includes a body part 20. The diameter of the body part 20 is larger than that of the upper wafer UW in the plane view. In the body part 20, ribs 21, 22, 23, and 24, a plurality of pins 25, a plurality of suction ports 26, 27, and 28, and a through hole” – this describes a monolithic structure, hereinafter ‘502’) extending through the semiconductor chuck (102) along an axis perpendicular to the facing (Fig. 3 shows this). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backing layer structure as taught by Mizuta into Kim, Hurley, and Ip. An ordinary artisan would have been motivated to use the known technique of Mizuta in the manner set forth above to produce the predictable result of providing support for the wafer structure while applying vacuum pressure to hold the wafer in place. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Pertinent Art For the benefits of the Applicant, US 6257564 B1, US 20220172993 A1, US 20210356439 A1, US 20230207369 A1, US 20240055290 A1, US 20180284071 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the material composition. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRA/ Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Oct 03, 2023
Application Filed
Jan 12, 2026
Non-Final Rejection — §102, §103
Mar 23, 2026
Examiner Interview Summary
Mar 23, 2026
Applicant Interview (Telephonic)
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+16.7%)
3y 4m
Median Time to Grant
Low
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