DETAILED ACTION
This Office action responds to the application filed on 10/03/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Species 1, reading on Figure 9, in the reply filed on January 14, 2026, is acknowledged. Since the applicant did not explicitly state the election was made with or without traverse, the election has been treated as an election without traverse (MPEP § 818.01(a)).
The applicant indicates that claims 1-10 read on the elected species. The examiner agrees. Accordingly, claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, & 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tang (US 20210202489).
Regarding Claim 1, Tang (see, e.g., fig. 14a) shows a semiconductor device, comprising:
a substrate 12 (see, e.g., para.0020);
a first dielectric layer (combination of layers 14, 18, & 26, see, e.g., fig. 2a, para.0021),
a second dielectric layer 20 (see, e.g., para.0023),
and a third dielectric layer sequentially disposed on the substrate (combination of layers 28, 32, & 92, see, e.g., fig. 14b, para.0060);
a source structure 26 & 18 (additionally 18 coupled to 26, see, e.g., para.0026-0027) in the first dielectric layer;
a drain structure 28 & 32 (additionally 32 coupled to 28, see, e.g., para.0026) in the third dielectric layer;
a channel structure 30 (see, e.g., para.0026) extending through the second dielectric layer and directly contacting the source structure and the drain structure;
and a gate structure 84 (see, e.g., para.0055) disposed at two sides of the channel structure, wherein the gate structure comprises:
a conductive layer 86 & 88 (see, e.g., para.0055);
and a gate dielectric layer 78 (see, e.g., para.0051) along sidewalls and a bottom surface of the conductive layer and interposed between the conductive layer and the channel structure and the second dielectric layer.
Regarding Claim 2, Tang (see, e.g., fig. 14a) shows the semiconductor device according to claim 1,
wherein the gate dielectric layer 78 has a U-shaped cross-sectional profile (see, e.g., fig. 14).
Regarding Claim 10, Tang (see, e.g., fig. 14a) shows the semiconductor device according to claim 1,
wherein the conductive layer, the source structure, and the drain structure comprise tungsten (see, e.g., para.0022, para.0027, para.0055),
the channel structure comprises poly silicon (see, e.g., para.0023).
Claims 1 & 3 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Miyairi (US 20250275174).
Regarding Claim 1, Miyairi (see, e.g., fig. 14b) shows a semiconductor device, comprising:
a substrate (under 212 not shown, see, e.g., para.0343);
a first dielectric layer 212 (see, e.g., para.0344),
a second dielectric layer (combination of layers 250 & 274, see, e.g., para.0150, para.0265),
and a third dielectric layer 278 (see, e.g., para.0265) sequentially disposed on the substrate;
a source structure 244 (see, e.g., para.0261) in the first dielectric layer;
a drain structure 246c (see, e.g., para.0236) in the third dielectric layer;
a channel structure 230 (see, e.g., para.0261) extending through the second dielectric layer and directly contacting the source structure 244 and the drain structure 246c (see, e.g., fig. 14b);
and a gate structure 260 & 254a disposed at two sides of the channel structure, wherein the gate structure comprises:
a conductive layer 260 (see, e.g., para.0099);
and a gate dielectric layer 254a (see, e.g., para.0334) along sidewalls and a bottom surface of the conductive layer and interposed between the conductive layer and the channel structure and the second dielectric layer.
Regarding Claim 3, Miyairi (see, e.g., annotated figure 14b) shows the semiconductor device according to claim 1,
wherein the gate dielectric layer 254a comprises:
vertical portions along the sidewalls of the conductive layer;
and a lateral portion along the bottom surface of the conductive layer,
wherein top surfaces of the vertical portions are flush with a top surface of the second dielectric layer.
Claims 1, 4, 5, & 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Anderson (US 20170373170).
Regarding Claim 1, Anderson (see, e.g., fig. 13a) shows a semiconductor device, comprising:
a substrate 102 (see, e.g., para.0028);
a first dielectric layer (combination of layers 902, 702, 704, & 104, see, e.g., para.0038),
a second dielectric layer (combination of layers fins/channels 106, 108, 110, high-k dielectric layers 1002, 1004, 1106, spacers 1108, see, e.g., para.0042),
and a third dielectric layer 1202 (see, e.g., para.0023) sequentially disposed on the substrate;
a source structure 104 (see, e.g., para.0030) in the first dielectric layer;
a drain structure 1204 (see, e.g., para.0044) in the third dielectric layer;
a channel structure 106 (see, e.g., para.0030) extending through the second dielectric layer and directly contacting the source structure 104 and the drain structure 1204 (see, e.g., fig. 13a);
and a gate structure 1102 & 1002 disposed at two sides of the channel structure, wherein the gate structure comprises:
a conductive layer 1102 (see, e.g., para.0041);
and a gate dielectric layer 1002 (see, e.g., para.0039, fig. 10a) along sidewalls and a bottom surface of the conductive layer and interposed between the conductive layer and the channel structure and the second dielectric layer.
Regarding Claim 4, Anderson (see, e.g., fig. 13a) shows the semiconductor device according to claim 1,
wherein the gate structure further comprises:
an insulating cap layer 1108 (see, e.g., para.0042) disposed on the conductive layer,
wherein a top surface of the insulating cap layer is flush with the top surface of the second dielectric layer (see, e.g., fig. 13a).
Regarding Claim 5, Anderson (see, e.g., fig. 13a) shows the semiconductor device according to claim 4,
wherein the drain structure 1204 is in direct contact with the top surface of the insulating cap layer 1108 (see, e.g., fig. 13a).
Regarding Claim 6, Anderson (see, e.g., fig. 13a) shows the semiconductor device according to claim 4,
wherein the gate dielectric layer 1002 is interposed between the insulating cap layer 1108 and the channel structure 106 and the second dielectric layer (see, e.g., fig. 13a).
Claims 1, 7, 8, & 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hung (US 20190081181).
Regarding Claim 1, Hung (see, e.g., fig. 1) shows a semiconductor device, comprising:
a substrate 100 (see, e.g., para.0016);
a first dielectric layer (combination of layers 902, 702, 704, & 104, see, e.g., para.0038),
a second dielectric layer (combination of layers fins/channels 106, 108, 110, high-k dielectric layers 1002, 1004, 1106, spacers 1108, see, e.g., para.0042),
and a third dielectric layer 1202 (see, e.g., para.0023) sequentially disposed on the substrate;
a source structure 101 (see, e.g., para.0016) in the first dielectric layer;
a drain structure 201 (see, e.g., para.0018) in the third dielectric layer;
a channel structure 200 (see, e.g., para.0018) extending through the second dielectric layer and directly contacting the source structure 101 and the drain structure 201 (see, e.g., fig. 1);
and a gate structure 300 & 310 disposed at two sides of the channel structure, wherein the gate structure comprises:
a conductive layer 300 (see, e.g., para.0020);
and a gate dielectric layer 310 (see, e.g., para.0020, fig. 1) along sidewalls and a bottom surface of the conductive layer and interposed between the conductive layer and the channel structure and the second dielectric layer.
Regarding Claim 7, Hung (see, e.g., fig. 1) shows the semiconductor device according to claim 1,
wherein the second dielectric layer comprises:
an etching stop layer 112 (see, e.g., para.0017);
a dielectric material layer 110 (see, e.g., para.0017) on the etching stop layer;
and a pad layer 122 (see, e.g., para.0040) on the dielectric material layer,
wherein the gate structure is above the etching stop layer and through the dielectric material layer and the pad layer (see, e.g., fig. 1).
Regarding Claim 8, Hung (see, e.g., annotated figure 1) shows the semiconductor device according to claim 7,
wherein a top surface of the conductive layer 300 is at a same height as a bottom surface of the pad layer 122 (see, e.g., annotated figure 1).
Regarding Claim 9, Hung (see, e.g., annotated figure 1) shows the semiconductor device according to claim 7,
wherein a top surface of the conductive layer 300 is lower than a bottom surface of the pad layer 122 (see, e.g., annotated figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814