DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 04/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 04/29/2026 in reply to the non-final rejection mailed on 02/19/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 4 & 5 are canceled. Accordingly, pending in this Office action are claims 1-3 & 6-10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 6, 7, 8, 9, & 10 are rejected under 35 U.S.C. 103 as being unpatentable over You (US 20210225766) in view of Tang (US 20210202489).
Regarding Claim 1, You (see, e.g., fig. 19a) shows a semiconductor device, comprising:
a substrate 202 (see, e.g., para.0014);
a first dielectric layer 208 (see, e.g., fig. 2a, para.0018),
a second dielectric layer 212b (see, e.g., fig. 3, para.0021),
and a third dielectric layer 246 & 250 (see, e.g., para.0026) sequentially disposed on the substrate;
a source structure 214 (see, e.g., para.0013) in the first dielectric layer;
a drain structure 280 (see, e.g., para.0030) in the third dielectric layer;
a channel structure 220 (see, e.g., para.0024) extending through the second dielectric layer and directly contacting the source structure and the drain structure;
and a gate structure 210, 212a, & 232 disposed at two sides of the channel structure, wherein the gate structure comprises:
a conductive layer 210 (see, e.g., para.0055);
an insulating cap layer 232 (see, e.g., fig. 5, para.0023) disposed on the conductive layer;
and a gate dielectric layer 212a (see, e.g., para.0051) along sidewalls of the conductive layer and interposed between the conductive layer and the channel structure and the second dielectric layer.
wherein the drain structure 280 directly contacts
a top surface of the insulating cap layer 232
and a top surface of the gate dielectric layer 212a,
and the third dielectric layer directly contacts the top surface of the insulating cap layer
Regarding the limitation “wherein the drain structure 280 directly contacts a top surface of the insulating cap layer 232” You (see, e.g., fig. 19a) shows direct contact between 280 and the top inclined surface of 232. The top inclined surface of 232 is still considered to be a top surface as the current claim language does not require direct contact with a topmost horizontal surface.
You, however, fails to show
and the gate dielectric layer along a bottom surface of the conductive layer.
Tang (see, e.g., fig. 14a, para.0051), in a similar device to You, teaches a gate dielectric layer 78 along sidewalls and a bottom surface of the conductive layer 86 & 88. The shape of the gate dielectric layer of Tang is incorporated into the device of You (see, e.g., annotated figure 1).
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the gate dielectric layer of Tang in the device of You as a simple substitution of one known element for another, gate dielectric layers, to obtain predictable results.
Regarding Claim 2, You, in view of Tang, shows the semiconductor device according to claim 1,
wherein the gate dielectric layer 212a has a U-shaped cross-sectional profile (see, e.g., annotated figure 1).
Regarding Claim 3, You (see, e.g., annotated figure 2), in view of Tang shows the semiconductor device according to claim 1,
wherein the gate dielectric layer 212a comprises:
vertical portions along the sidewalls of the conductive layer 210 (see, e.g., annotated figure 2);
and a lateral portion along the bottom surface of the conductive layer 210 (see, e.g., annotated figure 2),
wherein top surfaces of the vertical portions are flush with a top surface of the second dielectric layer 212b (see, e.g., annotated figure 2).
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Regarding Claim 6, You, in view of Tang, shows the semiconductor device according to claim 1,
wherein the gate dielectric layer 212a is interposed between the insulating cap layer 232 and the channel structure 220 and the second dielectric layer 212b (see, e.g., annotated figure 3).
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Regarding Claim 7, You, in view of Tang, shows the semiconductor device according to claim 1,
You, in view of Tang, however, fails to show
wherein the second dielectric layer 212b comprises:
an etching stop layer;
a dielectric material layer on the etching stop layer;
and a pad layer on the dielectric material layer,
wherein the gate structure is above the etching stop layer and through the dielectric material layer and the pad layer.
You (see, e.g., para.0021) states the second dielectric layer 212b is a part of the gate dielectric layer surrounding conductive layer 210. Tang (see, e.g., fig. 14a, para.0051) teaches the gate dielectric layer 78 along sidewalls and a bottom surface of the conductive layer 86 & 88. The shape of the gate dielectric layer of Tang is incorporated into the second dielectric layer 212b of You (see, e.g., annotated figure 4).
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Since the etching stop layer, the dielectric material layer, and the pad layer of the second dielectric layer are not claimed to be different materials, Examiner has indicated portions of the second dielectric layer that recite the limitations
wherein the second dielectric layer 212b (see, e.g., annotated figure 5, para.0021) comprises:
an etching stop layer (hereinafter referred to as “A”);
a dielectric material layer (hereinafter referred to as “B”) on the etching stop layer;
and a pad layer (hereinafter referred to as “C”) on the dielectric material layer,
wherein the gate structure 210, 212a, & 232 is above the etching stop layer and through the dielectric material layer and the pad layer.
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Regarding Claim 8, You, in view of Tang, shows the semiconductor device according to claim 7,
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wherein a top surface of the conductive layer 210 is at a same height as a bottom surface of the pad layer C (see, e.g., annotated figure 6).
Regarding Claim 9, You, in view of Tang, shows the semiconductor device according to claim 7,
wherein a top surface of the conductive layer 210 is lower than a bottom surface of the pad layer C (see, e.g., annotated figure 7).
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Regarding Claim 10, You, in view of Tang (see, e.g., para.0022-0023, para.0027, para.0055) shows the semiconductor device according to claim 1,
wherein the conductive layer 86 & 88 (corresponding to 210 of You), the source structure18 & 26 (corresponding to 214 of You), and the drain structure 28 & 32 (corresponding to 280 You) comprise tungsten (see, e.g., para.0022, para.0027, para.0055),
the channel structure 30 (corresponding to 220 of You) comprises poly silicon (see, e.g., para.0023).
Response to Arguments
Applicant’s arguments, see pages 9-13, filed 04/29/2026, with respect to the rejection(s) of claim(s) 1-10 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of You & Tang.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/ Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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