DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 1 is amended.
Claim 2 has been cancelled.
Claims 1 and 3-5 have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2012/0311304 by Tomono et al. (hereinafter referred to as “Tomono”).
Regarding claim 1, Tomono discloses:
an instruction decompression method, wherein the instruction decompression method is applied to a hardware circuit that decompresses an instruction and executes the instruction, the instruction comprises a header, and the header comprises a reference value, the instruction decompression method comprising: (Tomono discloses, at ¶ [0115], a restoring instructions using the circuitry disclosed at Figure 15 and related description, which discloses a decompression method where a hardware circuit decompresses and executes the instructions. As disclosed at Figure 11B and related description, each instruction group includes a compression information group indicating whether instructions are compressed or not, which discloses a header having a reference value.)
reading a first parameter of the instruction to obtain a total number of mismatched parameters when the reference value of the instruction is a preset value (Tomono discloses, at Figure 15 and related description, bit field information registers that indicate how many values are compressed, which discloses reading a first parameter to obtain a total number when the reference value is a preset value. See also Figure 19 and related description, which discloses determining the number of compressed instructions.); and
using a plurality of second parameters of the instruction to set a plurality of corresponding parameters of the hardware circuit, the number of second parameters is equal to the total number of mismatched parameters (Tomono discloses, at Figure 15 and related description, restoring each compressed instruction, which discloses using a plurality of second parameters of the instruction to set a plurality of corresponding parameters of the hardware circuit. See also Figure 19 and related description.); and
using all parameters of the instruction to set the corresponding parameters of the hardware circuit when the reference value of the instruction is not the preset value (Tomono discloses, at Figure 15 and related description, fetching and executing non-compressed instructions, which discloses using all parameters when the reference value is not the preset value. See also Figure 19 and related description, which discloses processing operands for non-compressed instructions.).
Regarding claim 3, Tomono discloses the elements of claim 1, as discussed above. Tomono also discloses:
the hardware circuit comprises a plurality of registers, and the corresponding parameters are register values of the registers (Tomono discloses, at Figure 15 and related description, the processor includes registers and the instructions specify registers, which discloses the corresponding parameters being register values of the registers.).
Regarding claim 4, Tomono discloses the elements of claim 1, as discussed above. Tomono also discloses:
when the total number of mismatched parameters is N, the second parameters are the second parameter to the (N+1)th parameter of the instruction (Tomono discloses, at Figure 11A and related description, the instructions include fields, the second through last of which are the registers to be restored, which discloses N parameters and the second through (N+1)th parameter.).
Regarding claim 5, Tomono discloses the elements of claim 1, as discussed above. Tomono also discloses:
the instruction is a variable-length instruction (Tomono discloses, at Figure 11B and related description, instruction groups of different lengths, which discloses variable length instructions.).
Response to Arguments
On pages 5-6 of the response filed August 14, 2025 (“response”), the Applicant argues, “According to the limitations of claim 1, different actions are performed depending on whether the reference value of the instruction is the preset value. The Examiner's opinion regarding the reference value is as follows. Specifically, the Examiner has equated the reference value with a compression information group. However, Tomono fails to disclose that different actions are performed according to the compression information group: one action is to read a first parameter of the instruction to obtain a total number of mismatched parameters, while the other action is to use all parameters of the instruction to set the corresponding parameters of the hardware circuit.”
Though fully considered, the Examiner respectfully disagrees. Tomono discloses, at Figures 15 and 19 and related description, a decompression process. The decompression process involves determining whether the instruction is a compressed instruction based on a bit, i.e. reference value. If so, first processing is performed, including determining the number of compressed operands. If not, second processing is performed, including using the operands of the non-compressed instruction. The Examiner maintains that this discloses the claimed two different actions based on the value of a reference value, as claimed. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 5 of the response the Applicant argues, “In addition, Tomono fails to disclose the limitation "the number of second parameters is equal to the total number of mismatched parameters."”
Though fully considered, the Examiner respectfully disagrees. As discussed above, Tomono discloses, e.g., at ¶ [0157], determining the number of compressed instructions. The Examiner maintains that this discloses the number of second parameters being equal to the total number of mismatched parameters. If the same number of instructions that was compressed was not decompressed, the processor’s performance would be unreliable. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183