DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114885250 A (Huang) in view of US 2015/0064901 A1 (Wakatsuki).
Regarding claim 1, Huang discloses, A method (method (300); FIG. 3; [n0118]) for manufacturing an interconnection structure (interconnection structure (100 or 200); FIGs. 1T or 2S; [n0118]), comprising:
forming a first conductive metal (first conductive metal (112); FIG. 1E; [n0071]) on a first dielectric layer (first dielectric layer (104); FIG. 1E; [n0058]);
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forming a hard mask layer (hard mask layer (114); FIG. 1E; [n0071]) on the first conductive metal (112);
patterning the hard mask layer (114) and partially etching the first conductive metal (112) to form a first conductive feature (annotated FIG 1F, below; [n0072]);
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forming a barrier layer (barrier layer (118); FIG. 1G; [n0074]) on the first dielectric layer (104), sidewalls of the first conductive feature (annotated FIG. 1G, below), and the hard mask layer (114);
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forming a second dielectric layer (second dielectric layer (126); FIG. 1L; [n0081]) on the barrier layer (118), the first conductive feature (annotated FIG. 1L, below), and the hard mask layer (114);
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performing a planarization process ([n0082] and [n0083]) to remove the hard mask layer (114) and a portion of the second dielectric layer (126) to expose a top surface of the first conductive feature (annotated FIG. 1N, below) and a top surface of the second dielectric layer (top surface of second dielectric layer (130); FIG. 1N; [n0083]); and
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forming a capping layer (caping layer (242); FIG. 2S; [n0114]) on the top surface (annotated FIG. 2S, below) of the first conductive feature (annotated FIG. 2S, below).
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But, Huang does not appear to explicitly disclose,
that the capping layer is formed only on the top surface of the first conductive feature; and
forming a catalyst layer on the top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap.
However it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Huang before him/her to form the capping layer (242) of Huang only on the top surface (annotated FIG. 2S, above) of the first conductive feature (annotated FIG. 2S, above) of Huang thereby saving material cost and/or enhancing manufacturing efficiency by saving time associated with forming of additional capping layer (242) on other components of interconnection structure (100 or 200) of Huang. Please see, MPEP 2143(G)—The courts have made clear that the teaching, suggestion, or motivation test is flexible and an explicit suggestion to combine the prior art is not necessary. The motivation to combine may be implicit and may be found in the knowledge of one of ordinary skill in the art, or, in some cases, from the nature of the problem to be solved. DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1366; 80 USPQ2d 1641, 1649 (Fed. Cir. 2006). [A]n implicit motivation to combine exists not only when a suggestion may be gleaned from the prior art as a whole, but when the ‘improvement’ is technology-independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.
But, Huang does not appear to explicitly disclose, forming a catalyst layer on the top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap.
However, in analogous art, Wakatsuki discloses, that it is well known that a catalyst metal layer is added to a silicide layer, the thermal stability of the silicide film is improved ([0098]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her to form a catalyst layer on the top surface (annotated FIG. 2S, above) of the second dielectric layer (second dielectric layer (226); FIG. 2P; [n0105]) of Huang in preparation for formation of a silicide layer, to improve the thermal stability of the silicide layer, as taught by Wakatsuki. See also, MPEP 2144(IV)—The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her that the capping layer(242) and the catalyst layer do not overlap because the capping layer (242) of Huang can only be formed on the top surface of the first conductive feature (annotated FIG. 2S, above), as discussed above, and not on the top surface (annotated FIG. 2S, above) of the second dielectric layer (226).
Regarding claim 2, Huang in view of Wakatsuki discloses, The method (300) according to claim 1, wherein the first conductive feature (annotated FIG. 1N, above) is a conductive post (annotated FIG. 1N, above), and before the planarization process, the hard mask layer (114) overlies the top surface of the first conductive feature (annotated FIG. 1L, above), and the second dielectric layer (126) surrounds the sidewalls of the first conductive feature (annotated FIG. 1L, above).
Regarding claim 3, Huang in view of Wakatsuki does not appear to explicitly disclose, wherein the top surface of the first conductive feature and the top surface of the second dielectric layer are coplanar.
However, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that there are a finite number of predicable solutions for the top surface of the first conductive feature (annotated FIG. 1N, above) of Huang relative to the top surface (130) of the second dielectric layer (126) of Huang—i.e., the top surface of the first conductive feature (annotated FIG. 1N, above) can lie in a different plane than top surface (130) of the second dielectric layer (126) or it can lie in the same plane (be coplanar) as top surface (130) of the second dielectric layer (126)—and, absent unexpected results, it would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to try each of them with a reasonable expectation of success, one of which is: wherein the top surface of the first conductive feature and the top surface of the second dielectric layer are coplanar, as recited by claim 3.
Regarding claim 4, Huang in view of Wakatsuki discloses, The method (300) according to claim 1, wherein the first conductive feature (annotated FIG. 1F, above) is formed by reactive ion etching ([n0072]).
Regarding claim 13, Huang discloses, An interconnection structure (interconnection structure (100 or 200); FIGs. 1T or 2S; [n0118]) comprising:
a first dielectric layer (first dielectric layer (104); FIG. 1E; [n0058]);
a first conductive feature (FIG. 1E; [n0071]; annotated FIG 1F, above; [n0072]) disposed on the first dielectric layer (104);
a second dielectric layer (second dielectric layer (126); FIG. 1L; [n0081]) disposed on the first dielectric layer (104), wherein the second dielectric layer (126) surrounds sidewalls (annotated FIG. 1L, above) of the first conductive feature (annotated FIG. 1L above);
a barrier layer (barrier layer (118); FIG. 1G; [n0074]) disposed between the first dielectric layer (104) and the second dielectric layer (126) (FIG. 1L) and between the sidewalls (annotated FIG. 1L, above) of the first conductive feature (annotated FIG. 1L, above) and the second dielectric layer (126) (annotated FIG. 1L, above); and
a capping layer (caping layer (132); FIG. 1O; [n0084]) disposed on a top surface (annotated 1O, below) of the first conductive feature (annotated FIG. 1O, below).
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But, Huang does not appear to explicitly disclose,
that the capping layer is disposed only on a top surface of the first conductive feature; and
a catalyst layer disposed on a top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap.
However it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Huang before him/her that the capping layer (132) of Huang is disposed only on a top surface (annotated FIG. 1O, above) of the first conductive feature (annotated FIG. 1O, above) of Huang thereby saving material cost and/or enhancing manufacturing efficiency by saving time associated with forming of additional capping layer (132) on other components of interconnection structure (100 or 200) of Huang. Please see, MPEP 2143(G), above.
But, Huang does not appear to explicitly disclose, a catalyst layer disposed on a top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap.
However, in analogous art, Wakatsuki discloses, that it is well known that a catalyst metal layer is added to a silicide layer, the thermal stability of the silicide film is improved ([0098]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her to form a catalyst layer disposed on the top surface (top surface of second dielectric layer (130); FIG. 1N; [n0083], all of Huang) of the second dielectric layer (126) of Huang in preparation for formation of a silicide layer, to improve the thermal stability of the silicide layer, as taught by Wakatsuki. See also, MPEP 2144(IV), above.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her that the capping layer(132) and the catalyst layer do not overlap because the capping layer (132) of Huang can only be formed on the top surface of the first conductive feature (annotated FIG. 1O, above), as discussed above, and not on the top surface of the second dielectric layer (126).
Regarding claim 16, Huang discloses, The interconnection structure (100 or 200) according to claim 13, further comprising a second conductive feature (second conductive feature (144); FIG. 1S; [n0090]) disposed on the first conductive feature (annotated FIG. 1S, below) and the capping layer (132).
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki, as applied to claim 1, above, and further in view of US 2020/0312815 A1 (Morein).
Regarding claim 5, Huang in view of Wakatsuki discloses, The method (300) according to claim 1, further comprising:
forming a layer (metal oxide layer (254); FIG. 2S; [n0108]) by a rapid atomic layer deposition (ALD) ([n0108]), wherein the layer (254) surrounds the capping layer (242);
forming an etch stop layer (etch stop layer (232); FIG. 2S; [n0105]) on the layer (254) and the capping layer (242);
forming a third dielectric layer (third dielectric layer (234); FIG. 2P; [n0111]) on the etch stop layer (232), removing a portion of the third dielectric layer (234) to form an opening (opening (240); FIG. 2Q; [n0112]) in the third dielectric layer (234); and
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forming a second conductive feature (second conductive feature (244); FIG. 2R; [n0114]) in the opening (240) and on the third dielectric layer (234).
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But, Huang in view of Wakatsuki does not appear to explicitly disclose,
forming a silicide layer on the catalyst layer; and
forming the etch stop layer on the silicide layer.
However, in analogous art, Morein discloses that it is well-know that silicides provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes ([0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, and Morein before him/her that: (i) layer (254) of Huang in view of Wakatsuki be formed as a silicide layer to provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes, as taught by Morein; (ii) this silicide layer be formed on the catalyst layer, to improve the thermal stability of the silicide layer, as taught by Wakatsuki; and (iii) the etch stop layer of (232) of Huang in view of Wakatsuki would be formed on the silicide layer of the combination of Huang in view of Wakatsuki and further in view of Morein. See also, MPEP 2144(IV), above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki and Morein, as applied to claim 5, above, and further in view of US 2023/0130702 A1 (Shin).
Regarding claim 6, Huang in view of Wakatsuki and Morein does not appear to explicitly disclose, wherein the capping layer comprises graphene or a self-assembled monolayer.
However, in analogous art, Shin, discloses that it is well-known in an interconnect structure (interconnect structure (100); FIG. 1; [0054]) that a capping layer (capping layer (150; FIG. 1; [0054]) overlying a conductive feature (conductive feature (140); FIG. 1; [0055]) and comprising graphene reduces the resistance of conductive feature (140) and improves adhesion ([0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, Morein, and Shin before him/her that capping layer (242) of Huang in view of Wakatsuki and Morein comprises graphene, as taught by Shin, to reduce the resistance of first conductive feature (annotated FIG. 2S, above) of Huang in view of Wakatsuki and Morein and improve adhesion, as also taught by Shin. See also, MPEP 2144(IV), above.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki and Morein, as applied to claim 5, above, and further in view of US 6,462,152 B1 (Berardi).
Regarding claim 7, Huang in view of Wakatsuki and Morein does not appear to explicitly disclose, wherein the catalyst layer comprises trimethylaluminum (TMA).
However, Berardi discloses that it was well known to one of ordinary skill in the art before the effective filing date of the claimed invention that trimethylaluminum (TMA) is particularly effective at improving catalyst activity in gas phase and also the activity of unsupported catalysts in slurry phase (Col. 2, lines 47-49).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, and Morein, and Berardi before him/her that it was common knowledge to one of ordinary skill in the art before the effective filing date of the claimed invention that the catalyst layer of Huang in view of Wakatsuki and Morein comprises trimethylaluminum (TMA), as taught by Berardi, to provide the advantage of improving catalyst activity in gas phase and/or the activity of unsupported catalysts in slurry phase of the method (300) for manufacturing an interconnection structure (100 or 200) of Huang in view of Wakatsuki and Morein, as also taught by Berardi. See, MPEP 2144(I)—The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. See also, MPEP 2144(IV), above.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki, as applied to claim 13, above, and further in view of Shin.
Regarding claim 15, Huang in view of Wakatsuki does not appear to explicitly disclose, wherein the capping layer comprises graphene or a self-assembled monolayer.
However, in analogous art, Shin, discloses that it is well-known in an interconnect structure (interconnect structure (100); FIG. 1; [0054]) that a capping layer (capping layer (150; FIG. 1; [0054]) overlying a conductive feature (conductive feature (140); FIG. 1; [0055]) and comprising graphene reduces the resistance of conductive feature (140) and improves adhesion ([0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, and Shin before him/her that capping layer (242) of Huang in view of Wakatsuki comprises graphene, as taught by Shin, to reduce the resistance of first conductive feature (annotated FIG. 2S, above) of Huang in view of Wakatsuki and improve adhesion, as also taught by Shin. See also, MPEP 2144(IV), above.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki, as applied to claim 13, above, and further in view of Morein.
Regarding claim 18, Huang in view of Wakatsuki does not appear to explicitly disclose, further comprising a silicide layer disposed on the catalyst layer.
However, in analogous art, Morein discloses that it is well-know that silicides provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes ([0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, and Morein before him/her that interconnect structure (100 or 200) of Huang in view of Wakatsuki further comprise a silicide layer, as taught by Morein, to provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes, as also taught by Morein, and that this silicide layer be disposed on the catalyst layer of Huang in view of Wakatsuki to improve the thermal stability of the silicide layer, as taught by Wakatsuki. See also, MPEP 2144(IV), above.
Claims 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki and further in view of Morein.
Regarding claim 19, Huang discloses, A method (method (300); FIG. 3; [n0118]) for forming silicide on an interconnect structure (interconnection structure (100 or 200); FIGs. 1T or 2S; [n0118]), the interconnection structure (100 or 200) comprising a dielectric layer (dielectric layer (226); FIG. 2P; [n0105], all of Huang) and a conductive feature (FIG. 2B; [n0097]; annotated FIG 2S, above; [n0098]), the method (300) for forming silicide comprising:
forming a capping layer (caping layer (242); FIG. 2S; [n0114]) on a top surface (annotated FIG. 2S, above) of the conductive feature (annotated FIG. 2S, above); and
forming a layer (metal oxide layer (254); FIG. 2S; [n0108], all of Huang) by a rapid atomic layer deposition (ALD) ([n0108]), wherein the layer (254) surrounds the capping layer (242).
But Huang does not appear to explicitly disclose,
that the capping layer is formed only on the top surface of the first conductive feature;
forming a catalyst layer on a top surface of the dielectric layer, wherein the capping layer and the catalyst layer do not overlap; and
forming a silicide layer on the catalyst layer.
However it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Huang before him/her to form the capping layer (242) of Huang only on the top surface (annotated FIG. 2S, above) of the first conductive feature (annotated FIG. 2S, above) of Huang thereby saving material cost and/or enhancing manufacturing efficiency by saving time associated with forming of additional capping layer (242) on other components of interconnection structure (100 or 200) of Huang. Please see, MPEP 2143(G), above.
But Huang does not appear to explicitly disclose,
forming a catalyst layer on a top surface of the dielectric layer, wherein the capping layer and the catalyst layer do not overlap; and
forming a silicide layer on the catalyst layer.
However, in analogous art, Wakatsuki discloses, that it is well known that a catalyst metal layer is added to a silicide layer, the thermal stability of the silicide film is improved ([0098]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her to form a catalyst layer on a top surface (annotated FIG. 2P, above) of the dielectric layer (226) of Huang in preparation for formation of a silicide layer, to improve the thermal stability of the silicide layer, as taught by Wakatsuki. See also, MPEP 2144(IV), above.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Wakatsuki before him/her that the capping layer(242) and the catalyst layer do not overlap because the capping layer (242) of Huang can only be formed on the top surface of the first conductive feature (annotated FIG. 2S, above), as discussed above, and not on the top surface (annotated FIG. 2S, above) of the second dielectric layer (226).
But the combination of Huang in view of Wakatsuki does not appear to explicitly disclose, forming a silicide layer on the catalyst layer.
However, in analogous art, Morein discloses that it is well-know that silicides provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes ([0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, and Morein before him/her that layer (254) of Huang in view of Wakatsuki be formed as a silicide layer to provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes, as taught by Morein, and that this silicide layer be formed on the catalyst layer to improve the thermal stability of the silicide layer, as taught by Wakatsuki. See also, MPEP 2144(IV), above.
Regarding claim 22, Huang in view of Wakatsuki and further in view of Morein discloses, The method (300) for forming silicide according to claim 19, wherein the capping layer (242) is formed before the catalyst layer is formed because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. Please see, MPEP 2144.04(IV)(C).
Claims 19 and 22 are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of US 9,728,485 (Lee) and further in view of Morein.
Regarding claim 19, Huang discloses, A method (method (300); FIG. 3; [n0118]) for forming silicide on an interconnect structure (interconnection structure (100 or 200); FIGs. 1T or 2S; [n0118]), the interconnection structure (100 or 200) comprising a dielectric layer (dielectric layer (226); FIG. 2P; [n0105], all of Huang) and a conductive feature (FIG. 2B; [n0097]; annotated FIG 2S, above; [n0098]), the method (300) for forming silicide comprising:
forming a capping layer (caping layer (242); FIG. 2S; [n0114]) on a top surface (annotated FIG. 2S, above) of the conductive feature (annotated FIG. 2S, above); and
forming a layer (metal oxide layer (254); FIG. 2S; [n0108], all of Huang) by a rapid atomic layer deposition (ALD) ([n0108]), wherein the layer (254) surrounds the capping layer (242).
But Huang does not appear to explicitly disclose,
that the capping layer is formed only on the top surface of the first conductive feature;
forming a catalyst layer on a top surface of the dielectric layer, wherein the capping layer and the catalyst layer do not overlap; and
forming a silicide layer on the catalyst layer.
However it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Huang before him/her to form the capping layer (242) of Huang only on the top surface (annotated FIG. 2S, above) of the first conductive feature (annotated FIG. 2S, above) of Huang thereby saving material cost and/or enhancing manufacturing efficiency by saving time associated with forming of additional capping layer (242) on other components of interconnection structure (100 or 200) of Huang. Please see, MPEP 2143(G), above.
But Huang does not appear to explicitly disclose,
forming a catalyst layer on a top surface of the dielectric layer, wherein the capping layer and the catalyst layer do not overlap; and
forming a silicide layer on the catalyst layer.
However, in analogous art, Lee discloses that it is well-known that catalyst layer (catalyst layer (116); FIG. 1C; Col. 4, line 49) may be disposed on a dielectric layer (dielectric layer (108); FIG. 1C; Col. 3, lines 30-31) in an interconnect structure (Title of the Invention). Lee also discloses that it is well-known that catalyst layer (116) may be used to facilitate the formation of a conductive feature (conductive feature (118); FIG. 1C; Col. 4, lines 57-58) and that, in some embodiments, catalyst layer (116) is capable of lowering a formation temperature of conductive feature (118).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Lee before him/her to form a catalyst layer on a top surface (annotated FIG. 2P, above) of the dielectric layer (226) of Huang, as taught by Lee, to facilitate subsequent formation of a conductive layer (e.g., a silicide layer) and, in some instances, lower a formation temperature of the conductive layer, as also taught by Lee. See also, MPEP 2144(IV), above.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang and Lee before him/her that the capping layer(242) and the catalyst layer do not overlap because the capping layer (242) of Huang can only be formed on the top surface of the first conductive feature (annotated FIG. 2S, above), as discussed above, and not on the top surface (annotated FIG. 2S, above) of the second dielectric layer (226).
But the combination of Huang in view of Lee does not appear to explicitly disclose, forming a silicide layer on the catalyst layer.
However, in analogous art, Morein discloses that it is well-know that silicides provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes ([0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Lee, and Morein before him/her that layer (254) of Huang in view of Lee be formed as a silicide layer to provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes, as taught by Morein, and that this silicide layer be formed on the catalyst layer to facilitate formation of the silicide layer and, in some instances, lower a formation temperature of the silicide layer, as taught by Lee. See also, MPEP 2144(IV), above.
Regarding claim 22, Huang in view of Lee and further in view of Morein discloses, The method (300) for forming silicide according to claim 19, wherein the capping layer (242) is formed before the catalyst layer is formed because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. Please see, MPEP 2144.04(IV)(C).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wakatsuki and Morein, as applied, claim 19, above, further in view of US 2024/0130242 A1 (Zhao).
Regarding claim 21, Huang in view of Wakatsuki and Morein does not appear to explicitly disclose, wherein the capping layer comprises a self-assembled monolayer.
However, in analogous art, Zhao discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a capping layer (capping layer (510); FIG. 8; [0048]) may be predicably fabricated to comprise a self-assembled monolayer ([0013] and [0048]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Wakatsuki, Morein, and Zhao before him/her that capping layer (242) of Huang in view of Wakatsuki and Morein can be predicably fabricated to comprise a self-assembled monolayer, as taught by Zhao, with no change in the function of capping layer (242) of Huang in view of Wakatsuki and Morein because it would still protect conductive feature (annotated FIG. 2S, above) of Huang in view of Wakatsuki and Morein.
Claim 21 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Lee and Morein, as applied, claim 19, above, further in view of Zhao.
Regarding claim 21, Huang in view of Lee and Morein does not appear to explicitly disclose, wherein the capping layer comprises a self-assembled monolayer.
However, in analogous art, Zhao discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a capping layer (capping layer (510); FIG. 8; [0048]) may be predicably fabricated to comprise a self-assembled monolayer ([0013] and [0048]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Huang, Lee, Morein, and Zhao before him/her that capping layer (242) of Huang in view of Lee and Morein can be predicably fabricated to comprise a self-assembled monolayer, as taught by Zhao, with no change in the function of capping layer (242) of Huang in view of Lee and Morein because it would still protect conductive feature (annotated FIG. 2S, above) of Huang in view of Lee and Morein.
Allowable Subject Matter
Claims 8-12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Amendments and Arguments
Applicant’s amendment of dependent claims 8 and 20 in the “Amendment Under 37 C.F.R. § 1.111” dated March 5, 2026 (hereinafter the “Reply”) has overcome the objection thereto in the Office Action dated December 8, 2025 (hereinafter the “Office Action”). Also, Applicant’s amendment of dependent claims 8 and 20 in the Reply has overcome the rejection thereof under 35 U.S.C. 112(b) in the Office Action. The Examiner notes that on page eight (8) of the Reply, Applicant respectfully traverses the rejection of dependent claims 8 and 20 under 35 U.S.C. 112(b) in the Office Action. For clarity of the written record, the Examiner respectfully notes that Applicant has provided no rational for why the original rejection of unamended dependent claims 8 and 20 under 35 U.S.C. 112(b) in the Office Action is traversed.
Applicant’s amendment of independent claims 1, 13, and 19 and remarks with respect thereto on pages ten (10)-twelve (12) of the Reply have been fully considered. However, they are not deemed persuasive for at least the following reasons.
For example, regarding amended independent claim 1, pages ten (10)-eleven (11) of the Reply state:
In particular, the Examiner has not provided any evidence showing where and how the cited references teach the feature "forming a capping layer only on the top surface of the first conductive feature; and forming a catalyst layer on the top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap" as recited in amended claim 1.
The Examiner respectfully disagrees at least because the Office Action did, in fact, provide evidence showing where and how the cited reference teach the recited limitations in original unamended claim 5 of “forming a capping layer on the top surface of the first conductive feature; and forming a catalyst layer on the top surface of the second dielectric layer” which were added to amended independent claim 1 in the Reply. Also, regarding the additional limitations added to amended independent claim 1, which were not in Applicant’s originally filed claims, for clarity of the written record, the Examiner respectfully does not understand how he could anticipate such amendments to independent claim 1 and provide “evidence showing where and how the cited references teach the[se] feature[s]” in the Office Action. However, such evidence is now provided in this Final Office Action.
As another example, regarding amended independent claim 13, pages ten (10)-eleven (11) of the Reply state:
Similarly, the Examiner has not provided any evidence showing where and how the cited references teach the feature "a capping layer disposed only on a top surface of the first conductive feature; and a catalyst layer disposed on a top surface of the second dielectric layer, wherein the capping layer and the catalyst layer do not overlap" as recited in amended claim 13.
The Examiner respectfully disagrees at least because the Office Action did, in fact, provide evidence showing where and how the cited reference teach the recited limitations in respective original dependent claims 14 and 17 (which were cancelled in Applicant’s Reply) of “further comprising a capping layer disposed on a top surface of the first conductive feature; and further comprising a catalyst layer disposed on a top surface of the second dielectric layer” which were added to amended independent claim 13 in the Reply. Also, regarding the additional limitations added to amended independent claim 13, which were not in Applicant’s originally filed claims, for clarity of the written record, the Examiner respectfully does not understand how he could anticipate such amendments to independent claim 13 and provide “evidence showing where and how the cited references teach the[se] feature[s]” in the Office Action. However, such evidence is now provided in this Final Office Action.
As an additional example, regarding amended independent claim 19, page 11 of the Reply states:
In addition, the Examiner alleged that it would have been obvious to one of ordinary skill in the art to modify Huang in view of Wakatsuki and Morein to arrive at the claimed invention of claim 19. However, the Examiner has not provided any evidence showing where and how the cited references teach the feature "the capping layer and the catalyst layer are formed on a top surface of the conductive feature and a top surface of the dielectric layer respectively and do not overlap" as recited in amended claim 19.
The Examiner respectfully disagrees at least because amended independent claim 19 actually does not recite that “the capping layer and the catalyst layer are formed on a top surface of the conductive feature”, as asserted by Applicant. Amended independent claim 19, in fact, actually recites: “forming a capping layer only on a top surface of the conductive feature” and “”forming a catalyst layer on a top surface of the dielectric layer”. Also, the Office Action did, in fact, provide evidence showing where and how the cited reference teach the recited limitations in original unamended claim 19 of “forming a capping layer on the top surface of the first conductive feature; and forming a catalyst layer on a top surface of the dielectric layer”. Additionally, regarding the further limitations added to amended independent claim 19, which were not in Applicant’s originally filed claims, for clarity of the written record, the Examiner respectfully does not understand how he could anticipate such amendments to independent claim 19 and provide “evidence showing where and how the cited references teach the[se] feature[s]” in the Office Action. However, such evidence is now provided in this Final Office Action.
As a further example, also regarding the rejection of amended independent claim 19, page 11 of the Reply states:
More specifically, Wakatsuki is directed to improving thermal stability by forming a silicide layer on a catalyst layer. Wakatsuki does not teach, or suggest any configuration between a capping layer and a catalyst layer, nor does it disclose a structure in which the capping layer and the catalyst layer do not overlap. In addition, Morein focuses on the material properties and advantages of silicide layers, such as low resistance, being easy to etch, providing good contacts to other materials and being compatible with different semiconductor processes. Morein does not teach, or suggest any configuration between a capping layer and a catalyst layer, nor does it disclose a structure in which the capping layer and the catalyst layer do not overlap.
The Examiner respectfully disagrees at least because it is an argument of nonobviousness that attacks the Wakatsuki and Morein references individually, rather than what the combined teachings of Huang, Wakatsuki and Morein would have taught and/or suggested to one of ordinary skill in the art before the effective filing date of the claimed invention. Please see, MPEP 2145(IV)—One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Where a rejection of a claim is based on two or more references, a reply that is limited to what a subset of the applied references teaches or fails to teach, or that fails to address the combined teaching of the applied references may be considered to be an argument that attacks the reference(s) individually. "[T]he test for obviousness is what the combined teachings of the references would have suggested to [a PHOSITA]." In re Mouttet, 686 F.3d 1322, 1333, 103 USPQ2d 1219, 1226 (Fed. Cir. 2012).
As yet a further example, regarding amended independent claim 19, the Examiner respectfully notes that Applicant’s remarks in the Reply fail to address why the alternative rejection of independent claim 19 under 35 U.S.C. 103 as being unpatentable over Huang in view of Lee and further in view of Morein is respectfully traversed by Applicant.
As yet still a further example, page 11 of the Reply states: “In addition, dependent claims are allowable due to their respective dependence from independent claims 1, 13 and 19, as well as due to the additional recitations included in these claims.” The Examiner respectfully disagrees at least because dependent claims 2-7, 15, 16, and 18 do not recite additional structure and/or limitations over the current prior art of record, as previously detailed in the Office Action, as well as detailed in this Final Office Action. The Examiner respectfully notes that Applicant’s above-quoted remarks do not specifically address the rejections of dependent claims 2-7, 15, 16, and 18, as previous detailed in the Office Action, as well as detailed in this Final Office Action, to explain why “the additional recitations included in these claims” distinguishes them over the current prior art of record.
As yet still an additional further example, page 12 of the Reply states: “Claims 21 and 22 have been added for the Examiner's consideration. Applicant respectfully submits that claims 21 and 22 are allowable due to their respective dependence from independent claim 19, as well as due to the additional recitations included in these claims.” The Examiner respectfully disagrees at least because newly added dependent claims 21 and 22 do not recite additional structure and/or limitations over the current prior art of record, as detailed in this Final Office Action. The Examiner respectfully notes that Applicant’s above-quoted remarks do not specifically address why “the additional recitations included in these claims” are patentable over the current prior art of record.
Notwithstanding the above, in an effort to advance prosecution, the Examiner respectfully requests that Applicant please consider initiating a telephone interview with the Examiner to discuss amendments that Applicant would like to propose to overcome the rejection of claims 1-7, 13, 15, 16, 18, 19, 21, and 22 in this Final Office Action prior to submitting a written response thereto. The Examiner would welcome such a conversation and is available at the telephone number indicated below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812