Prosecution Insights
Last updated: April 19, 2026
Application No. 18/376,674

WAFER SCALE ENHANCED GAIN ELECTRON BOMBARDED CMOS IMAGER

Final Rejection §102
Filed
Oct 04, 2023
Examiner
GUNBERG, EDWIN C
Art Unit
2884
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Elbit Systems Of America LLC
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
84%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
481 granted / 618 resolved
+9.8% vs TC avg
Moderate +7% lift
Without
With
+6.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
22 currently pending
Career history
640
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
51.8%
+11.8% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 618 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Smith et al. (10,734,184). Regarding claim 1, Smith discloses a method of forming an image intensifier, comprising: coupling a plurality of imager anodes to corresponding electrically isolated sets of conductive traces formed across an interconnect wafer (Smith, Col. 5 Lines 1-15 discussing anode 314); aligning a plurality of openings within an insulative spacer wafer with corresponding said plurality of imager anodes (Smith, channels 331); vacuum sealing a plurality of photocathodes within a photocathode wafer over the corresponding plurality of imager anodes while maintaining the corresponding plurality of openings around and between each of the plurality of imager anodes and the corresponding plurality of photocathodes (Smith, Col. 7 Lines 38-41); and dicing perpendicular to the parallel planes formed by the vacuum sealed and spaced interconnect wafer and photocathode wafer, and between the plurality of openings, to produce the image intensifier from among a plurality of concurrently produced image intensifiers. (Smith, Col. 7 Lines 38-41 “each cavity region configured to be assembled in a single image intensifier device, upon slicing of the assembled wafers”) Regarding claim 2, Smith further discloses coupling comprises: fabricating into the interconnect wafer a plurality of complementary metal oxide semiconductor (CMOS) sensors coupled to the electrically isolated sets of conductive traces; and fabricating into the plurality of CMOS sensors a plurality of primary electron multipliers spaced from the plurality of photocathodes. (Smith, Col. 5, Lines 1-15 indicating CMOS sensors as part of a suggested anode structure) Regarding claim 3, Smith further discloses coupling comprises: bonding onto the electrically isolated sets of conductive traces of the interconnect wafer a plurality of complementary metal oxide semiconductor (CMOS) sensors formed on an imager anode wafer (Smith, Col. 5 Lines 1-15 pertaining to the CMOS sensors); and fabricating in the imager anode wafer a primary electron multiplier on a surface of the imager anode wafer between the CMOS sensors and spaced from the plurality of photocathodes. (Smith, Fig. 2A, EBD 312, see Col. 3 Lines 59-65) Regarding claim 4, Smith further discloses aligning comprises: arranging the plurality of openings a spaced distance around corresponding said plurality of imager anodes while abutting the insulative spacer against the interconnect wafer. (Smith, Col. 4 Lines 41-60; Fig. 3) Regarding claim 5, Smith further discloses vacuum sealing comprises evacuating below atmospheric pressure the plurality of openings at the same time. (Smith, Col. 6, Lines 41-44) Regarding claim 6, the dicing cuts through the insulative spacer wafer. (Smith, Col. 5, glass spacer wafers 610, 620 apparently sliced through the non-cavity portion to form individual units) Regarding claim 7, Smith further discloses insulative spacer wafer includes opposing edges and wherein the cut is intermediate the opposing edges. (Smith, comparison of Smith, Cols. 6, 7, and [Figs. 2C, 3, 4, with those shown in Applicant’s 4A-4C, to which this claim is directed, reveals sufficient similarity to indicate anticipation) Response to Arguments Applicant's arguments filed 1/12/2026 have been fully considered but they are not persuasive. Applicant argues that the slicing in Smith is performed prior to cavity evacuation, and that claim 1 is therefore patentably distinct from Smith. This is incorrect. Smith teaches assembly of the glass spacer to the silicon wafer in a vacuum state prior to slicing. See Smith, Col. 6 Line 34 through Col. 7 Line 15. The formation of the seal under vacuum, with included getter to maintain that vacuum through any further processes including slicing, indicates evacuation of the cavity prior to slicing. Smith therefore anticipates the presented claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWIN C GUNBERG whose telephone number is (571)270-3107. The examiner can normally be reached Monday-Friday, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uzma Alam can be reached at 571-272-2995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDWIN C GUNBERG/ Primary Examiner, Art Unit 2884
Read full office action

Prosecution Timeline

Oct 04, 2023
Application Filed
Dec 10, 2025
Non-Final Rejection — §102
Jan 12, 2026
Response Filed
Mar 24, 2026
Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
84%
With Interview (+6.7%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 618 resolved cases by this examiner. Grant probability derived from career allow rate.

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