Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (10,734,184) in view of Nikzad et al. (2011/0256655)
Regarding claim 1, Smith discloses a method of forming an image intensifier, comprising: coupling a plurality of imager anodes to corresponding electrically isolated sets of conductive traces formed across an interconnect wafer (Smith, Col. 5 Lines 1-15 discussing anode 314); aligning a plurality of openings within an insulative spacer wafer with corresponding said plurality of imager anodes (Smith, channels 331); vacuum sealing a plurality of photocathodes within a photocathode wafer over the corresponding plurality of imager anodes while maintaining the corresponding plurality of openings around and between each of the plurality of imager anodes and the corresponding plurality of photocathodes (Smith, Col. 7 Lines 38-41); and dicing perpendicular to the parallel planes formed by the vacuum sealed and spaced interconnect wafer and photocathode wafer, and between the plurality of openings, to produce the image intensifier from among a plurality of concurrently produced image intensifiers. (Smith, Col. 7 Lines 38-41 “each cavity region configured to be assembled in a single image intensifier device, upon slicing of the assembled wafers”)
Smith further discloses coupling comprises: fabricating into the interconnect wafer a plurality of complementary metal oxide semiconductor (CMOS) sensors coupled to the electrically isolated sets of conductive traces; (Smith, Col. 5, Lines 1-15 indicating CMOS sensors as part of a suggested anode structure)
The limitation regarding fabrication of a plurality of primary electron multipliers in the CMOS sensors, spaced from the plurality of photocathodes is herein interpreted in light of Applicant’s remarks of 7/24/2026 to be directed to electron bombarded CMOS structure. (See p. 5 of Applicant’s remarks) Though the Examiner contends that the language used is broader than intended, this rejection assumes Applicant’s construction arguendo.
Smith does not disclose EBCMOS structure.
Nikzad discloses the manufacture of an electron bombarded CMOS detector where primary electron multipliers (in the form of active amplifiers) are provided in each CMOS detector pixel spaced apart from the plurality of photocathodes. (Nikzad, [0104])
It would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to include the EBCMOS technology of Nikzad into the image amplifier of Smith in order to provide “ultra-low power imaging” (Nikzad, [0109], [0110]), and improved signal processing (Nikzad, [0113],[0114]).
Regarding claim 4, Smith further discloses aligning comprises: arranging the plurality of openings a spaced distance around corresponding said plurality of imager anodes while abutting the insulative spacer against the interconnect wafer. (Smith, Col. 4 Lines 41-60; Fig. 3)
Regarding claim 5, Smith further discloses vacuum sealing comprises evacuating below atmospheric pressure the plurality of openings at the same time. (Smith, Col. 6, Lines 41-44)
Regarding claim 6, the dicing cuts through the insulative spacer wafer. (Smith, Col. 5, glass spacer wafers 610, 620 apparently sliced through the non-cavity portion to form individual units)
Regarding claim 7, Smith further discloses insulative spacer wafer includes opposing edges and wherein the cut is intermediate the opposing edges. (Smith, comparison of Smith, Cols. 6, 7, and [Figs. 2C, 3, 4, with those shown in Applicant’s 4A-4C, to which this claim is directed, reveals sufficient similarity to indicate anticipation)
Regarding claim 8, being a restatement of prior claim 3 with amendments in line with those made to claim 1, the combination of Smith and Nikzad further teaches coupling comprises: bonding onto the electrically isolated sets of conductive traces of the interconnect wafer a plurality of complementary metal oxide semiconductor (CMOS) sensors formed on an imager anode wafer (Smith, Col. 5 Lines 1-15 pertaining to the CMOS sensors); and fabricating in the imager anode wafer a primary electron multiplier on a surface of the imager anode wafer between the CMOS sensors and spaced from the plurality of photocathodes. (Smith, Fig. 2A, EBD 312, see Col. 3 Lines 59-65)
Response to Arguments
Applicant's arguments filed 7/24/2026 have been fully considered but they are not persuasive. Applicant asserts that the claim language of claim 1 as amended requires the use of EBCMOS technology, and that Smith does not teach this item. Notwithstanding any differences of opinion regarding the breadth of the claim as written, it is noted that even if the claim is interpreted to require EBCMOS technology, such capabilities are found in the prior art, as evidenced at least by Nikzad.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWIN C GUNBERG whose telephone number is (571)270-3107. The examiner can normally be reached Monday-Friday, 8:30AM-5:00PM.
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/EDWIN C GUNBERG/Primary Examiner, Art Unit 2884
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