CTNF 18/376,767 CTNF 79602 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on November 30, 2023 has been considered by the Examiner. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea (e.g. a mental process) without significantly more. As described in MPEP § 2106, the analysis as to whether a claim qualifies as eligible subject matter under 35 U.S.C. § 101 includes the following determinations: (1) Whether the claim is to a statutory category, i.e. to a process, machine, manufacture or composition of matter (“Step 1”) – see MPEP §§ 2106, subsection III, and 2106.03 (2) If the claim is to a statutory category, whether the claim recites any judicial exceptions, including certain groupings of abstract ideas (i.e., mathematical concepts, certain methods of organizing human activity, or mental processes) (“Step 2A, Prong One”) – see MPEP §§ 2106, subsection III, and 2106.04 (3) If the claim recites a judicial exception, whether the claim recites additional elements that integrate the judicial exception into a practical application (“Step 2A, Prong Two”) – see MPEP §§ 2106, subsection III, and 2106.04 (4) If the claim does not recite additional elements that integrate the judicial exception into a practical application, whether the claim recites additional elements that amount to significantly more than the judicial exception (“Step 2B”) – see MPEP §§ 2106, subsection III, and 2106.05 Claim 1 Regarding “Step 1,” independent claim 1 is to a statutory category, as claim 1 is directed to a processor, which is a machine or manufacture. The analysis thus proceeds to “Step 2A, Prong One” to determine if the claim recites a judicial exception. In this case, the claim recites a mental process. “’[T]he mental processes’ abstract idea grouping in particular is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgements, and opinions.” MPEP § 2106.04(a)(2), subsection III. “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claims recites an abstract idea. MPEP § 2106.04(a)(2), subsection III,B (citations omitted). In this case, the recitation in claim 1 of “to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits” can practically be performed in the human mind, and is thus considered a mental process. Because the claim recites a judicial exception (i.e. a mental process), the analysis proceeds to “Step2A, Prong Two” to determine whether the claim recites additional elements that integrate the judicial exception into a practical application. But other than the above-noted mental process, claim 1 merely recites that “[a] processor comprising: one or more circuits to use one or more neural networks” performs the prediction. This is tantamount to mere instructions to apply the abstract idea on a generic computer and thus fails to integrate the abstract idea into a practical application. See MPEP § 2106.05(f). Accordingly, as claim 1 does not recite additional elements that integrate the judicial exception into a practical application, the analysis proceeds to “Step 2B” to determine whether the claim recites additional elements that amount to significantly more than the judicial exception. However, in this case, claim 1 does not. As noted above, claim 1 comprises additional elements reciting that “[a] processor comprising: one or more circuits to use one or more neural networks” performs the prediction. However, as further noted above, these elements amount to mere instructions to apply the abstract idea on a generic computer. As such, they do not amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Consequently, claim 1 recites an abstract idea but does not include additional elements that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea. As a result, and for the reasons described above, claim 1 is rejected as being patent ineligible under 35 U.S.C. § 101. Claim 2 Claim 2 recites that “one or more of the one or more neural networks are neural networks of a variational autoencoder.” This recitation of one or more neural networks, which is at a high level of generality, is tantamount to mere instructions to apply the judicial exception on a computer. As such, claim 2 fails to integrate the above-noted judicial exception (i.e. mental process) into a practical application or amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Claim 3 Claim 3 further characterizes the mental process recited in claim 1 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 3 recites that “the one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model.” The use of such a cost-predict model, when given its broadest reasonable interpretation, can practically be performed in the human mind. Accordingly, claim 3 recites a mental process. Claim 3 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 3 is also patent ineligible under 35 U.S.C. § 101. Claim 4 Claim 4 further characterizes the mental process recited in claim 1 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 4 recites that “a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits is to be used to predict the one or more characteristics of the one or more first circuits.” The use of such a cost-predict model, when given its broadest reasonable interpretation, can practically be performed in the human mind. Accordingly, claim 4 recites a mental process. Claim 4 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 4 is also patent ineligible under 35 U.S.C. § 101. Claim 5 Claim 5 recites that “the one or more characteristics of the one or more first circuits are to be used to design an adder circuit.” Using characteristics of one or more first circuits to design an adder circuit can practically be performed in the human mind, e.g. with pen and paper. Accordingly, claim 5 recites a mental process. Claim 5 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 5 is also patent ineligible under 35 U.S.C. § 101. Claim 6 Claim 6 recites that “the one or more circuits are to cause first information to be selected for inferencing by the one or more neural networks based, at least in part, on a similarity of the first information to information used to train the one or more neural networks.” However, such selection of first information based on its similarity to other information (i.e. to information used to train one or more neural networks) can practically be performed in the human mind. Accordingly, claim 6 recites a mental process. Claim 6 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 6 is also patent ineligible under 35 U.S.C. § 101. Claim 7 Claim 7 recites that “the one or more circuits are to select one or more third circuits to initialize a search to identify one or more fourth circuits, based, at least in part, on one or more predictions of one or more characteristics of the one or more third circuits.” However, such selection of one or more third circuits can practically be performed in the human mind. Accordingly, claim 7 recites a mental process. Claim 7 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 7 is also patent ineligible under 35 U.S.C. § 101. Claim 8 Regarding “Step 1,” independent claim 8 is to a statutory category, as claim 8 is directed to a method, i.e. a process. Per “Step 2A, Prong One,” the claim recites a mental process. In particular, the recitation in claim 8 of “to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits” can practically be performed in the human mind, and is thus considered a mental process. The analysis thus proceeds to “Step2A, Prong Two” to determine whether the claim recites additional elements that integrate the judicial exception into a practical application. But other than the above-noted mental process, claim 8 merely recites that “one or more neural networks” are used to perform the prediction. This is tantamount to mere instructions to apply the abstract idea on a generic computer and thus fails to integrate the abstract idea into a practical application. See MPEP § 2106.05(f). The analysis thus proceeds to “Step 2B” to determine whether the claim recites additional elements that amount to significantly more than the judicial exception. However, in this case, claim 8 does not. As noted above, claim 8 comprises additional elements reciting that “one or more neural networks” are used to perform the prediction. However, as further noted above, these elements amount to mere instructions to apply the abstract idea on a generic computer. As such, they do not amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Consequently, claim 8 recites an abstract idea but does not include additional elements that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea. As a result, and for the reasons described above, claim 8 is rejected as being patent ineligible under 35 U.S.C. § 101. Claim 9 Claim 9 recites that “at least one neural network of the one or more neural networks is an encoder of a variational autoencoder.” This recitation of an encoder, which is at a high level of generality, is tantamount to mere instructions to apply the judicial exception on a computer. As such, claim 9 fails to integrate the above-noted judicial exception (i.e. mental process) into a practical application or amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Claim 10 Claim 10 recites that “at least one neural network of the one or more neural networks is a decoder of a variational autoencoder.” This recitation of a decoder, which is at a high level of generality, is tantamount to mere instructions to apply the judicial exception on a computer. As such, claim 10 fails to integrate the above-noted judicial exception (i.e. mental process) into a practical application or amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Claim 11 Claim 11 recites that “at least one neural network of the one or more neural networks is a cost-prediction model of a variational autoencoder.” This recitation of a cost-prediction model and variational autoencoder, which is at a high level of generality, is tantamount to mere instructions to apply the judicial exception on a computer. As such, claim 11 fails to integrate the above-noted judicial exception (i.e. mental process) into a practical application or amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Claim 12 Claim 12 further characterizes the mental process recited in claim81 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 12 recites that “the one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits.” The use of such a cost-predict model, when given its broadest reasonable interpretation, can practically be performed in the human mind. Accordingly, claim 12 recites a mental process. Claim 12 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 12 is also patent ineligible under 35 U.S.C. § 101. Claim 13 Claim 13 recites that “the one or more characteristics of the one or more first circuits are to be used to design a digital circuit.” Using characteristics of one or more first circuits to design a circuit can practically be performed in the human mind, e.g. with pen and paper. Accordingly, claim 13 recites a mental process. Claim 13 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 13 is also patent ineligible under 35 U.S.C. § 101. Claim 14 Claim 14 recites that “the one or more characteristics of the one or more first circuits are to be used to simulate a digital circuit.” However, using characteristics of one or more first circuits to simulate a circuit can practically be performed in the human mind. Accordingly, claim 14 recites a mental process. Claim 14 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 14 is also patent ineligible under 35 U.S.C. § 101. Claim 15 Regarding “Step 1,” independent claim 15 is to a statutory category, as claim 15 is directed to a computer system, which can be considered e.g. a machine. Per “Step 2A, Prong One,” the claim recites a mental process. In particular, the recitation in claim 15 of “to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits” can practically be performed in the human mind, and is thus considered a mental process. The analysis thus proceeds to “Step2A, Prong Two” to determine whether the claim recites additional elements that integrate the judicial exception into a practical application. But other than the above-noted mental process, claim 15 merely recites that a “computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, use one or more neural networks” to perform the prediction. This is tantamount to mere instructions to apply the abstract idea on a generic computer and thus fails to integrate the abstract idea into a practical application. See MPEP § 2106.05(f). The analysis thus proceeds to “Step 2B” to determine whether the claim recites additional elements that amount to significantly more than the judicial exception. However, in this case, claim 15 does not. As noted above, claim 15 comprises additional elements reciting that a “computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, use one or more neural networks” to perform the prediction. However, as further noted above, these elements amount to mere instructions to apply the abstract idea on a generic computer. As such, they do not amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Consequently, claim 15 recites an abstract idea but does not include additional elements that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea. As a result, and for the reasons described above, claim 15 is rejected as being patent ineligible under 35 U.S.C. § 101. Claim 16 Claim 16 recites that “one or more of the one or more neural networks are neural networks of a variational autoencoder.” This recitation of one or more neural networks, which is at a high level of generality, is tantamount to mere instructions to apply the judicial exception on a computer. As such, claim 16 fails to integrate the above-noted judicial exception (i.e. mental process) into a practical application or amount to significantly more than the judicial exception. See MPEP § 2106.05(f). Claim 17 Claim 17 recites that “the one or more characteristics of the one or more first circuits are to be used to design a prefix adder circuit.” Using characteristics of one or more first circuits to design a prefix adder circuit can practically be performed in the human mind, e.g. with pen and paper. Accordingly, claim 17 recites a mental process. Claim 17 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 17 is also patent ineligible under 35 U.S.C. § 101. Claim 18 Claim 18 further characterizes the mental process recited in claim 15 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 18 recites that “the one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits.” The use of such a cost-predict model, when given its broadest reasonable interpretation, can practically be performed in the human mind. Accordingly, claim 18 recites a mental process. Claim 18 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 18 is also patent ineligible under 35 U.S.C. § 101. Claim 19 Claim 19 further characterizes the mental process recited in claim 15 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 19 recites that “the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of fabricating a circuit using the one or more characteristics of the one or more first circuits.” Accordingly, claim 19 recites a mental process. Claim 19 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 19 is also patent ineligible under 35 U.S.C. § 101. Claim 20 Claim 20 further characterizes the mental process recited in claim 15 (i.e. “predict one or more characteristics of one or more first circuits…”), as claim 20 recites that “the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of simulating a circuit using the one or more characteristics of the one or more first circuits.” Accordingly, claim 20 recites a mental process. Claim 20 fails to recite any additional elements (i.e. additional to the mental process) that integrate the abstract idea into a practical application or that amount to significantly more than the abstract idea, and as a result, claim 20 is also patent ineligible under 35 U.S.C. § 101. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 8-13, 15, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated U.S. Patent No. 12,585,920 to Kazda et al. (“Kazda”). Regarding claim 1, Kazda describes systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of integrated circuit (IC) designs (see e.g. column 1, lines 40-50). Kazda particularly teaches using one or more neural networks to predict one or more characteristics of one or more first circuits, wherein the prediction is based, at least in part, on one or more characteristics of one or more second circuits (see e.g. column 1, line 51 – column 2, line 3: Kazda teaches using a Variational Autoencoder (VAE) and a regression network to predict optimal design flow parameters for a given integrated circuit (IC) design. Accordingly, Kazda is considered to teach using one or more neural networks, i.e. a VAE and regression network, to predict one or more characteristics of one or more first circuits, e.g. to predict optimal design flow parameters of a first IC design. Kazda further discloses that the VAE and regression network are trained using an historical dataset that comprises features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. Accordingly, Kazda is also considered to teach that the prediction is based, at least in part, on one or more characteristics of one or more second circuits, e.g. on the features and metrics from design construction flows from the historical IC designs used to train the VAE and regression network.). Kazda discloses that such teachings can be implemented via a computing system that comprises memory storing computer code for execution by one or more processors of the system (see e.g. column 5, line 51 – column 6, line 53). The processor of such a computing system implementing the teachings of Kazda is considered a processor like that of claim 1. As per claim 2, Kazda discloses that one or more of the or more neural networks are neural networks of a variational autoencoder (see e.g. column 1, line 51 – column 2, line 3). Accordingly, Kazda further teaches a processor like that of claim 2. As per claim 3, Kazda discloses that one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model (see e.g. column 1, line 51 – column 2, line 3: like noted above, Kazda teaches using a Variational Autoencoder and a regression network to predict one or more characteristics, e.g. optimal design flow parameters, for a given integrated circuit design. Kazda particularly discloses that the regression network predicts one or more target metrics, such as congestion, timing and/or power, which are used to identify the optimal design flow parameters – see e.g. column 3, line 57 – column 4, line 3; column 10, lines 33-44; and column 12, lines 7-19. Such target metrics are indicative of costs, and thus the regression network is considered a “cost-prediction model” like claimed.). Accordingly, Kazda further teaches a processor like that of claim 3. As per claim 4, Kazda teaches that a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits is to be used to predict the one or more characteristics of one or more first circuits (see e.g. column 1, line 51 – column 2, line 3: like noted above, Kazda teaches using a Variational Autoencoder and a regression network to predict one or more characteristics, e.g. optimal design flow parameters, for a given integrated circuit design, i.e. for a first circuit. Kazda particularly discloses that the regression network predicts one or more target metrics, such as congestion, timing and/or power, which are used to identify the optimal design flow parameters – see e.g. column 3, line 57 – column 4, line 3; column 10, lines 33-44; and column 12, lines 7-19. Such target metrics are indicative of costs, and thus the regression network is considered a “cost-prediction model” like claimed. Moreover, like further noted above, Kazda teaches that the regression network is trained using one or more characteristics of one or more second circuits, i.e. features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. The cost-prediction model, i.e. regression network, is thus based, at least in part, on the one or more characteristics of the one or more second circuits and is used to predict the one or more characteristics of one or more first circuits.). Accordingly, Kazda further teaches a processor like that of claim 4. As per claim 6, Kazda further teaches causing first information to be selected for inferencing by the one or more neural networks based, at least in part, on a similarity of the first information to information used to train the one or more neural networks (see e.g. column 3, lines 43-56; column 4, lines 25-34; and column 16, lines 21-27: Kazda teaches selecting points within latent space for inferencing by the one or more neural networks based, at least in part, on a similarity, i.e. closeness, of the point to the points associated with the historical IC designs used to train the neural networks.). Accordingly, Kazda further teaches a processor like that of claim 6. Regarding claim 8, Kazda describes systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of integrated circuit (IC) designs (see e.g. column 1, lines 40-50). Kazda particularly teaches using one or more neural networks to predict one or more characteristics of one or more first circuits, wherein the prediction is based, at least in part, on one or more characteristics of one or more second circuits (see e.g. column 1, line 51 – column 2, line 3: Kazda teaches using a Variational Autoencoder (VAE) and a regression network to predict optimal design flow parameters for a given integrated circuit (IC) design. Accordingly, Kazda is considered to teach using one or more neural networks, i.e. a VAE and regression network, to predict one or more characteristics of one or more first circuits, e.g. to predict optimal design flow parameters of a first IC design. Kazda further discloses that the VAE and regression network are trained using an historical dataset that comprises features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. Accordingly, Kazda is also considered to teach that the prediction is based, at least in part, on one or more characteristics of one or more second circuits, e.g. on the features and metrics from design construction flows from the historical IC designs used to train the VAE and regression network.). Kazda discloses that such teachings can be implemented via a computing system that comprises memory storing computer code for execution by one or more processors of the system (see e.g. column 5, line 51 – column 6, line 53). Kazda thus teaches a computer-implemented method like that of claim 8. As per claim 9, Kazda discloses that at least one neural network of the one or more neural networks is an encoder of a variational autoencoder (see e.g. column 1, line 51 – column 2, line 3; and column 10, lines 57-67). Accordingly, Kazda further teaches a computer-implemented method like that of claim 9. As per claim 10, Kazda discloses that at least one neural network of the one or more neural networks is a decoder of a variational autoencoder (see e.g. column 1, line 51 – column 2, line 3; and column 10, lines 57-67). Accordingly, Kazda further teaches a computer-implemented method like that of claim 10. As per claim 11, Kazda discloses that at least one neural network of the one or more neural networks is a cost-prediction model of a variational autoencoder (see e.g. column 1, line 51 – column 2, line 3: like noted above, Kazda teaches using a Variational Autoencoder and a regression network to predict one or more characteristics, e.g. optimal design flow parameters, for a given integrated circuit design. Kazda particularly discloses that the regression network predicts one or more target metrics, such as congestion, timing and/or power, which are used to identify the optimal design flow parameters – see e.g. column 3, line 57 – column 4, line 3; column 10, lines 33-44; and column 12, lines 7-19. Such target metrics are indicative of costs. Moreover, Kazda discloses that the regression network acts on points in the latent space generated by the autoencoder – see e.g. column 12, lines 20-35; and FIG. 3. The regression network is thus considered a cost-prediction model of the variational autoencoder like claimed.). Accordingly, Kazda further teaches a computer-implemented method like that of claim 11. As per claim 12, Kazda further discloses that the one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits (see e.g. column 1, line 51 – column 2, line 3: like noted above, Kazda teaches using a Variational Autoencoder and a regression network to predict one or more characteristics, e.g. optimal design flow parameters, for a given integrated circuit design, i.e. for a first circuit. Kazda particularly discloses that the regression network predicts one or more target metrics, such as congestion, timing and/or power, which are used to identify the optimal design flow parameters – see e.g. column 3, line 57 – column 4, line 3; column 10, lines 33-44; and column 12, lines 7-19. Such target metrics are considered indicative of costs, and thus the regression network is considered a “cost-prediction model” like claimed. Moreover, like further noted above, Kazda teaches that the regression network is trained using one or more characteristics of one or more second circuits, i.e. features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. The cost-prediction model, i.e. regression network, is thus based, at least in part, on the one or more characteristics of the one or more second circuits and is used to predict the one or more characteristics of one or more first circuits.). Accordingly, Kazda further teaches a computer-implemented method like that of claim 12. As per claim 13, Kazda teaches that the one or more characteristics of the one or more first circuits are to be used to design a digital circuit (see e.g. column 1, line 6 – column 2, line 11: Kazda teaches that the optimal design flow parameters identified via the Variational Autoencoder and regression network are for use in physical synthesis a digital circuit. The one or more characteristics, e.g. the identified optimal design flow parameters, are thus used at least in part in the design of the digital circuit.). Accordingly, Kazda further teaches a computer-implemented method like that of claim 13. Regarding claim 15, Kazda describes systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of integrated circuit (IC) designs (see e.g. column 1, lines 40-50). Kazda particularly teaches using one or more neural networks to predict one or more characteristics of one or more first circuits, wherein the prediction is based, at least in part, on one or more characteristics of one or more second circuits (see e.g. column 1, line 51 – column 2, line 3: Kazda teaches using a Variational Autoencoder (VAE) and a regression network to predict optimal design flow parameters for a given integrated circuit (IC) design. Accordingly, Kazda is considered to teach using one or more neural networks, i.e. a VAE and regression network, to predict one or more characteristics of one or more first circuits, e.g. to predict optimal design flow parameters of a first IC design. Kazda further discloses that the VAE and regression network are trained using an historical dataset that comprises features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. Accordingly, Kazda is also considered to teach that the prediction is based, at least in part, on one or more characteristics of one or more second circuits, e.g. on the features and metrics from design construction flows from the historical IC designs used to train the VAE and regression network.). Kazda discloses that such teachings can be implemented via a computing system that comprises memory storing computer code for execution by one or more processors of the system (see e.g. column 5, line 51 – column 6, line 53). Such a computing system implementing the above-described teachings of Kazda is considered a computer system like that of claim 15. As per claim 16, Kazda discloses that one or more of the or more neural networks are neural networks of a variational autoencoder (see e.g. column 1, line 51 – column 2, line 3). Accordingly, Kazda further teaches a computer system like that of claim 16. As per claim 18, Kazda further discloses that the one or more characteristics of the one or more first circuits are to be predicted based, at least in part, on a cost-prediction model based, at least in part, on the one or more characteristics of the one or more second circuits (see e.g. column 1, line 51 – column 2, line 3: like noted above, Kazda teaches using a Variational Autoencoder and a regression network to predict one or more characteristics, e.g. optimal design flow parameters, for a given integrated circuit design, i.e. for a first circuit. Kazda particularly discloses that the regression network predicts one or more target metrics, such as congestion, timing and/or power, which are used to identify the optimal design flow parameters – see e.g. column 3, line 57 – column 4, line 3; column 10, lines 33-44; and column 12, lines 7-19. Such target metrics are considered indicative of costs, and thus the regression network is considered a “cost-prediction model” like claimed. Moreover, like further noted above, Kazda teaches that the regression network is trained using one or more characteristics of one or more second circuits, i.e. features and metrics from design construction flows from historical IC designs – see e.g. column 3, line 57 – column 4, line 3. The cost-prediction model, i.e. regression network, is thus based, at least in part, on the one or more characteristics of the one or more second circuits and is used to predict the one or more characteristics of one or more first circuits.). Accordingly, Kazda further teaches a computer system like that of claim 18. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over the U.S. Patent to Kazda described above, and also over the article entitled “High-Speed Adder Design Space Exploration via Graph Neural Processes” by Geng et al. (“Geng”) . Regarding claim 5, Kazda teaches a processor like that of claim 1, as is described above, which uses one or more neural networks to predict one or more characteristics of one or more first circuits. Kazda, however, does not explicitly disclose that the one or more characteristics of the one or more first circuits are to be used to design an adder circuit, as is required by claim 5. Geng nevertheless teaches using one or more neural networks (i.e. a variational graph autoencoder and a neural process) to predict one or more characteristics (e.g. metrics such as power, area, and delay) of one or more adder circuits, and wherein the characteristics are used to identify optimal adder circuit designs: Adders are the primary components in the data path logic of a microprocessor, and thus, adder design has been always a critical issue in the very large-scale integration (VLSI) industry. However, it is infeasible for designers to obtain optimal adder architecture by exhaustively running EDA [electronic design automation] flow due to the extremely large design space. Previous arts have proposed the machine learning-based framework to explore the design space. Nevertheless, they fall into suboptimality due to a two-stage flow of the learning process and less efficient nor effective feature representations of prefix adder structures. In this article, we first integrate a variational graph autoencoder and a neural process (NP) into an end-to-end, multibranch framework, which is termed the graph neural process. The former performs automatic feature learning of prefix adder structures, whilst the latter one is designed as an alternative to the Gaussian process. Then, we propose a sequential optimization framework with the graph NP as the surrogate model to explore the Pareto-optimal prefix adder structures with tradeoff among Quality-of-Result (QoR) metrics, such as power, area, and delay. The experimental results show that compared with state-of-the-art methodologies, our frame work can achieve a much better Pareto frontier in multiple QoR metric spaces with fewer design-flow evaluations. (Abstract. Emphasis added.). In this article, we propose an end-to-end deep learning model, graph neural process (GNP), which outputs predictions and uncertainties based on the feature representations automatically learned from adder structures. With GNP as the surrogate model, in this article, we harness a sequential optimization algorithm [17], [18] to perform DSE [design space exploration] in the physical solution space. The visualization of adder DSE is displayed in Fig. 1. Our main contributions are summarized as follows. 1) A variational graph autoencoder (VGAE) is built to extract features from prefix adder structures automatically . 2) A neural process (NP) is exploited as an alternative to the GP to reduce computational complexity. 3) A multibranch, end-to-end surrogate model (i.e., GNP), which incorporates a VGAE and a NP, is proposed. 4) A GNP-based sequential optimization algorithm to explore Pareto-optimal solutions is investigated. 5) The proposed optimization framework with the developed surrogate model uses less labeled data and achieves better Pareto frontiers. (Section I. Introduction. Emphasis added.). During the initialization, the proposed sequential optimization-based DSE framework interacts with EDA tools to obtain the golden QoR metric (area/power/delay) values of a small number of prefix adders, which are randomly sampled from the entire adder design space E. Afterward, the DSE framework starts working iteratively. Our GNP is first calibrated with the initial data. The trained GNP outputs the QoR metric values of the adder designs in design space E with prediction uncertainties. The proposed DSE framework paradigm tries to classify the input adder designs based on the GNP’s outputs into three classes: 1) Pareto-optimal; 2) nonPareto-optimal; and 3) unknown. During iterations, it incrementally selects the most representative adder designs as candidates for EDA flow (including synthesis, placement, and routing tools) evaluation toward a goal of minimizing the size of the unknown set. By harnessing the representative data along with their ground-truth QoR metric values, the GNP is updated. As more and more adder designs being selected, the GNP gets more and more accurate. The whole DSE process is terminated when the number of maximum iterations is reached or the unknown set is empty. … When the classification finishes, a prefix adder design x t s with the longest diagonal of its uncertainty region R t ( x ) is sampled from Pareto-optimal and unknown categories for tool evaluation. The sampling rule can be written in x t s : = a r g m a x y , y ' ∈ R t ( x ) y - y ' 2 . (28) The GNP model calibration and prediction, the classification of prefix adder designs, and adder design incremental sampling perform alternatively in iterations until the stopping criteria (exceeds the maximum iterations or the unknown set is empty) meet. Eventually, the predicted Pareto-optimal adder designs are evaluated by running EDA flow. For a better understanding, we visualize the mathematical principles of the DSE framework in Fig. 7. (Section IV. Proposed DSE Framework. Emphasis added.). Geng thus teaches that the one or more characteristics of the one or more first circuits are used to design an adder circuit. It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Geng before the effective filing date of the claimed invention, to modify the one or more neural networks taught by Kazda such that the one or more characteristics predicted thereby for one or more first circuits can be used to design an adder circuit, as is taught by Geng. It would have been advantageous to one of ordinary skill to utilize such a combination because “adder design has been always a critical issue in the very large-scale integration (VLSI) industry“ (Abstract) and the resulting “methodology is almost automatic from feature extraction to high-quality adder design space exploration” (section VI. Conclusion.). Accordingly, Kazda and Geng are considered to teach, to one of ordinary skill in the art, a processor like that of claim 5. Regarding claim 17, Kazda teaches a computer system like that of claim 15, as is described above, which uses one or more neural networks to predict one or more characteristics of one or more first circuits. Kazda, however, does not explicitly disclose that the one or more characteristics of the one or more first circuits are to be used to design a prefix adder circuit, as is required by claim 17. Nevertheless, as described above (see the rejection for claim 5), Geng teaches using one or more neural networks (i.e. a variational graph autoencoder and a neural process) to predict one or more characteristics (e.g. metrics such as power, area, and delay) of one or more adder circuits, and wherein the characteristics are used to design an adder circuit. Geng particularly teaches that the adder circuit can be a prefix adder circuit (see e.g. section IV. Proposed DSE Framework, which recites: “[w]hen the classification finishes, a prefix adder design x t s with the longest diagonal of its uncertainty region R t ( x ) is sampled from Pareto-optimal and unknown categories for tool evaluation….The GNP model calibration and prediction, the classification of prefix adder designs , and adder design incremental sampling perform alternatively in iterations until the stopping criteria (exceeds the maximum iterations or the unknown set is empty) meet. Eventually, the predicted Pareto-optimal adder designs are evaluated by running EDA flow.”). It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Geng before the effective filing date of the claimed invention, to modify the one or more neural networks taught by Kazda such that the one or more characteristics predicted thereby for one or more first circuits can be used to design an adder circuit, and particularly to design a prefix adder circuit, as is taught by Geng. It would have been advantageous to one of ordinary skill to utilize such a combination because “adder design has been always a critical issue in the very large-scale integration (VLSI) industry“ (Abstract) and the resulting “methodology is almost automatic from feature extraction to high-quality adder design space exploration” (section VI. Conclusion.). Accordingly, Kazda and Geng are considered to teach, to one of ordinary skill in the art, a computer system like that of claim 17 . 07-21-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over the U.S. Patent to Kazda described above, and also over the article entitled “A Hybrid Evolutionary Programming Method for Circuit Optimization” by Damavandi et al. (“Damavandi”) . Regarding claim 7, Kazda teaches a processor like that of claim 1, as is described above, which comprises one or more circuits that use one or more neural networks to predict one or more characteristics of one or more first circuits, wherein the prediction is based, at least in part, on one or more characteristics of one or more second circuits. Kazda further teaches selecting one or more third circuits to initialize a search to identify one or more fourth circuits (see e.g. column 15, line 49 – column 16, line 31: Kazda teaches randomly selecting samples in the latent space to initiate a gradient descent search for locally optimal design parameters. The randomly-selected samples are decoded to generate particular design characteristics and design flow parameters of an IC circuit design – see e.g. column 15, line 63 – column 16, line 7 – and are thus indicative of “one or more third circuits” like claimed, i.e. of an IC circuit design having the particular design characteristics and design flow parameters. Similarly, the locally optimal design parameters are considered indicative of “one or more fourth circuits” like claimed). Kazda, however, does not explicitly disclose that the one or more third circuits are selected based, at least in part, on one or more predictions of one or more characteristics of the one or more third circuits, as is further required by claim 7. Damavandi generally describes a “hybrid evolutionary programming (EP) method…for global optimization of complex circuits.” (Abstract). Damavandi particularly teaches that such a method entails selecting one or more third circuits to initialize a search to identify one or more fourth circuits, based, at least in part, on one or more predictions of one or more characteristics of the one or more third circuits (see e.g. section II. Review of Evolutionary Programming, and section III. Enhancement of Evolutionary Programming Using Cluster Analysis: Damavandi discloses that the hybrid evolutionary programming method comprises performing evolutionary programming and clustering to identify clusters of points within a search space based on predicted characteristics of the points, e.g. based on a fitness value/objective function determined for the points. Damavandi discloses that a gradient-based search is then performed on the point with the best fitness in each cluster to identify an exact minimum – see e.g. section IV. Hybrid EP. Damavandi thus teaches using evolutionary programming and clustering select one or more third points to initialize a search via gradient descent to identify one or more fourth points, wherein the selection is based, at least in part, on one or more predictions of one or more characteristics of the one or more third points. Damavandi discloses that such a hybrid evolutionary programming method can be utilized to identify optimum circuit parameters – see e.g. section V.B Diplexer Synthesis . In such circumstances, the one or more third points within the search space would correspond to one or more third circuits, and the one or more fourth points would correspond to one or more fourth circuits. Damavandi also discloses modifying the algorithm to utilize an initial estimate of the solution: Another issue in hybrid EP is the implication of the initial solution on the performance of algorithm. Generally, random search methods do not use the initial estimate of the solution. However, in many practical cases, such as circuit optimization, a rough estimate of the initial solution may be available. In order to take advantage of this knowledge, the EP algorithm is modified to accept the initial solution. At the beginning of the program, this initial solution will be added to the pool of initial parents. If the initial solution is close to a local solution, a subpopulation will soon form around this local minimum and the clustering algorithm will identify it. This cluster will then be marked as forbidden zone and it will be excluded from the search in the next stages. (Section IV. Hybrid EP. Emphasis added). As applied to optimize circuits, such an initial estimate can alternatively be considered a third circuit that is selected to initialize a search to identify one or more fourth circuits based, at least in part, on one or more predictions of one or more characteristics of the one or more third circuits.). It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Damavandi before the effective filing date of the claimed invention, to modify the processor taught by Kazda so as to select one or more third circuits to initialize a search to identify one or more fourth circuits, based, at least in part, on one or more predictions of one or more characteristics of the one or more third circuits, as is taught by Damavandi. It would have been advantageous to one of ordinary skill to utilize such a combination because gradient-based search alone (i.e. like done by Kazda) “may fail to provide the global solution and can be easily trapped into local minima” (section I. Introduction), whereas the hybrid evolutionary programming method taught by Damavandi (i.e. wherein one or more initial points are selected via an evolutionary program and clustering to initialize a gradient descent search) “can successfully optimize the complete circuit and provide the global solution very efficiently.” (section V.B. Diplexer Synthesis ). Accordingly, Kazda and Damavandi are considered to teach, to one of ordinary skill in the art, a processor like that of claim 7 . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over the U.S. Patent to Kazda described above, and also over the article entitled, “Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design” by Huang et al. (“Huang”) . Regarding claim 14, Kazda teaches a computer-implemented method like that of claim 8, as is described above, which comprise using one or more neural networks to predict one or more characteristics of one or more first circuits. Kazda, however, does not explicitly disclose that the one or more characteristics of the one or more first circuits are to be used to simulate a digital circuit, as is required by claim 14. Similar to Kazda, Huang teaches using one or more neural networks (i.e. a variational autoencoder and performance predictors) to predict one or more characteristics (e.g. hardware design features and performance) of one or more first circuits (e.g. a hardware design) based, at least in part, on one or more characteristics of one or more second circuits (e.g. based on the features and performances of hardware designs used to train the neural networks) (see e.g. section III. B . Latent Space Generation VAE Training and Visualization , and section III.C.2. Predictor-Based GD ). Huang further suggests that the one or more characteristics of the one or more first circuits are used to simulate a digital circuit (see e.g. section III.A. Overview , which recites “[t]o evaluate the performance of different DNNs on a wide range of DNN hardware, we harness CoSA, a constrained optimization-based scheduler [36], to automatically generate high-performance mappings and Timeloop, an accurate latency and energy simulator [1], to estimate the performance of different design points .” Section III.C.2. Predictor-Based GD further recites “…the GD-based DSE flow performs iterative gradient updates on the latent space performance predictor, and only invokes the scheduler and simulator after an optimized latent space design is found with respect to the predictor performance .”). It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Huang before the effective filing date of the claimed invention, to modify the computer-implemented method taught by Kazda so as to further comprise using the one or more characteristics of the one or more first circuits to simulate a digital circuit, as is taught by Huang. It would have been advantageous to one of ordinary skill to utilize such a combination because it would further ensure the predicted performance of the designed circuit, as is evident from Huang (see e.g. section III.C.2. Predictor-Based GD ). Accordingly, Kazda and Huang are considered to teach, to one of ordinary skill in the art, a computer-implemented method like that of claim 14 . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over the U.S. Patent to Kazda described above, and also over the article entitled, “Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs” by Dong et al. (“Dong”) . Regarding claim 19, Kazda teaches a computer system like that of claim 15, as is described above, which uses one or more neural networks to predict one or more characteristics of one or more first circuits. Kazda, however, does not explicitly disclose that the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of fabricating a circuit using the one or more characteristics of the one or more first circuits, as is required by claim 19. Dong nevertheless generally teaches estimating costs of fabricating a circuit, therein the estimated costs can be utilized during the design of the circuit: 3-D integration technology is emerging as an at tractive alternative to increase the transistor count for future chips. The majority of the existing 3-D integrated circuit (IC) research is focused on the performance, power, density, and heterogeneous integration benefits offered by 3-D integration. All such advantages, however, ultimately have to translate into cost evaluation when a design strategy has to be decided. Consequently, system-level cost analysis at early design stages is imperative to decide on whether 3-D integration should be adopted. This paper presents a cost estimation method for 3-D ICs at early design stages and proposes a set of cost models that include wafer cost, 3-D bonding cost, package cost, and cooling cost. The proposed 3-D IC cost estimation method can help designers analyze the cost implication for 3-D ICs during the design space exploration at the early stage, and it enables a cost-driven 3-D IC design flow that can guide the design choice toward a cost-effective direction. Based on the proposed cost estimation method, this paper demonstrates two case studies that explore the cost benefits of 3-D integration for application-specific integrated circuit designs and many-core microprocessor designs style, respectively. Finally, this paper suggests the optimum partitioning strategy for future 3-D IC designs. (Abstract. Emphasis added.). The 3-D IC cost analysis discussed above is conducted before the real design, and all the inputs of the cost model are predicted from early design estimation. However, if the same cost analysis methodology is applied during design time, using the real design data, such as die area, TSV interconnects, and metal interconnects, as the inputs of the cost model, then a cost-driven 3-D IC design flow becomes possible. Fig. 12 shows a proposed cost-driven 3-D IC design flow. The integration of 3-D IC cost models into design flows guides the designer to optimize their 3-D IC design and eventually to manufacture low-cost product. Such a unique and close integration of cost analysis with 3-D EDA design flow has two advantages. First, as we discussed earlier, many design decisions (such as partitioning and placement and routing) can affect cost analysis. Closely coupling cost analysis with 3-D EDA flow can result in more accurate cost estimation. Second, the cost analysis result can drive 3-D EDA tools to carry out a more cost-effective optimization, in addition to considering other design goals (such as performance and power consumption). (Section V. E Cost-Driven Design Flow ). Dong further teaches that the estimated costs are determined using one or more characteristics (e.g. a fabrication process type) of the one or more first circuits (see e.g. section IV. 3-D Cost Model). It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Dong before the effective filing date of the claimed invention, to modify the computer system taught by Kazda such that the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of fabricating a circuit using the one or more characteristics of the one or more first circuits, as is taught by Dong. It would have been advantageous to one of ordinary skill to utilize such a combination because it can result in more cost-effective designs, as is evident from Dong (see e.g. the Abstract). Accordingly, Kazda and Dong are considered to teach, to one of ordinary skill in the art, a computer system like that of claim 19 . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over the U.S. Patent to Kazda described above, and also over the article entitled “DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling” by Mariani et al. (“Mariani”) Regarding claim 20, Kazda teaches a computer system like that of claim 15, as is described above, which uses one or more neural networks to predict one or more characteristics of one or more first circuits. Kazda, however, does not explicitly disclose that the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of simulating a circuit using the one or more characteristics of the one or more first circuits, as is required by claim 20. Mariani nevertheless teaches predicting one or more characteristics of one or more first circuits (e.g. of computing architectures), wherein the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of simulating (i.e. based on predicted simulation times for) a circuit using the one or more characteristics of the one or more first circuits: Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26× to 4× with respect to other parallel state-of-the art DSE techniques. (Abstract. Emphasis added). In [18], we combined the advantages of a parallel computing environment and analytic performance prediction models. We proposed DESPERATE, a prediction-based simulation scheduling technique for parallel design environments that adopts an analytic prediction technique for estimating the simulation run-time with the goal of balancing the workload on the computational nodes . In this paper, we extend [18] by proposing the DESPERATE++ DSE algorithm that adds a configuration quality predictor in an orthogonal way to the previous simulation time prediction model. Given some candidate design configurations, the combination of the two models predict: 1) the quality of these configurations, to focus the exploration effort on the most promising design regions and 2) their simulation times, to fully exploit the parallel environment. Finally, in this paper we demonstrate that, thanks to this new feature, the novel DESPERATE++ approach overcomes the exploration performance of its predecessor by providing a 1.3× speedup. (Section II. Related Works. Emphasis added). It would have been obvious to one of ordinary skill in the art, having the teachings of Kazda and Mariani before the effective filing date of the claimed invention, to modify the computer system taught by Kazda such that the one or more characteristics of the one or more first circuits are based, at least in part, on one or more costs of simulating a circuit using the one or more characteristics of the one or more first circuits, as is taught by Mariani. It would have been advantageous to one of ordinary skill to utilize such a combination because it can more efficiently schedule simulations, as is taught by Mariani (see e.g. section III. Motivating Example). Accordingly, Kazda and Mariani are considered to teach, to one of ordinary skill in the art, a computer system like that of claim 20 . Double Patenting 08-30 AIA A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co. , 151 U.S. 186 (1894); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert , 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. 08-32 AIA Claim 6 is provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 6 of copending Application No. 18/376769 (“reference application 1”) . This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. In particular, claim 6 of the instant application, and by virtue of its dependency from claim 1, requires: A processor comprising: one or more circuits to use one or more neural networks to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits; wherein the one or more circuits are to cause first information to be selected for inferencing by the one or more neural networks based, at least in part, on a similarity of the first information to information used to train the one or more neural networks. Claim 6 of reference application 1, and by virtue of its dependency from claim 1 thereof, requires: A processor comprising: one or more circuits to cause first information to be selected for inferencing by one or more neural networks based, at least in part, on a similarity of the first information to information used to train the one or more neural networks; wherein the one or more circuits are to use the one or more neural networks to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits. As can be seen, claim 6 of the instant application and claim 6 of reference application 1 are identical in scope and thus claim the same invention. 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 8 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of copending Application No. 18/376769 (“reference application 1”). This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. In particular, like in each of claims 1, 8 and 15 of the instant application, claim 6 of reference application 1 recites, “one or more circuits…to use…one or more neural networks to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits.” Claim 6 of reference application 1 further discloses that a processor comprises the one or more circuits. Accordingly, claim 6 of reference application 1 teaches a processor like that of claim 1 of the instant application, and which executes a computer-implemented method like that of claim 8 of the instant application. Such a processor would understandably be connected to memory storing computer-executable instructions. A processor and memory implementing the teachings of claim 6 of reference application 1 forms a computer system like that of claim 15 of the instant application. 08-37 AIA Claim s 1, 8 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of copending Application No. 18/376772 (“reference application 2”) in view of U.S. Patent No. 12,585,920 to Kazda et al. (“Kazda”) . This is a provisional nonstatutory double patenting rejection. In particular, similar to each of claims 1, 8 and 15 of the instant application, claim 6 of reference application 2 recites, “one or more circuits…to use…one or more neural networks to predict one or more characteristics of the one or more second circuits based, at least in part, on one or more characteristics of the one or more second circuits.” Claim 6 of reference application 2 further discloses that a processor comprises the one or more circuits. Accordingly, claim 6 of reference application 2 teaches a processor similar to that of claim 1 of the instant application, and which executes a computer-implemented method similar to that of claim 8 of the instant application. Such a processor would understandably be connected to memory storing computer-executable instructions. A processor and memory implementing the teachings of claim 6 of reference application 2 forms a computer system similar to that of claim 15 of the instant application. Claim 6 of reference application 2, however, does not explicitly recite predicting one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits, as is required by claims 1, 8 and 15 of the instant application. Nevertheless, like described above, Kazda teaches using one or more neural networks to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits (e.g. based on a historical dataset of features and metrics of circuits that is used to train the one or more neural networks) (see e.g. column 1, line 51 – column 2, line 3; and column 3, line 57 – column 4, line 3). It would have been obvious to one of ordinary skill in the art, having the teachings of reference application 2 and Kazda before the effective filing date of the claimed invention, to modify the processor, computer-implemented method and computer system taught by claim 6 of reference application 2, such that the one or more neural networks predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits like taught by Kazda. It would have been advantageous to one of ordinary skill to utilize such a combination because it would enable the one or neural networks to learn from a historical dataset, as is taught by Kazda (see e.g. column 3, line 57 – column 4, line 3). Accordingly, claim 6 of reference application 2 and Kazda are considered to teach, to one of ordinary skill in the art, a processor like that of claim 1, a computer-implemented method like that of claim 8, and a computer system like that of claim 15 of the instant application. Conclusion The prior art made of record on form PTO-892 and not relied upon is considered pertinent to applicant’s disclosure. The applicant is required under 37 C.F.R. §1.111(C) to consider these references fully when responding to this action. In particular, the U.S. Patent Application Publication to Yazdanbakhsh cited therein describes an optimization engine that includes an auto-encoder and one or more regressors and which can be used for optimizing integrated circuit architectures. The U.S. Patent Application Publication to Cummings et al. cited therein describes methods for designing hardware, wherein a machine learning based performance estimator is used to predict the performance of hardware architectural configurations. The article by Touloupas et al. cited therein (“Mixed-Variable Bayesian Optimization for Analog Circuit Sizing through Device Representation Learning”) describes a deep representation learning method for building continuous-valued representations of individual integrated circuit (IC) devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BLAINE T BASOM whose telephone number is (571)272-4044. The examiner can normally be reached Monday-Friday, 9:00 am - 5:30 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Ell can be reached at (571)270-3264. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BTB/ 4/28/2026 /MATTHEW ELL/Supervisory Patent Examiner, Art Unit 2141 Application/Control Number: 18/376,767 Page 2 Art Unit: 2141 Application/Control Number: 18/376,767 Page 3 Art Unit: 2141 Application/Control Number: 18/376,767 Page 4 Art Unit: 2141 Application/Control Number: 18/376,767 Page 5 Art Unit: 2141 Application/Control Number: 18/376,767 Page 6 Art Unit: 2141 Application/Control Number: 18/376,767 Page 7 Art Unit: 2141 Application/Control Number: 18/376,767 Page 8 Art Unit: 2141 Application/Control Number: 18/376,767 Page 9 Art Unit: 2141 Application/Control Number: 18/376,767 Page 10 Art Unit: 2141 Application/Control Number: 18/376,767 Page 11 Art Unit: 2141 Application/Control Number: 18/376,767 Page 12 Art Unit: 2141 Application/Control Number: 18/376,767 Page 13 Art Unit: 2141 Application/Control Number: 18/376,767 Page 14 Art Unit: 2141 Application/Control Number: 18/376,767 Page 15 Art Unit: 2141 Application/Control Number: 18/376,767 Page 16 Art Unit: 2141 Application/Control Number: 18/376,767 Page 17 Art Unit: 2141 Application/Control Number: 18/376,767 Page 18 Art Unit: 2141 Application/Control Number: 18/376,767 Page 19 Art Unit: 2141 Application/Control Number: 18/376,767 Page 20 Art Unit: 2141 Application/Control Number: 18/376,767 Page 21 Art Unit: 2141 Application/Control Number: 18/376,767 Page 22 Art Unit: 2141 Application/Control Number: 18/376,767 Page 23 Art Unit: 2141 Application/Control Number: 18/376,767 Page 24 Art Unit: 2141 Application/Control Number: 18/376,767 Page 25 Art Unit: 2141 Application/Control Number: 18/376,767 Page 26 Art Unit: 2141 Application/Control Number: 18/376,767 Page 27 Art Unit: 2141 Application/Control Number: 18/376,767 Page 28 Art Unit: 2141 Application/Control Number: 18/376,767 Page 29 Art Unit: 2141 Application/Control Number: 18/376,767 Page 30 Art Unit: 2141 Application/Control Number: 18/376,767 Page 31 Art Unit: 2141 Application/Control Number: 18/376,767 Page 32 Art Unit: 2141 Application/Control Number: 18/376,767 Page 33 Art Unit: 2141 Application/Control Number: 18/376,767 Page 34 Art Unit: 2141 Application/Control Number: 18/376,767 Page 35 Art Unit: 2141 Application/Control Number: 18/376,767 Page 36 Art Unit: 2141 Application/Control Number: 18/376,767 Page 37 Art Unit: 2141 Application/Control Number: 18/376,767 Page 38 Art Unit: 2141
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