DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claim 1-17 in the reply filed on 02/23/2026 is acknowledged. The traversal is on the ground(s) that “Group I is generic to the embodiment of Group II. Thus, there is no undue burden on the Examiner to simultaneously examine claims of both Groups I and II.” This is found persuasive because group II claims 13-17 do contain majority of the elements as recited in claim 1 with the exception of the third die which is claimed in a dependent form relying back to claim 1.
The examiner is withdrawing the restriction requirement of claims 13-17 and examine the claims in the action below. Similar examiner response applies to the species restriction as well, therefore the examiner is withdrawing the Species restriction requirement.
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/23/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/05/2024 is being considered by the examiner.
Drawings
The drawings submitted on 10/05/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 6 and 10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Pan et al. (US 20200006186 A1).
Regarding claim 1, Pan discloses a chip package, comprising:
an interconnect routing structure (122); ([0024], Fig. 1)
a first die (114) disposed on a first surface (above) of the interconnect routing structure (122), the first die (114) having a circuitry (130/132) connected to a circuitry (148) of the interconnect routing structure (122); ([0027], Fig. 1)
a second die (116) at least partially disposed over the first die (114), the second die (116) having circuitry (130/132) connected to the circuitry (130/132) of the first die (114); ([0033], Fig. 1) and
a thermal carrier (108) bonded (indirectly) on the second die (116), wherein at least one of the thermal carrier, the first die (114), or the second die (116) includes a plurality of metallic pillars (112) configured to transfer heat (per [0025]), wherein the plurality of metallic pillars (112) are electrically floating (per [0038]). (Fig. 1)
Regarding claim 5, Pan discloses the chip package of claim 1, wherein the first die (114) includes the plurality of metallic pillars (114). (Fig. 1)
Regarding claim 6, Pan discloses the chip package of claim 1, wherein each of the plurality of metallic pillars (112) comprises a single plated column (see Fig. 1).
Regarding claim 10, Pan discloses the chip package of claim 1, wherein the interconnect routing structure (122) is a package substrate (per [0024]).
Claim 13, 16 and 17 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Park (US 20110215457 A1).
Regarding claim 13, Park discloses a chip package, comprising:
an interconnect routing structure (110); (Fig. 1)
a first die (120) disposed on a first surface (above) of the interconnect routing structure (110), the first die (120) having a circuitry (per [0017]) connected to a circuitry (per [0017]) of the interconnect routing structure (110); (Fig. 1)
a second die (124) at least partially disposed over the first die (120), the second die (124) having circuitry (per [0017]) connected to the circuitry (per [0017]) of the first die (120); (Fig. 1)
a third die (128) at least partially disposed over the first die (120) and the second die (124), the third die (128) having a circuitry (per [0017]) connected to the circuitry of the first die (120) and the second die (124);
the thermal carrier (180) having a plurality of metallic pillars (133-138) extending from a top surface of the thermal carrier (180) to a bottom surface of the thermal carrier (180), wherein the plurality of metallic pillars (133-138) are electrically floating. ([018], Fig. 1)
and a thermal carrier (130) mounted (indirectly) on the third die (128).
Regarding claim 16, Park discloses the chip package of claim 13, wherein each of the plurality of metallic pillars (133-138) comprise a single plated column (per [0007]). (Fig. 1)
Regarding claim 17, Park discloses the chip package of claim 16, wherein the plurality of metallic pillars (133-138) comprise copper (per [0007]). (Fig. 1)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 3, 4, 7, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20200006186 A1) in view of Chang (US 20220367406 A1).
Regarding claim 2, Pan discloses the chip package of claim 1, further comprising:
the circuitry (130/132) of the second die (116) connected to the circuitry (148) of the interconnect routing structure (122), (Fig. 1)
Pan does not disclose:
a third die disposed on the first surface of the interconnect routing structure
and the second die is at least partially disposed over the third die.
However, Chang discloses:
a third die (820) disposed on the first surface (above) of the interconnect routing structure (per [0069]), and
the second die (850b) is at least partially disposed over (from below) the third die (820). ([0066], Fig. 8E)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang to have a third die disposed on the first surface of the interconnect routing structure and the second die is at least partially disposed over the third die in order to have “ a large multi-functional device having high performance.” (Chang, [0003])
Regarding claim 3, Pan discloses the chip package of claim 1. Pan does not disclose wherein the thermal carrier is bonded to the second die using a fusion bond, the fusion bond having reduced thickness.
However, Chang discloses:
the thermal carrier (840) is bonded (indirectly) to the second die (850b) using a fusion bond (per [0066]), the fusion bond having reduced thickness (per [0066]). (Fig. 1)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang for the thermal carrier is bonded to the second die using a fusion bond, the fusion bond having reduced thickness because “fusion bonding between a substrate of the semiconductor die and the carrier substrate” can be done “without using of intermediate adhesives.” (Chang, [0062])
Regarding claim 4, Pan discloses the chip package of claim 1. Pan does not disclose further comprising a silicon spacer disposed between the thermal carrier and the first die, wherein the silicon spacer is bonded to the first die using a fusion bond, the fusion bond having reduced thickness.
However, Chang does disclose:
a silicon spacer (858) disposed between the thermal carrier (840) and the first die (850a), wherein the silicon spacer (858) is bonded (from the side) to the first die (850a) using a fusion bond (per [0037]), the fusion bond having reduced thickness (per [0070]). (Fig. 8E)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang to have a silicon spacer disposed between the thermal carrier and the first die, wherein the silicon spacer is bonded to the first die using a fusion bond, the fusion bond having reduced thickness because “fusion bonding between a substrate of the semiconductor die and the carrier substrate” can be done “without using of intermediate adhesives.” (Chang, [0062])
Regarding claim 7, Pan discloses the chip package of claim 1. Pan does not disclose wherein the thermal carrier is bonded to the second die using hybrid bonding.
However, Chang discloses:
the thermal carrier (840) is bonded to the second die (850b) using hybrid bonding (per [0070]). (Fig. 8E)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang for the thermal carrier is bonded to the second die using hybrid bonding so that “the two wafers are bonded at the same time.” (Chang, [0035])
Regarding claim 8, Chang discloses the chip package of claim 7, wherein the second die (850b) includes bond pads (per [0047]/[0070]) for hybrid bonding (per [0070]), and the bond pads are electrically floating. ([0047]/[0070]), Chang)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang for similar reasons as stated above.
Regarding claim 9, Pan discloses the chip package of claim 1. Pan does not disclose wherein the thermal carrier comprises silicon.
However, Chang discloses:
the thermal carrier (840) comprises silicon. ([0064], Fig. 8E)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Chang the thermal carrier comprises silicon since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20200006186 A1) in view of Pancholi et al. (US 20200212011 A1).
Regarding claim 11, Pan discloses the chip package of claim 1. Pan does not disclose further comprising a redistribution layer disposed on a bottom surface of the thermal carrier.
However, Pancholi discloses:
a redistribution layer (108) disposed on a bottom surface of the thermal carrier (124). (Fig. 2H)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Pancholi to have a redistribution layer disposed on a bottom surface of the thermal carrier in order to “redistribute the connections of the interconnect layer 107.” (Pancholi, [0020])
Regarding claim 12, Pancholi discloses the chip package of claim 11, wherein the redistribution layer (108) is hybrid bonded to the second die (105). (Fig. 2H)
It would have been obvious to one skilled in in the art before the effective filing date to combine the teachings of Pan and Pancholi for similar reasons as stated above.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20110215457 A1) in view of Chang (US 20220367406 A1).
Regarding claim 14, Park discloses the chip package of claim 13. Park does not disclose further comprising: a silicon spacer mounted to at least one of the first die and the second die.
However, Chang discloses:
a silicon spacer (858) mounted (from the side) to at least one of the first die (850a) and the second die (850b).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Park and Chang for a silicon spacer mounted to at least one of the first die and the second die in order to “provide mechanical stability to the second plane level when the second plane level does not have sufficient die density.” (Chang, [0070])
Regarding claim 15, Chang discloses the chip package of claim 14, wherein the silicon spacer (858) is mounted to the first die (850a) or the second die (850b) using a fusion bond (per [0035]) having reduced thickness (per [0070]). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Park and Chang for similar reasons as stated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897