DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claims 1, 11, and 17 have been fully considered. Based on the cited prior arts Rubin, Waidhas, Ecton, Hsiung, and Yun and new grounds of rejection from Tsai (US20210313271A1) the claims 1 - 20 are rejected.
Response to Amendment
Applicant’s amendments to the specification has been fully considered and resolve the specification rejections. The specification rejections has been withdrawn.
Applicant’s amendments to claim 3 has been fully considered and resolve the U.S.C. $ 112(b) rejection. The U.S.C. $112(b) rejections to claim 3 has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US20210265275A1; hereinafter Rubin) in view of Tsai et al. (US20210313271A1; hereinafter Tsai).
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Regarding Claim 17 (Amended), Rubin discloses a semiconductor package (multi-chip package structure, [0059]) comprising:
a package substrate (192), FIG. 1E reproduced above, [0059];
a bridge structure (110) stacked on the package substrate (192), FIG. 1E, [0058];
a first molding member (122) surrounding a side surface of the bridge structure (110), (the first insulating layer 122 comprises a mold compound that is formed to encapsulate the chip interconnect bridge 110, FIG. 1E, [0047]);
a first semiconductor chip (140) and a second semiconductor chip (150) each stacked on an upper surface of the first molding member (122) and electrically connected to each other by the bridge structure (110), FIG. 1D, [0051].
wherein the first semiconductor chip (140) and the second semiconductor chip (150) are arranged along a first direction (X direction) parallel to an upper surface of the package substrate (192), FIG. 1E, [0051] and
Rubin does not explicitly disclose “a trace pattern having a trace line extending along and in contact with an upper surface of the bridge structure and an upper surface of the first molding member; a via pattern penetrating through the first molding member and electrically connecting the package substrate and the trace pattern to each other; the trace pattern extends lengthwise in the first direction and is electrically connected to at least one of the first semiconductor chip and the second semiconductor chip.”
In a similar art, Tsai discloses a semiconductor package structure 500, FIG. 5, [0062].
Tsai discloses: a trace pattern (a second redistribution layer 504) having a trace line (metal layers within redistribution later 504, [0020], [0063]) extending along and in contact with an upper surface of the bridge structure (bridge structure 110) and an upper surface of the first molding member (molding material 510), FIG. 5 reproduced above, [0075].
Tsai [0020], [0063] discloses the second redistribution layer may include one or more metal layers disposed in one or more passivation layers. Tsai [0075] discloses the second redistribution layer 504 is in contact with the bridge structure 110 and the molding material 510 may surround the bridge structure 110. Thereby the trace pattern 504 including metal layers extends along and is in contact with an upper surface of the bridge structure 110 and an upper surface of the molding material 510.
a via pattern (conductive pillars 506) penetrating through the first molding member (510) and electrically connecting the package substrate (substrate 102) and the trace pattern (substrate 102 and trace pattern 504 are electrically connected via conductive structures 104, first redistribution layer 502, and conductive pillars 506) to each other, FIG. 5, [0075], [0076]; and
the trace pattern (504) extends lengthwise in the first direction (X direction) and is electrically connected to at least one of the first semiconductor chip (112a) and the second semiconductor chip (112b), FIG. 5, [0076].
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin’s package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 19, The combination of Rubin and Tsai discloses the semiconductor package of claim 17.
Rubin does not explicitly disclose “wherein the semiconductor package is configured to receive a power supply voltage and transfer the power supply voltage to the first semiconductor chip and the second semiconductor chip, respectively, through the package substrate, the via pattern, and the trace pattern.”
Tsai discloses: wherein the semiconductor package (500) is configured to receive a power supply voltage and transfer the power supply voltage to the first semiconductor chip (112a) and the second semiconductor chip (112b), respectively, through the package substrate (102), the via pattern (506), and the trace pattern (504), FIG. 5, [0044], [0076].
Tsai [0044] discloses a plurality of conductive terminals 118 are formed below the substrate 102, and electrically coupled to the wiring structure of the substrate 102, and the conductive terminals 118 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, indicating the terminals 118 provide the package with external electrical connections through which power may be supplied.
Tsai [0076] discloses the first semiconductor component 112a and the second semiconductor component 112b may be electrically coupled to the wiring structure of the substrate 102 through the second redistribution layer 504, the bridge structure 110, the conductive pillars 506, the first redistribution layer 502, and the conductive structures 104.
It would be obvious that Tsai’s semiconductor package (500) is configured to receive external power through conductive terminals 118 of the package substrate 102. The received power would then be routed through conductive structures 104, first redistribution layer 502, via pattern (conductive pillar 506), and trace pattern (504), and delivered to the first and second semiconductor chips (112a and 112b).
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin’s package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 20, The combination of Rubin and Tsai discloses the semiconductor package of claim 17.
Rubin discloses: further comprising a second molding member (170) covering at least a portion of the first semiconductor chip (140) and at least a portion of the second semiconductor chip (150) on the package substrate (192), FIG. 1E, [0053].
Claims 1 – 6, 8-12, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Waidhas et al. (US20220199562A1; hereinafter Waidhas), further in view of Tsai.
Regarding Claim 1, (Amended) Rubin discloses a semiconductor package (multi-chip package structure, FIG. 1E, [0059]) comprising:
a package substrate (192), FIG. 1E, [0059];
a bridge structure (110) stacked on the package substrate (192), FIG. 1E, [0058];
a first molding member (122) on the package substrate (192) and surrounding a side surface of the bridge structure (110), (the first insulating layer 122 comprises a mold compound that is formed to encapsulate the chip interconnect bridge 110, FIG. 1E, [0047]);
a second molding member (170) covering at least a portion of the first semiconductor chip (140) and at least a portion of the second semiconductor chip (150) on the package substrate (192), FIG. 1E, [0053]. Rubin [0053] discloses a molding process is performed to encapsulate the first and second IC chips 140 and 150 in a molding layer 170.
Rubin does not disclose “a first through via penetrating through the first molding member and spaced apart from a first side surface of the bridge structure; a second through via penetrating through the first molding member and spaced apart from a second side surface of the bridge structure; a first semiconductor chip stacked on the trace pattern and the first through via; a second semiconductor chip stacked on the trace pattern and the second through via; a first chip connection terminal electrically connecting the first through via and the first semiconductor chip to each other; a second chip connection terminal electrically connecting the second through via and the second semiconductor chip to each other; a first trace connection terminal electrically connecting the trace pattern and the first semiconductor chip to each other; a second trace connection terminal electrically connecting the trace pattern and the second semiconductor chip to each other.”
In a similar art, Waidhas discloses multi-chip packages with interconnect bridges [0022].
Waidhas discloses:
a first through via (opening 612 with solder ball 613 adjacent to 625A) penetrating through the first molding member (621) and spaced apart from a first side surface of the bridge structure (side of the bridge 627 adjacent to 625A), FIG. 6E, [0069];
a second through via (opening 612 with solder ball 613 adjacent to 625B) penetrating through the first molding member (621) and spaced apart from a second side surface of the bridge structure (side of the bridge 627 adjacent to 625B), FIG. 6E, [0069];
a first chip connection terminal (solder balls 613 with first pads 622 on 625A) electrically connecting the first through via (opening 612 with solder ball 613 adjacent to 625A) and the first semiconductor chip (625A) to each other, FIG. 6F, [0070];
a second chip connection terminal (solder balls 613 with first pads 622 on 625B) electrically connecting the second through via (opening 612 with solder ball 613 adjacent to 625B) and the second semiconductor chip (625B) to each other, FIG. 6F, [0070].
Waidhas discloses that a package as taught improves routing flexibility of the package [0026]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin’s package, in order to provide a structure with improved routing flexibility as disclosed by Waidhas [0026].
The combination of Rubin and Waidhas does not disclose “a trace pattern having a trace line extending along an upper surface of the bridge structure and an upper surface of the first molding member”
In a similar art, Tsai discloses a semiconductor package structure 500, FIG. 5, [0062].
Tsai discloses: a trace pattern (a second redistribution layer 504) having a trace line (metal layers within redistribution later 504, [0020], [0063]) extending along and in contact with an upper surface of the bridge structure (bridge structure 110) and an upper surface of the first molding member (molding material 510), FIG. 5, [0075].
Tsai [0020], [0063] discloses the second redistribution layer may include one or more metal layers disposed in one or more passivation layers. Tsai [0075] discloses the second redistribution layer 504 is in contact with the bridge structure 110 and the molding material 510 may surround the bridge structure 110. Thereby the trace pattern 504 including metal layers extends along and is in contact with an upper surface of the bridge structure 110 and an upper surface of the molding material 510.
a first via pattern (conductive pillars 506) penetrating through the first molding member (510) and electrically connecting the package substrate (substrate 102) and the trace pattern (substrate 102 and trace pattern 504 are electrically connected via conductive structures 104, first redistribution layer 502, and conductive pillars 506) to each other, FIG. 5, [0075], [0076].
The combination of Rubin, Waidhas, and Tsai disclose:
a first semiconductor chip (Rubin: 140) stacked on the trace pattern (Tsai: 504) and the first through via (Waidhas: opening 612 with solder ball 613 adjacent to 625A, FIG. 6E, [0069]);
a second semiconductor chip (Rubin: 150) stacked on the trace pattern (Tsai: 504) and the second through via (Waidhas: opening 612 with solder ball 613 adjacent to 625B, FIG. 6E, [0069]);
a first trace connection terminal (Rubin: 142) electrically connecting the trace pattern (Tsai: 504, FIG. 5, [0076]) and the first semiconductor chip (Rubin: 140, FIG. 1D, [0051]) to each other;
a second trace connection terminal (Rubin: 152) electrically connecting the trace pattern (Tsai: 504, FIG. 5, [0076]) and the second semiconductor chip (Rubin: 150, FIG. 1D, [0051]) to each other; and
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin and Waidhas’ package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 2 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 1.
Rubin discloses: further comprising: a first bridge connection terminal (vertical connects 136 and chip bump connections 144) electrically connecting the bridge structure (110) and the first semiconductor chip (140) to each other, FIG. 1E, [0051]; and
a second bridge connection terminal (vertical connects 136 and chip bump connections 154) electrically connecting the bridge structure (110) and the second semiconductor chip (150) to each other, FIG. 1E, [0051].
Regarding Claim 3 (Amended), The combination of Rubin, Waidhas, and Tsai disclose the semiconductor package of claim 2.
The combination of Rubin, Waidhas, and Tsai discloses: wherein a lateral width of the first trace connection terminal (Rubin:142) and a lateral width of the first bridge connection terminal (Rubin:144 on 136) are each smaller than a lateral width of the first chip connection terminal (Waidhas: solder balls 613 with first pads 622 on 625A).
Waidhas FIG. 1, [0029] discloses on the first base die 125A, the first pads 122 have a first pitch P1 of approximately 55 μm or larger, and the second pads 124 have a second pitch P2 of approximately 20 μm or smaller, indicating the lateral width of the first trace connection terminal (Rubin:142) and a lateral width of the first bridge connection terminal (Rubin:144) may be each smaller than a lateral width of the first chip connection terminal (Waidhas: solder balls 613 with first pads 622 on 625A).
a lateral width of the second trace connection terminal (Rubin: 152) and a lateral width of the second bridge connection terminal (Rubin:154 on 136) are each smaller than a lateral width of the second chip connection terminal (Waidhas: solder balls 613 with first pads 622 on 625B). Waidhas FIG. 1, [0029] discloses on the second base die 125B, the first pads 122 have a third pitch P3 which may be substantially equal to first pitch P1, and the second pads 124 have a fourth pitch P4 which may be substantially equal to second pitch P2, indicating the lateral width of the second trace connection terminal (Rubin:152) and a lateral width of the second bridge connection terminal (Rubin:154) may be each smaller than a lateral width of the second chip connection terminal (Waidhas: solder balls 613 with first pads 622 on 625B).
Waidhas discloses that a package as taught enables high density routing in the bridge structure [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package, in order to enable high density routing in the bridge structure as disclosed by Waidhas [0029].
Regarding Claim 4 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 1.
Rubin discloses: wherein the bridge structure (110) includes a bridge substrate (substrate of bridge die 110) and a bridge wiring layer (stack of signal interconnect and redistribution layers comprising fine pitch signal wires and vertical inter-level vias, e.g., copper wiring and vias) on a front side of the bridge substrate (bridge 110 die), [0045] and
The combination of Rubin, Waidhas, and Tsai discloses: the trace pattern (Tsai: 504) extends along an upper surface of the bridge wiring layer (Rubin: stack of signal interconnect and redistribution layers) and the upper surface of the molding member (Rubin: 122, FIG. 1C, [0049]).
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 5 (Original), The combination of Rubin, Waidhas, and Tsai disclose the semiconductor package of claim 4.
Rubin discloses: wherein the first semiconductor chip (140) includes a first semiconductor substrate (substrate of die 140) and a first wiring layer (wirings connected to 142, 144) on a front side of the first semiconductor substrate (active side of substrate of die 140), FIG.1D, [0051].
the second semiconductor chip (150) includes a second semiconductor substrate (substrate of die 150) and a second wiring layer (wirings connected to 152, 154) on a front side of the second semiconductor substrate (active side of the substrate of die 150), FIG.1D, [0051], and
the front side of the first semiconductor substrate (active side of the substrate of die 140) and the front side of the second semiconductor substrate (active side of the substrate of die 150) each face the front side of the bridge substrate (active side of the substrate of bridge die 110), FIG.1D, [0051].
Regarding Claim 6 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 1.
Rubin discloses: further comprising a second via pattern (124 adjacent to the second side surface of the bridge 110) penetrating through the first molding member (122) and electrically connecting the package substrate (192 via solder bump connections 180) and the metallization 134 to each other, FIG. 1E, [0049], [0059].
wherein the first via pattern (124 adjacent to the first side surface of the bridge 110) is disposed adjacent the first side surface of the bridge structure (110), and
the second via pattern (124 adjacent to the second side surface of the bridge 110) is disposed adjacent the second side surface of the bridge structure (110).
Tsai discloses: further comprising a second via pattern (506) penetrating through the first molding member (510) and electrically connecting the package substrate (102) and the trace pattern (504) to each other, FIG. 5, [0075], [0076].
wherein the first via pattern (506) is disposed adjacent the first side surface of the bridge structure (side surface of 110 towards chip 112a), FIG. 5, [0075], [0076].
the second via pattern (506) is disposed adjacent the second side surface of the bridge structure (side surface of 110 towards chip 112b), FIG. 5, [0075], [0076].
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 8 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 1.
Rubin discloses: further comprising an adhesive film (112) interposed between the package substrate (192) and the bridge structure (110), FIG. 1E, [0043].
Regarding Claim 9 (Original), The combination of Rubin, Waidhas, and Tsai disclose the semiconductor package of claim 1.
Rubin discloses: wherein the first semiconductor chip (140) is an application processor chip or a logic chip (a hardware accelerator device, a multi-core processor device, central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and other types of general purposes processors or work-load optimized processors such as graphics processing units (GPUs), digital signal processors (DSPs), system-on-chip (SoC), and other types of specialized processors or coprocessors that are configured to execute one or more fixed functions, [0054]), and
the second semiconductor chip (150) is a memory chip, (high-bandwidth memory (HBM) dynamic random-access memory (DRAM), memory device, [0054]).
Regarding Claim 10 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 9.
Rubin discloses: wherein the second semiconductor chip (150) includes a high bandwidth memory (HBM), (high-bandwidth memory (HBM) dynamic random-access memory (DRAM), [0054]).
Regarding Claim 11 (Amended), Rubin discloses a semiconductor package (multi-chip package structure, FIG. 1E, [0059]) comprising:
a package substrate (192), FIG. 1E, [0059];
a bridge structure (110) stacked on the package substrate (192), FIG. 1E, [0058];
a first molding member (122) on the package substrate (192) and surrounding a side surface of the bridge structure (110), (the first insulating layer 122 comprises a mold compound that is formed to encapsulate the chip interconnect bridge 110, FIG. 1E, [0047]);
a first semiconductor chip (140) and a second semiconductor chip (150) each stacked on an upper surface of the first molding member (122) and electrically connected to each other by the bridge structure (110), FIG. 1D, [0051];
Rubin discloses electrically connecting the package substrate (192) and the first semiconductor chip (140) to each other and electrically connecting the package substrate (192) and the second semiconductor chip (150) to each other, FIG. 1E, [0059]; but does not disclose “a first through via penetrating through the first molding member and electrically connecting the package substrate and the first semiconductor chip to each other; a second through via penetrating through the first molding member and electrically connecting the package substrate and the first semiconductor chip to each other.”
In a similar art, Waidhas discloses multi-chip packages with interconnect bridges [0022].
The combination of Rubin and Waidhas disclose:
a first through via penetrating through the first molding member (Waidhas: opening 612 with solder ball 613 adjacent to 625A penetrating 621, FIG. 6E, [0069]) and electrically connecting the package substrate and the first semiconductor chip (Rubin: electrically connecting package substrate 192 and chip 140, FIG. 1E, [0059]) to each other;
a second through via penetrating through the first molding member (Waidhas: opening 612 with solder ball 613 adjacent to 625B penetrating 621, FIG. 6E, [0069]) and electrically connecting the package substrate and the second semiconductor chip (Rubin: electrically connecting package substrate 192 and chip 150, FIG. 1E, [0059]) to each other.
Waidhas discloses that a package as taught improves routing flexibility of the package [0026]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin’s package, in order to provide a structure with improved routing flexibility as disclosed by Waidhas [0026].
The combination of Rubin and Waidhas does not disclose “a trace pattern having a trace line extending along and in contact with an upper surface of the bridge structure and an upper surface of the first molding member”
In a similar art, Tsai discloses a semiconductor package structure 500, FIG. 5, [0062].
Tsai discloses: a trace pattern (a second redistribution layer 504) having a trace line (metal layers within redistribution later 504, [0020], [0063]) extending along and in contact with an upper surface of the bridge structure (bridge structure 110) and an upper surface of the first molding member (molding material 510), FIG. 5, [0075].
Tsai [0020], [0063] discloses the second redistribution layer may include one or more metal layers disposed in one or more passivation layers. Tsai [0075] discloses the second redistribution layer 504 is in contact with the bridge structure 110 and the molding material 510 may surround the bridge structure 110. Thereby the trace pattern 504 including metal layers extends along and is in contact with an upper surface of the bridge structure 110 and an upper surface of the molding material 510.
a via pattern (506) penetrating through the first molding member (510) and electrically connecting the package substrate (102) and the trace pattern (504) to each other, FIG. 5, [0075], [0076];
The combination of Rubin, Waidhas, and Tsai discloses:
a first trace connection terminal (Rubin: 142) electrically connecting the trace pattern (Tsai: 504) and the first semiconductor chip (Rubin 140, FIG. 1D, [0051]) to each other;
a second trace connection terminal (Rubin: 152) electrically connecting the trace pattern (Tsai: 504) and the second semiconductor chip (Rubin: 150, FIG. 1D, [0051]) to each other.
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin and Waidhas’ package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 12 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 11.
Rubin does not explicitly disclose “wherein the semiconductor package is configured to receive a power supply voltage and transfer the power supply voltage to the first semiconductor chip and the second semiconductor chip, respectively, through the package substrate, the via pattern, and the trace pattern.”
Tsai discloses: wherein the semiconductor package (500) is configured to receive a power supply voltage and transfer the power supply voltage to the first semiconductor chip (112a) and the second semiconductor chip (112b), respectively, through the package substrate (102), the via pattern (506), and the trace pattern (504), FIG. 5, [0044], [0076].
Tsai [0044] discloses a plurality of conductive terminals 118 are formed below the substrate 102, and electrically coupled to the wiring structure of the substrate 102, and the conductive terminals 118 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, indicating the terminals 118 provide the package with external electrical connections through which power may be supplied.
Tsai [0076] discloses the first semiconductor component 112a and the second semiconductor component 112b may be electrically coupled to the wiring structure of the substrate 102 through the second redistribution layer 504, the bridge structure 110, the conductive pillars 506, the first redistribution layer 502, and the conductive structures 104.
It would be obvious that Tsai’s semiconductor package (500) is configured to receive external power through conductive terminals 118 of the package substrate 102. The received power would then be routed through conductive structures 104, first redistribution layer 502, via pattern (conductive pillar 506), and trace pattern (504), and delivered to the first and second semiconductor chips (112a and 112b).
Tsai discloses that a package as taught minimizes signal path and increases processing speed [0082]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package, in order to provide a package with improved processing speed as disclosed by Tsai [0082].
Regarding Claim 14 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 11.
Rubin discloses: exposing an upper surface of the package substrate (Rubin: exposing the upper surface of the substrate 192 through solder bumps 180, FIG. 1E, [0059]); but does not disclose “wherein the first molding member includes a plurality of mold trenches exposing an upper surface of the package substrate, and each of the first through via and the second through via are disposed in a respective mold trench of the plurality of mold trenches and are connected to the package substrate.”
The combination of Rubin, Waidhas, and Tsai discloses:
wherein the first molding member (Rubin:122) includes a plurality of mold trenches (Waidhas: openings 612, FIG. 6E, [0069]) exposing an upper surface of the package substrate (Rubin: exposing the upper surface of the substrate 192 through solder bumps 180, FIG. 1E, [0059]), and
each of the first through via (Waidhas: opening 612 with solder ball 613 adjacent to 625A) and the second through via (Waidhas: opening 612 with solder ball 613 adjacent to 625B) are disposed in a respective mold trench of the plurality of mold trenches (Waidhas: opening 612 of the plurality of openings 612, FIG. 6E, [0069]) and are connected to the package substrate (Rubin: 192).
Waidhas discloses that a package as taught eliminates warpage and planarity issues during assembly [0024]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package, in order to eliminate warpage and planarity issues during assembly as disclosed by Waidhas [0024].
Regarding Claim 16 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 11.
Rubin discloses: further comprising a second molding member (170) covering at least a portion of the first semiconductor chip (140) and at least a portion of the second semiconductor chip (150) on the package substrate (192), FIG. 1E, [0053]. Rubin [0053] discloses a molding process is performed to encapsulate the first and second IC chips 140 and 150 in a molding layer 170.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Tsai, further in view of Yun (KR100813624B1; hereinafter Yun).
Regarding Claim 18 (Original), The combination of Rubin and Tsai discloses the semiconductor package of claim 17.
The combination of Rubin and Tsai does not disclose “wherein the trace pattern is formed from conductive ink.”
In a similar art, Yun discloses semiconductor package and a method of manufacturing the same [Page 2, Line 13].
The combination of Rubin, Tsai, and Yun discloses: wherein the trace pattern (Tsai: 504) is formed from conductive ink [Yun: page 7, line 17].
Yun [page 7, line 17] discloses the first wiring 140 may be formed by spraying a conductive ink onto the upper surface 130c of the first insulating layer 130, indicating the trace pattern (Tsai: 504) may be formed from conductive ink.
Yun discloses that a structure as taught reduces the thickness of the package [page 7, line 25]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin and Tsai’s package, in order to provide a structure with reduced thickness as disclosed by Yun [page 7, line 25].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Waidhas, further in view of Tsai, still further in view of Hsiung et al. (US20190181092A1; hereinafter Hsiung).
Regarding Claim 7 (Amended), The combination of Rubin, Waidhas, and Tsai disclose the semiconductor package of claim 6.
The combination of Rubin, Waidhas, and Tsai does not disclose “wherein the first via pattern is closer to the bridge structure than the first through via is to the bridge structure, and the second via pattern is closer to the bridge structure than the second through via is to the bridge structure.”
In a similar art, Hsiung discloses a package structure 400D with bridge die 310, FIG. 4D, [0025].
Hsiung FIG. 4D, [0025] discloses the semiconductor dies 318 and 320 are coupled to the bridge die 310 via the electrical interconnects 312 and 314 and at least one through mold via 406 is placed in the first mold layer 316. The FIG. 4D discloses the electrical interconnects 312 and 314 are closer to the bridge die 310 than the through mold via 406.
The combination of Rubin, Waidhas, Tsai, and Hsiung discloses:
wherein the first via pattern (Rubin: 124 adjacent to the first side surface of the bridge 110) is closer to the bridge structure (Rubin:110) than the first through via (Waidhas: opening 612 with solder ball 613 adjacent to die 625A) is to the bridge structure (Rubin: 110), Hsiung: FIG. 4D, [0025].
Hsiung FIG. 4D discloses electrical interconnects are closer to the bridge die than the through mold via, indicating the first via pattern (Rubin: 124 adjacent to the first side surface of the bridge 110) may be closer to the bridge structure (Rubin:110) than the first through via (Waidhas: opening 612 with solder ball 613 adjacent to die 625A).
the second via pattern (Rubin: 124 adjacent to the second side surface of the bridge 110) is closer to the bridge structure (Rubin:110) than the second through via (Waidhas: opening 612 with solder ball 613 adjacent to die 625B) is to the bridge structure (Rubin:110), Hsiung: FIG. 4D, [0025].
Hsiung FIG. 4D discloses electrical interconnects are closer to the bridge die than the through mold via, indicating the second via pattern (Rubin: 124 adjacent to the second side surface of the bridge 110) may be closer to the bridge structure (Rubin:110) than the second through via (Waidhas: opening 612 with solder ball 613 adjacent to die 625B).
Hsiung discloses that a structure as taught enables fine pitch routing and improves manufacturability [0016]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin, Waidhas, and Tsai’s package, in order to enable fine-pitch routing and improve manufacturability as disclosed by Hsiung [0016].
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Waidhas, further in view of Tsai, still further in view of Ecton et al. (US20190304912A1; hereinafter Ecton).
Regarding Claim 13 (Original), The combination of Rubin, Waidhas, and Tsai disclose the semiconductor package of claim 11.
The combination of Rubin, Waidhas, and Tsai does not disclose “wherein a width of the via pattern decreases as a distance from the package substrate decreases.”
In a similar art, Ecton discloses a semiconductor package structure 100 with interconnect bridge 100 [0027].
The combination of Rubin, Waidhas, Tsai, and Ecton discloses: wherein a width of the via pattern (Rubin: 124) decreases as a distance from the package substrate (Rubin: 192) decreases, (Ecton: FIG. 1E, [0038]).
Ecton [0038] discloses the interconnect vias 118 may comprise a tapered profile resembling a “V” shape, the top portion having a greater lateral width than a lateral width of a bottom portion of the via 118, indicating the via pattern (Rubin:124) decreases as a distance from the package substrate (Rubin:192) decreases.
Ecton discloses that a structure as taught improves lithographic alignment and manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin, Waidhas, and Tsai’s package, in order to improve lithographic alignment and manufacturability as disclosed by Ecton [0050].
Regarding Claim 15 (Original), The combination of Rubin, Waidhas, and Tsai discloses the semiconductor package of claim 14.
The combination of Rubin, Waidhas, and Tsai does not disclose “wherein a width of each of the plurality of mold trenches decreases as a distance from the package substrate decreases.”
The combination of Rubin, Waidhas, Tsai, and Ecton discloses: wherein a width of each of the plurality of mold trenches (Waidhas: openings 612, FIG. 6E, [0069]) decreases as a distance from the package substrate (Rubin: 192) decreases, (Ecton: FIG. 1E, [0038]).
Ecton [0038] discloses the interconnect vias 118 may comprise a tapered profile resembling a “V” shape, the top portion having a greater lateral width than a lateral width of a bottom portion of the via 118, indicating the plurality of mold trenches (Waidhas: openings 612) decreases as a distance from the package substrate (Rubin:192) decreases.
Ecton discloses that a structure as taught improves lithographic alignment and manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Rubin, Waidhas, and Tsai’ package, in order to improve lithographic alignment and manufacturability as disclosed by Ecton [0050].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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