DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15, 18-20 in the reply filed on 04/14/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negate[0014 of Siao]d by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smeys(USPGPUB DOCUMENT: 2016/0362293, hereinafter Smeys) in view of Siao (USPGPUB DOCUMENT: 2024/0258387, hereinafter Siao).
Re claim 1 Smeys discloses a semiconductor structure comprising: an upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140); a frontside interconnect layer(132/134/132’/134’) above, and interconnected with, the upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140), the frontside interconnect layer(132/134/132’/134’), the frontside interconnect layer(132/134/132’/134’) including at least three frontside interconnect layer(132/134/132’/134’) metal levels; a lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140); a backside interconnect layer(132/134/132’/134’) below, and interconnected with, the lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140), the backside interconnect layer(132/134/132’/134’), the backside interconnect layer(132/134/132’/134’) including at least three backside interconnect layer(132/134/132’/134’) metal levels;
Smeys does not discloses a semiconductor structure comprising: an (CMOS) transistor layer(120/140) having a plurality of upper-level N-type field effect transistors and a plurality of upper-level P-type field effect transistors; the frontside interconnect layer(132/134/132’/134’) including frontside power rails and frontside signal wiring, the backside interconnect layer(132/134/132’/134’) including backside power rails and backside signal wiring, the backside interconnect layer(132/134/132’/134’) including at least three backside interconnect layer(132/134/132’/134’) metal levels; and at least one conductive interconnection between a third or higher of the at least three frontside interconnect layer(132/134/132’/134’) metal levels and a third or lower of the at least three backside interconnect layer(132/134/132’/134’) metal levels, the at least one conductive interconnection being located at a peripheral region of the semiconductor structure.
Siao discloses a semiconductor structure comprising: an (CMOS) transistor layer having a plurality of upper-level N-type field effect transistors and a plurality of upper-level P-type field effect transistors[0013]; the frontside interconnect layer(132/134/132’/134’) including frontside power rails and frontside signal wiring, the backside interconnect layerincluding backside power rails[0088] and backside signal wiring, the backside interconnect layer including at least three backside interconnect layer(within 170/200) metal levels; and at least one conductive interconnection between a third or higher of the at least three frontside interconnect layer(within 170/200) metal levels and a third or lower of the at least three backside interconnect layer(within 170/200) metal levels, the at least one conductive interconnection being located at a peripheral region of the semiconductor structure[0053].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Saio to the teachings of Smeys in order to improve the integration density of various electronic components [0003, Saio].
Re claim 2 Smeys and Siao disclose the semiconductor structure of Claim 1, further comprising an intermediate dielectric region separating the upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) and the lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140).
Re claim 3 Smeys and Siao disclose the semiconductor structure of Claim 2, further comprising a substrate wafer outward of the frontside interconnect layer(132/134/132’/134’).
Re claim 4 Smeys and Siao disclose the semiconductor structure of Claim 2, further comprising a backside gate[0014 of Siao] cap interposed between high-K metal gate[0014 of Siao] structures of at least some of the lower-level N-type field effect transistors and the backside interconnect layer(132/134/132’/134’).
Re claim 5 Smeys and Siao disclose the semiconductor structure of Claim 4, further comprising a shallow trench isolation region located between the plurality of lower-level N-type field effect transistors and the plurality of lower-level P-type field effect transistors[0013 of Siao] and the backside interconnect layer(132/134/132’/134’).
Re claim 6 Smeys and Siao disclose the semiconductor structure of Claim 5, further comprising back side gate[0014 of Siao] spacers isolating the backside gate[0014 of Siao] cap from the shallow trench isolation region.
Re claim 7 Smeys and Siao disclose the semiconductor structure of Claim 6, wherein the high-K metal gate[0014 of Siao] structures of the at least some of the lower-level N-type field effect transistors include a region between the back side gate[0014 of Siao] spacers that extends inward below an outer surface of the shallow trench isolation region, inward of at least one channel region of the at least some of the lower-level N-type field effect transistors.
Re claim 8 Smeys and Siao disclose the semiconductor structure of Claim 1, wherein the plurality of upper-level N-type field effect transistors and the plurality of upper-level P-type field effect transistors[0013 of Siao] each have upper field effect transistor high-K metal gate[0014 of Siao] structures defined by upper gate[0014 of Siao] dielectric cuts and the plurality of lower-level N-type field effect transistors and the plurality of lower-level P-type field effect transistors[0013 of Siao] each have lower field effect transistor high-K metal gate[0014 of Siao] structures defined by lower gate[0014 of Siao] dielectric cuts.
Re claim 9 Smeys and Siao disclose the semiconductor structure of Claim 8, wherein metal portions of the upper field effect transistor high-K metal gate[0014 of Siao] structures contact the upper gate[0014 of Siao] dielectric cuts and metal potions of the lower field effect transistor high-K metal gate[0014 of Siao] structures contact the lower gate[0014 of Siao] dielectric cuts.
Re claim 10 Smeys and Siao disclose the semiconductor structure of Claim 8, wherein high-K dielectric portions of the upper field effect transistor high-K metal gate[0014 of Siao] structures contact the intermediate dielectric region and the metal potions of the lower field effect transistor high-K metal gate[0014 of Siao] structures contact the intermediate dielectric region.
Re claim 11 Smeys and Siao disclose the semiconductor structure of Claim 1, wherein:the frontside power rails and the frontside signal wiring are included in at least a first of the at least three frontside interconnect layer(132/134/132’/134’) metal levels; and the backside power rails and the backside signal wiring are included in at least a first of the at least three backside interconnect layer(132/134/132’/134’) metal levels.
Re claim 12 Smeys and Siao disclose the semiconductor structure of Claim 11, wherein the at least one conductive interconnection comprises a deep via contact[0124 of Siao].
Re claim 13 Smeys and Siao disclose the semiconductor structure of Claim 12, wherein at least one terminal of the upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) is electrically interconnected to at least one terminal of the lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) through the deep via contact[0124 of Siao], the third or higher of the at least three frontside interconnect layer(132/134/132’/134’) metal levels and the third or lower of the at least three backside interconnect layer(132/134/132’/134’) metal levels.
Re claim 14 Smeys and Siao disclose the semiconductor structure of Claim 1, wherein at least one transistor of one of N-type and P-type, selected from the plurality of upper-level N-type field effect transistors and the plurality of upper-level P-type field effect transistors[0013 of Siao], has a different threshold voltage than at least one other transistor of the one of N-type and P-type, selected from the plurality of upper-level N- type field effect transistors and the plurality of upper-level P-type field effect transistors[0013 of Siao].
Re claim 15 Smeys and Siao disclose the semiconductor structure of Claim 1, wherein at least one transistor of one of N-type and P-type, selected from the plurality of lower-level N-type field effect transistors and the plurality of lower-level P-type field effect transistors[0013 of Siao], has a different threshold voltage than at least one other transistor of the one of N-type and P-type, selected from the plurality of lower-level N- type field effect transistors and the plurality of lower-level P-type field effect transistors[0013 of Siao].
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smeys(USPGPUB DOCUMENT: 2016/0362293, hereinafter Smeys) in view of Siao (USPGPUB DOCUMENT: 2024/0258387, hereinafter Siao) and Andry (USPGPUB DOCUMENT: 2012/0086100, hereinafter Andry).
Re claim 18 Smeys discloses an upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140); a frontside interconnect layer(132/134/132’/134’) above, and interconnected with, the upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140), the frontside interconnect layer(132/134/132’/134’), the frontside interconnect layer(132/134/132’/134’) including at least three frontside interconnect layer(132/134/132’/134’) metal levels;a lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140); a backside interconnect layer(132/134/132’/134’) below, and interconnected with, the lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140), the backside interconnect layer(132/134/132’/134’), the backside interconnect layer(132/134/132’/134’) including at least three backside interconnect layer(132/134/132’/134’) metal levels; and at least one conductive interconnection between a third or higher of the at least three frontside interconnect layer(132/134/132’/134’) metal levels and a third or lower of the at least three backside interconnect layer(132/134/132’/134’) metal levels.
Smeys does not discloses a hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor structure, wherein the HDL design structure comprises:an upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) having a plurality of upper-level N-type field effect transistors and a plurality of upper-level P-type field effect transistors;, the frontside interconnect layer(132/134/132’/134’) including frontside power rails and frontside signal wiring, a lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) having a plurality of lower-level N-type field effect transistors and a plurality of lower-level P-type field effect transistors; the backside interconnect layer(132/134/132’/134’) including backside power rails and backside signal wiring, and at least one conductive interconnection between a third or higher of the at least three frontside interconnect layer(132/134/132’/134’) metal levels and a third or lower of the at least three backside interconnect layer(132/134/132’/134’) metal levels, the at least one conductive interconnection being located at a peripheral region of the semiconductor structure.
Siao discloses a structure comprises:an upper-level complementary metal oxide semiconductor (CMOS) transistor layer having a plurality of upper-level N-type field effect transistors and a plurality of upper-level P-type field effect transistors[0013];, the frontside interconnect layer including frontside power rails and frontside signal wiring[0088], a lower-level complementary metal oxide semiconductor (CMOS) transistor layer having a plurality of lower-level N-type field effect transistors and a plurality of lower-level P-type field effect transistors[0013]; the backside interconnect layer including backside power rails and backside signal wiring[0088], and at least one conductive interconnection between a third or higher of the at least three frontside interconnect layer metal levels and a third or lower of the at least three backside interconnect layer metal levels, the at least one conductive interconnection being located at a peripheral region of the semiconductor structure[0053].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Saio to the teachings of Smeys in order to improve the integration density of various electronic components [0003, Saio].
Smeys and Siao do not discloses a hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor structure,
Andry discloses a hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor structure, [0007]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Andry to the teachings of Smeys in order to considerably reduces costs and complexities of building high performance CMOS structures [0013, Andry].
Re claim 19 Smeys and Siao and Andry disclose the hardware description language (HDL) design structure of Claim 18, wherein the HDL design structure further comprises an intermediate dielectric region separating the upper-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140) and the lower-level complementary metal oxide semiconductor (CMOS) transistor layer(120/140).
Re claim 20 Smeys and Siao and Andry disclose the hardware description language (HDL) design structure of Claim 19, wherein the HDL design structure further comprises a substrate wafer outward of the frontside interconnect layer(132/134/132’/134’).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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