DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 1 (Fig. 1, claims 1-18) in the reply filed on 6/23/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 7-8, 11, 13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tochibayashi et al. (US 20170263651).
Regarding claim 1, Tochibayashi teaches, in Fig. 2B, a semiconductor device ([0126]), comprising:
a first insulation layer (401, [0115]) disposed on a substrate (400, [0126]);
a lower gate pattern (310c/311c, [0126], [0132]) disposed on the first insulation layer (401);
a second insulation layer (301, [0115]) covering at least a portion of the lower gate pattern (310c/311c);
a first lower gate insulation layer (402 excluding its top layer; [0143], 402 can be stacked-layered) disposed on the lower gate pattern (310c/311c) and the second insulation layer (301);
a source pattern and a drain pattern (416b1 and 416b2, [0128]) disposed on the first lower gate insulation layer (402 excluding its top layer), wherein the source pattern and the drain pattern are spaced apart from each other to include a trench (filled by 406_3b) facing the lower gate pattern (310c/311c);
an upper gate insulation layer (412b, [0127]) disposed on the oxide semiconductor layer (406_3b); and
an upper gate pattern (404b, [0127]) disposed on the upper gate insulation layer (412b) and filling the trench.
Regarding claim 5, Tochibayashi further teaches an etch stop layer (top layer of 402; [0143], 402 can be stacked-layered; and [0293], the top layer of 402 can act as an etch stop layer) disposed on the first lower gate insulation layer (402 excluding its top layer).
Regarding claim 7, Tochibayashi further teaches that the oxide semiconductor layer (406_3b) is formed on sidewalls and upper surfaces of the source and drain patterns (416b1 and 416b2), wherein the oxide semiconductor layer (406_3b) is formed in the trench such that it is formed on an upper surface of the etch stop layer (top layer of 402).
Regarding claim 8, Tochibayashi further teaches that the oxide semiconductor layer (406_3b) includes IGZO, IGO, In203, ZnO, Ga2O3, IGTO, IZO, or ITZO ([0154]-[0156]).
Regarding claim 11, Tochibayashi further teaches a protective insulation layer (417b1/417b2, [0147]) disposed on the oxide semiconductor layer (406_3b) to prevent diffusion of hydrogen ions ([0129]).
Regarding claim 13, Tochibayashi teaches, in Fig. 2B, a semiconductor device ([0126]), comprising:
a first insulation layer (401, [0115]) disposed on a substrate (400, [0126]);
a lower gate pattern (310c/311c, [0126], [0132]) disposed on the first insulation layer (401);
a second insulation layer (301, [0115]) covering sidewalls of the lower gate pattern (310c/311c);
a first lower gate insulation layer (402 excluding its top layer; [0143], 402 can be stacked-layered) disposed on the lower gate pattern (310c/311c) and the second insulation layer (301);
an etch stop layer (top layer of 402; [0143], 402 can be stacked-layered; and [0293], the top layer of 402 can act as an etch stop layer) covering the first lower gate insulation layer (402 excluding its top layer);
pattern structures disposed on the etch stop layer (top layer of 402), wherein each of the pattern structures includes a third insulation layer pattern (417b1 and 417b2, [0147]) and a conductive layer pattern (416b1 and 416b2, [0128]) stacked on each other, and the pattern structures are spaced apart from each other to include a trench (filled by 406_3b) overlapping the lower gate pattern;
an oxide semiconductor layer (406_3b, [0126], [0153]) formed along surfaces of the pattern structures and an upper surface of the etch stop layer (top layer of 402) in the trench;
an upper gate insulation layer (412b, [0127]) disposed on the oxide semiconductor layer (406_3b); and
an upper gate pattern (404b, [0127]) disposed on the upper gate insulation layer (412b) and filling the trench.
Regarding claim 15, Tochibayashi further teaches that the third insulation layer pattern (417b1/417b2) includes an insulation material having a dielectric constant lower than a dielectric constant of the etch stop layer (top layer of 402) ([0147], 417b1/417b2 can have aluminum oxide which has a dielectric constant of around 9-10; [0143]-[0144], top layer of 402 can have hafnium oxide which has a dielectric constant of around 20-25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tochibayashi et al. (US 20170263651) in view of Yamazaki et al. (US 20170373192), cited by Applicant in the Information Disclosure Statement filed on 6/10/2024.
Regarding claim 2, Tochibayashi teaches the limitations of claim 1. Tochibayashi further teaches that each of the source pattern and the drain pattern (416b1 and 416b2) includes a metal ([0148])
Tochibayashi does not teach that each of the source pattern and the drain pattern can be etched by an etching process.
In a similar field of endeavor, Yamazaki teaches that each of the source pattern and the drain pattern (416a1 and 416a2, [0097]) can be etched by an etching process ([0259]), in order to form the source and drain pattern into a desired shape ([0254]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the etched source and drain pattern of Yamazaki, in order to form the source and drain pattern into a desired shape ([0254]).
Regarding claim 3, Tochibayashi in view of Yamazaki teaches the limitations of claim 2. Yamazaki further teaches that each of the source pattern and the drain pattern (416a1 and 416a2) includes at least one of molybdenum, tungsten, titanium, or tantalum nitride ([0138]-[0139]).
Regarding claim 14, Tochibayashi teaches the limitations of claim 13. Tochibayashi further teaches that the conductive layer pattern includes a source pattern and a drain pattern (416b1 and 416b2, [0128]), and that each of the source pattern and the drain pattern (416b1 and 416b2) includes a metal ([0148]).
Tochibayashi does not teach that each of the source pattern and the drain pattern can be etched by an etching process.
In a similar field of endeavor, Yamazaki teaches that each of the source pattern and the drain pattern (416a1 and 416a2, [0097]) can be etched by an etching process ([0259]), in order to form the source and drain pattern into a desired shape ([0254]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the etched source and drain pattern of Yamazaki, in order to form the source and drain pattern into a desired shape ([0254]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tochibayashi et al. (US 20170263651) in view of Ji et al. (KR 20220000153 A, citations made hereinafter to the attached English machine translation), cited by Applicant in the Information Disclosure Statement filed on 6/25/2026.
Regarding claim 4, Tochibayashi teaches the limitations of claim 1. Tochibayashi does not teach insulation layer patterns disposed on a bottom surface of each of the source pattern and the drain pattern.
In a similar field of endeavor, Ji teaches, in Fig. 3H, insulation layer patterns (130, [0073]) disposed on a bottom surface of each of the source pattern and the drain pattern (140a/140b, [0046]) (see Fig. 3H), in order to reduce leakage current and short channel effects ([0005]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the insulation layer patterns of Ji, in order to reduce leakage current and short channel effects ([0005]).
Claims 6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tochibayashi et al. (US 20170263651) in view of Atsumi et al. (US 2016043110).
Regarding claim 6, Tochibayashi teaches the limitations of claim 5. Tochibayashi further teaches that each of the first lower gate insulation layer (402 excluding its top layer) and the etch stop layer (top layer of 402) includes metal oxides having dielectric constants higher than a dielectric constant of silicon nitride ([0144], e.g. hafnium oxide or gallium oxide).
Tochibayashi does not teach that the first lower gate insulation layer and the etch stop layer include different materials from each other.
In a similar field of endeavor, Atsumi teaches that the first lower gate insulation layer (402a/402b, Fig. 10B) and the etch stop layer (402c, Fig. 10B, [0184]) include different materials from each other ([0174]; 402b can include aluminum oxide while 402c can include hafnium oxide), for the purpose of “preventing the leakage of trapped electrons” ([0132]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the materials of the first lower gate insulation layer and the etch stop layer with the materials of Atsumi, for the purpose of preventing the leakage of trapped electrons ([0132]).
Regarding claim 16, Tochibayashi teaches the limitations of claim 13. Tochibayashi further teaches that each of the first lower gate insulation layer (402 excluding its top layer) and the etch stop layer (top layer of 402) includes metal oxides having dielectric constants higher than a dielectric constant of silicon nitride ([0144], e.g. hafnium oxide or gallium oxide).
Tochibayashi does not teach that the first lower gate insulation layer and the etch stop layer include different materials from each other.
In a similar field of endeavor, Atsumi teaches that the first lower gate insulation layer (402a/402b, Fig. 10B) and the etch stop layer (402c, Fig. 10B, [0184]) include different materials from each other ([0174]; 402b can include aluminum oxide while 402c can include hafnium oxide), for the purpose of “preventing the leakage of trapped electrons” ([0132]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the materials of the first lower gate insulation layer and the etch stop layer with the materials of Atsumi, for the purpose of preventing the leakage of trapped electrons ([0132]).
Regarding claim 17, Tochibayashi in view of Atsumi teaches the limitations of claim 16. Atsumi further teaches that the first lower gate insulation layer (402a/402b) includes aluminum oxide or zirconium oxide ([0174]), and the etch stop layer (402c) includes hafnium oxide ([0174]).
Claims 9-10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tochibayashi et al. (US 20170263651) in view of Koezuka et al. (US 20160225795).
Regarding claim 9, Tochibayashi teaches the limitations of claim 1. Tochibayashi further teaches that the oxide semiconductor layer has a structure in which a plurality of oxide semiconductor layers are stacked ([0126], [0153], the oxide semiconductor layer can include 406_2b in addition to 406_3b).
Tochibayashi does not teach that the plurality of oxide semiconductor layers has different charge carrier concentrations from each other.
In a similar field of endeavor, Koezuka teaches that the plurality of oxide semiconductor layers (108a and 108b, Fig. 9) have different charge carrier concentrations ([0108]) from each other, in order to improve the reliability of the semiconductor device ([0108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the charge carrier concentrations of Koezuka, in order to improve the reliability of the semiconductor device ([0108]).
Regarding claim 10, Tochibayashi teaches the limitations of claim 1. Tochibayashi further teaches that the oxide semiconductor layer has a stacked structure including a first oxide semiconductor layer and a second oxide semiconductor layer ([0126], [0153], the oxide semiconductor layer can include 406_2b in addition to 406_3b).
Tochibayashi does not teach that the second oxide semiconductor layer has a charge carrier concentration higher than a charge carrier concentration of the first oxide semiconductor layer.
In a similar field of endeavor, Koezuka teaches that the second oxide semiconductor layer (108b) has a charge carrier concentration higher than a charge carrier concentration of the first oxide semiconductor layer (108a) ([0108]), in order to improve the reliability of the semiconductor device ([0108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the charge carrier concentrations of Koezuka, in order to improve the reliability of the semiconductor device ([0108]).
Regarding claim 18, Tochibayashi teaches the limitations of claim 13. Tochibayashi further teaches that the oxide semiconductor layer has a stacked structure including a first oxide semiconductor layer and a second oxide semiconductor layer ([0126], [0153], the oxide semiconductor layer can include 406_2b in addition to 406_3b).
Tochibayashi does not teach that the second oxide semiconductor layer has a charge carrier concentration higher than a charge carrier concentration of the first oxide semiconductor layer.
In a similar field of endeavor, Koezuka teaches that the second oxide semiconductor layer (108b) has a charge carrier concentration higher than a charge carrier concentration of the first oxide semiconductor layer (108a) ([0108]), in order to improve the reliability of the semiconductor device ([0108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tochibayashi with the charge carrier concentrations of Koezuka, in order to improve the reliability of the semiconductor device ([0108]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tochibayashi et al. (US 20170263651) embodiment of Fig. 2B in view of Tochibayashi et al. (US 20170263651) embodiment of Fig. 34.
Regarding claim 12, Tochibayashi teaches the limitations of claim 1. Tochibayashi further teaches, in Fig. 2B, that the substrate (400) includes a silicon substrate ([0135]).
Tochibayashi does not teach, in Fig. 2B, a lower structure including a silicon based transistor disposed on the silicon substrate.
Tochibayashi teaches, in Fig. 34, a lower structure including a silicon based transistor (300, [0370]) disposed on the silicon substrate, in order to provide a semiconductor device with improved reliability ([0012]) and because embodiments can be combined ([0598]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the embodiment of Fig. 2B with the embodiment of Fig. 34, in order to provide a semiconductor device with improved reliability ([0012]) and because embodiments can be combined ([0598]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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