Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 15, paragraph 1 of applicant’s arguments, filed 08/04/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 over Morito(US 20160064473 A1, hereafter Morito) in view of Ding(US 20210118794 A1, hereafter Ding) and over Morito in view of Choi(US 20160104763 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Zhan(US 20220208764 A1, hereafter Zhan) in view of Ding. While independent claim 19 is not separately discussed in applicant’s reply, the corresponding rejection of claim 19 in view of the relevant arguments regarding Claim 1 is also withdrawn. A new rejection of claim 19 is also made below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-7, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of Ding.
Regarding Claim 1, Zhan discloses:
A semiconductor device(Fig. 21), comprising:
A substrate(Fig. 21 [10]) including a cell region(Fig. 21 [A]) and a peripheral region(Fig. 21 [B]) surrounding the cell region(Fig. 21 [A]);
a lower electrode(Fig. 21 [41]) extending in a vertical direction on the cell region(Fig. 21 [A]) of the substrate(Fig. 21 [10]);
an upper electrode(Fig. 21 [29]) surrounding a sidewall and a top surface of the lower electrode(Fig. 21 [41]);
a capacitor dielectric(Fig. 21 [27]) between the lower electrode(Fig. 21 [41]) and the upper electrode(Fig. 21 [29]);
a first barrier layer(Fig. 21 [50]) on the upper electrode(Fig. 21 [29]), the first barrier layer(Fig. 21 [50]) being in contact with each of a sidewall and a top surface of the upper electrode(Fig. 21 [29]);
a first interlayer insulating layer(Fig. 21 [70]) covering the first barrier layer(Fig. 21 [50]),
a first contact(Fig. 21 [71]) penetrating through the first barrier layer(Fig. 21 [50]) and the first interlayer insulating layer(Fig. 21 [70]) in the vertical direction, the first contact(Fig. 21 [71]) being in direct contact with the upper electrode(Fig. 21 [29]), wherein no portion of the first barrier layer(Fig. 21 [50]) is interposed between the first contact(Fig. 21 [71]) and the upper electrode(Fig. 21 [29]);
Firstly, Zhan does not explicitly state that the barrier layer(Fig. 21 [50]) and the interlayer insulating layer(Fig. 21 [70]) are comprised of different materials. However, they possess different structural features and are clearly indicated as being separate layers. One of ordinary skill in the art would have conceived these two as comprising different materials as a matter of routine experimentation in the creation of Zhan’s device.
Secondly, Zhan does not teach or disclose a wiring pattern on the first contact, a second barrier layer on the first interlayer insulating layer, the second barrier layer extending along an upper surface of the first interlayer insulating layer and surrounding a sidewall of the wiring pattern; and
a second interlayer insulating layer on the second barrier layer and surrounding the sidewall of the wiring pattern.
In the same field of endeavor, Ding discloses a wiring pattern(Fig. 4 [332]) on a first contact(Fig. 4 [270]); a second barrier layer(Fig. 4 [305]) extending along an upper surface of a first interlayer insulating layer(Fig. 4 [210]) and surrounding a sidewall of the wiring pattern(Fig. 4 [332]); and
A second interlayer insulating layer(Fig. 4 [312]) on the second barrier layer(Fig. 4 [305]) and surrounding the sidewall of the wiring pattern(Fig. 4 [332]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify Zhan’s device as to add Ding’s wiring structure and accompanying barrier and interlayer insulation layers. One might have been motivated to provide such a structure in order to connect Zhan’s capacitor with a connection to an external component to operate Zhan’s device. The resulting device would have been a predictable result as the addition of Ding’s wiring structure to Zhan’s device would have resulted in an expected integrated capacitor structure.
Regarding Claim 2, Zhan further discloses:
A first etch stop layer(Fig. 21 [24]) between the substrate(Fig. 21 [10]) and the first barrier layer(Fig. 21 [50]), the first etch stop layer(Fig. 21 [24]) being in contact with the first barrier layer(Fig. 21 [50]) on the peripheral region(Fig. 21 [B]) of the substrate(Fig. 21 [10]).
For clarity, the specification of the application at hand states the etch stop layer as being silicon nitride, as Zhan also discloses their layer(Fig. 21 [24]) as comprising silicon nitride(See paragraph 0045).
Regarding Claim 3, Zhan further discloses a top surface of the first interlayer insulating layer(Fig. 21 [70]) is on a same plane as a top surface of the first contact(Fig. 21 [71]).
In the same field of endeavor,
Regarding Claim 6, Zhan further discloses:
A first supporter pattern(Fig. 21 [22]) surrounding a portion of the sidewall of the lower electrode(Fig. 21 [41]) on the substrate(Fig. 21 [10]); and
a second supporter pattern(Fig. 21 [24]) surrounding another portion of the sidewall of the lower electrode(Fig. 21 [41]) on the first supporter pattern(Fig. 21 [22]).
Regarding Claim 7, Zhan further discloses:
The first barrier layer(Fig. 21 [50]) is conformal on the upper electrode(Fig. 21 [29]).
Regarding Claim 21, Zhan further discloses:
The lower electrode(Fig. 21 [41]) is confined within the cell region(Fig. 21 [A]) of the substrate(Fig. 21 [10]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan and Ding, further in view of Morito.
Regarding Claim 4, Neither Zhan nor Ding teach or disclose the first barrier layer includes at least one of aluminum oxide and aluminum nitride.
In the same field of endeavor, Morito discloses a barrier layer(Fig. 1 [300]) including aluminum oxide(See paragraph 0039).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Zhan along the lines of Morito. One might have been motivated to use an alternative composition of the barrier layer to utilize the advantageous physical properties over aluminum oxide as Zhan does not provide an explicit mention of what their barrier layer is comprised of. Performing this modification would have generated a predictable result in the creation of an alternative embodiment of Zhan’s device with a barrier layer comprising a known material.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan and Ding, further in view of Tong et al.(CN 112436007 A, hereafter Tong).
Regarding Claim 5, Zhan further discloses:
A second contact(Fig. 21 [52]) penetrating through the first barrier layer(Fig. 21 [50]) on the peripheral region of the substrate(Fig. 21 [10]), the second contact(Fig. 21 [52]) being spaced apart from the upper electrode(Fig. 21 [29]) in a horizontal direction.
Neither Zhan nor Ding teach or disclose the second contact penetrating through the first interlayer insulating layer in the vertical direction.
In the same field of endeavor, Tong discloses a second contact(Fig. 16 [801]) penetrating a first barrier layer(Fig. 16 [603]) and a first interlayer insulating layer(Fig. 16 [702]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify Zhan’s device along the lines of Tong. One might have been motivated to provide a contact which penetrates both the interlayer insulating layer and the barrier layer as to route a signal between a component above Zhan’s device and the lower wordline structure(See Fig. 21 [12]) of Zhan without interfacing with an interposing transistor(Fig. 21 [60] of Zhan). Producing this device would have generated a predictable result in the generation of a simplified version of Zhan’s device.
Regarding claim 22, Zhan further discloses:
The second contact(Fig. 21 [52]) does not overlap the lower electrode(Fig. 21 [41]) in the vertical direction.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan and Ding, further in view of Choi.
Regarding Claim 10,
Ding discloses a second barrier layer(Fig. 2 [326]).
Neither Zhan nor Ding teach or disclose the second barrier layer as being made of aluminum oxide or aluminum nitride.
In the same field of endeavor, Choi discloses a barrier layer(Fig. 2A [184]) comprising aluminum nitride(See Paragraph 0063).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Zhan and Ding along the lines of Choi. While Ding does not disclose aluminum nitride as a suitable material, they do disclose a set of suitable materials as a number of conductive nitrides(See paragraph 0052 of Ding). As aluminum nitride is a conductive nitride, one might have been motivated to use aluminum nitride as it is a known conductive nitride used for the prevention of diffusion of chlorine ions into the electrode(See paragraph 0102). Producing this device would have generated a predictable result in the creation of Zhan’s device with an aluminum nitride barrier layer surrounding the second wiring layer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan and Ding, further in view of Kim et al.(US 20190157214 A1, hereafter Kim).
Regarding Claim 11,
Zhan does not teach or disclose a second etch stop layer surrounding the sidewall of the wiring pattern between the second barrier layer and the second interlayer insulating layer, the second etch stop layer including a material different from a material of the second barrier layer.
In the same field of endeavor, Kim discloses:
A second etch stop layer(Fig. 10 [LE/SS1]) surrounding the sidewall of the wiring pattern(Fig. 10 [131]) between the second barrier layer(Fig. 10 [SS2]) and the second interlayer insulating layer(Fig. 10 [LK1]), the second etch stop layer(Fig. 10 [LE/SS1]) including a material different from a material of the second barrier layer(SS2 comprises Al2O3, See paragraph 0052, SS1 comprises SiCN, See paragraph 0051).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Zhan and Ding along the lines of Kim. One might have been motivated to apply the second barrier layer and second etch stop layer as to direct hydrogen to a transistor on a lower level, as the purpose of Kim’s layer configuration is to guide hydrogen to transistors on a lower level in order to improve the data retention time(See paragraphs 0040-0042). Producing this device would have generated a predictable result in the creation of a capacitor device as disclosed by Zhan and Ding, with a layer structure disclosed by Kim. While Kim may not explicitly disclose the SS2 layer as being an etch stop layer, the resulting structure, which as specified in paragraph 0034 of the application at hand can be comprised of SiCN, matches the structure disclosed by Kim.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito in view of Zhan and Ding.
Regarding Claim 19, Morito discloses:
A semiconductor device(Fig. 1, 3) comprising:
A substrate(Fig. 1 [110]) including a cell region(See Fig. 3 below) and a peripheral region(See Fig. 3 below) surrounding the cell region(See Fig. 3 below);
A lower electrode(Fig. 1 [200]) extending in a vertical direction on the cell region(See Fig. 3 below) of the substrate(Fig. 1 [110]);
An upper electrode(Fig. 1 [220]) on a top surface of the lower electrode(Fig. 1 [200]);
A capacitor dielectric layer(Fig. 1 [210]) between the lower electrode(Fig. 1 [200]) and the upper electrode(Fig. 1 [220]);
A first barrier layer(Fig. 1 [300]) on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being in contact with each of a sidewall and a top surface of the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being conformally on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) including aluminum oxide(See paragraph 0039);
A first interlayer insulating layer(Fig. 1 [400]) covering the first barrier layer(Fig. 1 [300]), the first interlayer insulating layer(Fig. 1 [400]) including a material different from the material of the first barrier layer(Fig. 1 [300], See paragraph 0041, [400] is made of polyimide, See paragraph 0039, [300] is made of Al2O3); and
A first contact(Fig. 1 [520]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction, the first contact(Fig. 1 [520]) being connected to the upper electrode(Fig. 1 [220]); and
A second contact(Fig. 1 [510]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction on the peripheral region(See Fig. 1 below) of the substrate(Fig. 1 [110]), the second contact(Fig. 1 [510]) being spaced apart from the upper electrode(Fig. 1 [220]) in a horizontal direction, and top surfaces of the first interlayer insulating layer(Fig. 1 [400]), the first contact(Fig. 1 [520]), and the second contact(Fig. 1 [510]) being coplanar with each other.
Morito also does not teach or disclose a first etch stop layer or the limitations contained therein.
In the same field of endeavor, Ding discloses a first etch stop layer(Fig. 2 [205]) on a substrate(Fig. 2 [100]), the first etch stop layer(Fig. 2 [205]) surrounding a portion of the sidewall of the lower electrode(Fig. 2 [252]), the first etch stop layer(Fig. 2 [205]) being on the peripheral region of the substrate.
Furthermore, Ding and Morito do not explicitly teach the first etch stop layer between the substrate and the first barrier layer or in contact with the barrier layer on the peripheral region of the substrate.
However, when taken in combination, it would have been obvious to arrive at the limitations of claim 2 based on the teachings of Morito and Ding. According to Ding, the creation of Ding’s capacitor structure would require a set of deposition and etching steps(See Figs. 11-14 of Ding) of which the etch stop layer(See Figs. 11-14 [205]) would be necessary as a part of etching a structure to produce the capacitor structure described by Ding. Furthermore, if considering the capacitor described by Ding to the device disclosed by Morito, placement of Morito’s barrier layer(Fig. 1 [300]) directly above the capacitor structure provided by Ding would be the most immediate location to deposit the barrier layer, as in accordance with the plate capacitor given by Morito only, the barrier layer is deposited directly on top of the capacitor structure with the layer trailing past the capacitor plates themselves. Therefore, it would have been obvious to arrive at this limitation when applying the capacitor structure described by Ding to the device disclosed by Morito.
In addition, neither Morito nor Ding teach or disclose no portion of the first barrier layer is interposed between the first contact and the upper electrode.
In the same field of endeavor, Zhan discloses a first barrier layer(Fig. 21 [50]) wherein no portion of it is interposed between the first contact(Fig. 21 [71]) and the upper electrode(Fig. 21 [29]).
It would have been obvious to one of ordinary skill in the art to produce Morito’s device along the lines of Zhan. When viewing the contact structure disclosed by Morito, the presence of contact structure which covers a portion of the barrier layer is a consequence of the steps of etching and deposition that accompany the production of the device. One might have been motivated to provide a contact structure wherein there is no barrier layer between the top electrode and bottom electrode in order to provide a more compact structure, as the ability of a contact to transmit charge would be limited by the narrowest portion of the contact. Producing this device would have generated a predictable result in the creation of a modified version of Morito’s device with an etch stop structure as disclosed by Ding and a modified contact as disclosed by Zhan.
Furthemore, Morito does not teach or disclose a wiring pattern on the first contact, a second barrier layer on the first interlayer insulating layer, the second barrier layer extending along an upper surface of the first interlayer insulating layer and surrounding a sidewall of the wiring pattern; and
a second interlayer insulating layer on the second barrier layer and surrounding the sidewall of the wiring pattern.
In the same field of endeavor, Ding discloses a wiring pattern(Fig. 4 [332]) on a first contact(Fig. 4 [270]); a second barrier layer(Fig. 4 [305]) extending along an upper surface of a first interlayer insulating layer(Fig. 4 [210]) and surrounding a sidewall of the wiring pattern(Fig. 4 [332]); and
A second interlayer insulating layer(Fig. 4 [312]) on the second barrier layer(Fig. 4 [305]) and surrounding the sidewall of the wiring pattern(Fig. 4 [332]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify Morito’s device as to add Ding’s wiring structure and accompanying barrier and interlayer insulation layers. One might have been motivated to provide such a structure in order to connect Morito’s capacitor with a connection to an external component to operate Morito’s device. The resulting device would have been a predictable result as the addition of Ding’s wiring structure to Morito’s device would have resulted in an expected integrated capacitor structure.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito, Zhan, and Ding, further in view of Choi.
Regarding Claim 20,
Ding discloses a second barrier layer(Fig. 2 [326]).
Neither Morito, Ding, nor Zhan teach or disclose the second barrier layer as being made of aluminum oxide or aluminum nitride.
In the same field of endeavor, Choi discloses a barrier layer(Fig. 2A [184]) comprising aluminum nitride(See Paragraph 0063).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Morito, Zhan and Ding along the lines of Choi. While Ding does not disclose aluminum nitride as a suitable material, they do disclose a set of suitable materials as a number of conductive nitrides(See paragraph 0052 of Ding). As aluminum nitride is a conductive nitride, one might have been motivated to use aluminum nitride as it is a known conductive nitride used for the prevention of diffusion of chlorine ions into the electrode(See paragraph 0102). Producing this device would have generated a predictable result in the creation of Morito’s device with Ding’s capacitor structure and an aluminum nitride barrier layer surrounding the second wiring layer.
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Above: Fig. 1 of Morito with cell region and peripheral region denoted by examiner.
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Above: Fig. 3 of Morito with Cell and peripheral regions denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zelner(US 20090121316 A1) discloses a capacitor structure with a contact that penetrates a barrier layer. Cho(US 8310026 B2) discloses a capacitor structure with a contact that penetrates a barrier layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
