Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species III, drawn to Figs. 15-16, Claims 1-7, 9-11, 19-20 in the reply filed on 04/15/2026 is acknowledged. The traversal is on the ground(s) that Group II is not unique because of the limitations in group II(such as the first etch stop layer and the composition of aluminum) are found in claims of Group I. This is true, however, claim 1 must still be examined under the conditions of not necessarily holding those dependent limitations. If these limitations were present in both independent claims, then the claims would then be overlapping and/or not mutually exclusive. Furthermore, while a restriction between species III and V can be withdrawn as the argument that a search of the second etch stop layer and the second barrier layer as in Fig. 15 should necessarily encompass that of Fig. 19 of Species V, the same cannot be said for Species VII, wherein two different sub-barrier layers are shown. Therefore, the election requirement between species III and V is withdrawn, but the remaining election requirement between species is maintained.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito et al.(US 20160064473 A1, hereafter Morito) in view of Ding et al.(US 20210118794 A1, hereafter Ding).
Regarding Claim 1, Morito discloses:
A semiconductor device(Fig. 1, 3) comprising:
A substrate(Fig. 1 [110]) including a cell region(See Fig. 3 below) and a peripheral region(See Fig. 3 below) surrounding the cell region(See Fig. 3 below);
A lower electrode(Fig. 1 [200]) extending in a vertical direction on the cell region(See Fig. 3 below) of the substrate(Fig. 1 [110]);
An upper electrode(Fig. 1 [220]) on a top surface of the lower electrode(Fig. 1 [200]);
A capacitor dielectric layer(Fig. 1 [210]) between the lower electrode(Fig. 1 [200]) and the upper electrode(Fig. 1 [220]);
A first barrier layer(Fig. 1 [300]) on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being in contact with each of a sidewall and a top surface of the upper electrode(Fig. 1 [220]);
A first interlayer insulating layer(Fig. 1 [400]) covering the first barrier layer(Fig. 1 [300]), the first interlayer insulating layer(Fig. 1 [400]) including a material different from the material of the first barrier layer(Fig. 1 [300], See paragraph 0041, [400] is made of polyimide, See paragraph 0039, [300] is made of Al2O3); and
A first contact(Fig. 1 [520]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction, the first contact(Fig. 1 [520]) being connected to the upper electrode(Fig. 1 [220]).
Morito does not teach or disclose the upper electrode surrounding a sidewall and a top surface of the lower electrode.
In the same field of endeavor, Ding discloses a top electrode(Fig. 2 [256]) which surrounds a top surface and a sidewall of the lower electrode(Fig. 2 [252]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to apply Ding’s capacitor structure to the device disclosed by Morito. One might have been motivated to apply the capacitor structure provided by Ding in order to improve the capacitance per area of the capacitor structure(See paragraphs 0005-0007), as well as a known property of capacitors in that capacitance will scale with the area of the plates of a capacitor. Performing this modification would have generated a predictable result in the creation of Morito’s device with an improved capacitor structure provided by Ding.
Regarding Claim 2,
Morito does not teach or disclose a first etch stop layer or the limitations contained therein.
In the same field of endeavor, Ding discloses a first etch stop layer(Fig. 2 [205]) on a substrate(Fig. 2 [100]), the first etch stop layer(Fig. 2 [205]) surrounding a portion of the sidewall of the lower electrode(Fig. 2 [252]), the first etch stop layer(Fig. 2 [205]) being on the peripheral region of the substrate.
Furthermore, Ding and Morito do not explicitly teach the first etch stop layer between the substrate and the first barrier layer or in contact with the barrier layer on the peripheral region of the substrate.
However, when taken in combination, it would have been obvious to arrive at the limitations of claim 2 based on the teachings of Morito and Ding. According to Ding, the creation of Ding’s capacitor structure would require a set of deposition and etching steps(See Figs. 11-14 of Ding) of which the etch stop layer(See Figs. 11-14 [205]) would be necessary as a part of etching a structure to produce the capacitor structure described by Ding. Furthermore, if considering the capacitor described by Ding to the device disclosed by Morito, placement of Morito’s barrier layer(Fig. 1 [300]) directly above the capacitor structure provided by Ding would be the most immediate location to deposit the barrier layer, as in accordance with the plate capacitor given by Morito only, the barrier layer is deposited directly on top of the capacitor structure with the layer trailing past the capacitor plates themselves. Therefore, it would have been obvious to arrive at this limitation when applying the capacitor structure described by Ding to the device disclosed by Morito.
Regarding Claim 3, Morito further discloses:
A top surface of the first interlayer insulating layer(Fig. 1 [400]) is on a same plane as a top surface of the first contact(Fig. 1 [520]).
Regarding Claim 4, Morito further discloses:
The first barrier layer(Fig. 1 [300]) includes at least one of Aluminum oxide(Al2O3) and aluminum nitride(AlN)(See Paragraph paragraph 0039, [300] is made of Al2O3).
Regarding Claim 5, Morito further discloses:
A second contact(Fig. 1 [510]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction on the peripheral region(See Fig. 1 below) of the substrate(Fig. 1 [110]), the second contact(Fig. 1 [510]) being spaced apart from the upper electrode(Fig. 1 [220]) in a horizontal direction.
Regarding Claim 7, Morito further discloses:
The first barrier layer(Fig. 1 [300]) is conformal on the upper electrode(Fig. 1 [220]).
Regarding Claim 9, Morito further discloses:
A circuit board(See paragraph 0034) on which a first(Fig. 1 [520]) and second(Fig. 1 [510]) contact lead out of.
Morito does not teach or disclose:
a wiring pattern on the first contact;
A second barrier layer surrounding a sidewall of the wiring pattern on the first interlayer insulating layer; and
A second interlayer insulating layer surrounding the sidewall of the wiring pattern on the second barrier layer.
In the same field of endeavor, Ding discloses:
A wiring pattern(Fig. 2 [322]) on a first contact(Fig. 2 [270]);
A second barrier layer(Fig. 2 [326]) surrounding a sidewall of the wiring pattern(Fig. 2 [322]) on the first interlayer insulating layer(Fig. 2 [210]); and
A second interlayer insulating layer(Fig. 2 [312]) surrounding the sidewall of the wiring pattern(Fig. 2 [322]) on the second barrier layer(Fig. 2 [326]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Morito along the lines of Ding. One might have been motivated to apply the wiring pattern as to provide a circuitry with which to connect the capacitor to other components, a barrier layer in order to prevent diffusion of conductive particles into the insulating films, and an additional interlayer insulating layer to insulate and provide structural support for the wiring layers. Performing this modification would have generated a predictable result in the generation of Morito’s device with an additional wiring structure as disclosed by Ding.
Regarding Claim 19, Morito discloses:
A semiconductor device(Fig. 1, 3) comprising:
A substrate(Fig. 1 [110]) including a cell region(See Fig. 3 below) and a peripheral region(See Fig. 3 below) surrounding the cell region(See Fig. 3 below);
A lower electrode(Fig. 1 [200]) extending in a vertical direction on the cell region(See Fig. 3 below) of the substrate(Fig. 1 [110]);
An upper electrode(Fig. 1 [220]) on a top surface of the lower electrode(Fig. 1 [200]);
A capacitor dielectric layer(Fig. 1 [210]) between the lower electrode(Fig. 1 [200]) and the upper electrode(Fig. 1 [220]);
A first barrier layer(Fig. 1 [300]) on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being in contact with each of a sidewall and a top surface of the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being conformally on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) including aluminum oxide(See paragraph 0039);
A first interlayer insulating layer(Fig. 1 [400]) covering the first barrier layer(Fig. 1 [300]), the first interlayer insulating layer(Fig. 1 [400]) including a material different from the material of the first barrier layer(Fig. 1 [300], See paragraph 0041, [400] is made of polyimide, See paragraph 0039, [300] is made of Al2O3); and
A first contact(Fig. 1 [520]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction, the first contact(Fig. 1 [520]) being connected to the upper electrode(Fig. 1 [220]); and
A second contact(Fig. 1 [510]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction on the peripheral region(See Fig. 1 below) of the substrate(Fig. 1 [110]), the second contact(Fig. 1 [510]) being spaced apart from the upper electrode(Fig. 1 [220]) in a horizontal direction, and top surfaces of the first interlayer insulating layer(Fig. 1 [400]), the first contact(Fig. 1 [520]), and the second contact(Fig. 1 [510]) being coplanar with each other.
Morito does not teach or disclose the upper electrode surrounding a sidewall and a top surface of the lower electrode.
In the same field of endeavor, Ding discloses a top electrode(Fig. 2 [256]) which surrounds a top surface and a sidewall of the lower electrode(Fig. 2 [252]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to apply Ding’s capacitor structure to the device disclosed by Morito. One might have been motivated to apply the capacitor structure provided by Ding in order to improve the capacitance per area of the capacitor structure(See paragraphs 0005-0007), as well as a known property of capacitors in that capacitance will scale with the area of the plates of a capacitor. Performing this modification would have generated a predictable result in the creation of Morito’s device with an improved capacitor structure provided by Ding.
Morito also does not teach or disclose a first etch stop layer or the limitations contained therein.
In the same field of endeavor, Ding discloses a first etch stop layer(Fig. 2 [205]) on a substrate(Fig. 2 [100]), the first etch stop layer(Fig. 2 [205]) surrounding a portion of the sidewall of the lower electrode(Fig. 2 [252]), the first etch stop layer(Fig. 2 [205]) being on the peripheral region of the substrate.
Furthermore, Ding and Morito do not explicitly teach the first etch stop layer between the substrate and the first barrier layer or in contact with the barrier layer on the peripheral region of the substrate.
However, when taken in combination, it would have been obvious to arrive at the limitations of claim 2 based on the teachings of Morito and Ding. According to Ding, the creation of Ding’s capacitor structure would require a set of deposition and etching steps(See Figs. 11-14 of Ding) of which the etch stop layer(See Figs. 11-14 [205]) would be necessary as a part of etching a structure to produce the capacitor structure described by Ding. Furthermore, if considering the capacitor described by Ding to the device disclosed by Morito, placement of Morito’s barrier layer(Fig. 1 [300]) directly above the capacitor structure provided by Ding would be the most immediate location to deposit the barrier layer, as in accordance with the plate capacitor given by Morito only, the barrier layer is deposited directly on top of the capacitor structure with the layer trailing past the capacitor plates themselves. Therefore, it would have been obvious to arrive at this limitation when applying the capacitor structure described by Ding to the device disclosed by Morito.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito in view of Choi et al.(US 20170104763 A1, hereafter Choi).
Regarding Claim 1, Morito discloses:
A semiconductor device(Fig. 1, 3) comprising:
A substrate(Fig. 1 [110]) including a cell region(See Fig. 3 below) and a peripheral region(See Fig. 3 below) surrounding the cell region(See Fig. 3 below);
A lower electrode(Fig. 1 [200]) extending in a vertical direction on the cell region(See Fig. 3 below) of the substrate(Fig. 1 [110]);
An upper electrode(Fig. 1 [220]) on a top surface of the lower electrode(Fig. 1 [200]);
A capacitor dielectric layer(Fig. 1 [210]) between the lower electrode(Fig. 1 [200]) and the upper electrode(Fig. 1 [220]);
A first barrier layer(Fig. 1 [300]) on the upper electrode(Fig. 1 [220]), the first barrier layer(Fig. 1 [300]) being in contact with each of a sidewall and a top surface of the upper electrode(Fig. 1 [220]);
A first interlayer insulating layer(Fig. 1 [400]) covering the first barrier layer(Fig. 1 [300]), the first interlayer insulating layer(Fig. 1 [400]) including a material different from the material of the first barrier layer(Fig. 1 [300], See paragraph 0041, [400] is made of polyimide, See paragraph 0039, [300] is made of Al2O3); and
A first contact(Fig. 1 [520]) penetrating through the first barrier layer(Fig. 1 [300]) and the first interlayer insulating layer(Fig. 1 [400]) in the vertical direction, the first contact(Fig. 1 [520]) being connected to the upper electrode(Fig. 1 [220]).
Morito does not teach or disclose the upper electrode surrounding a sidewall and a top surface of the lower electrode.
In the same field of endeavor, Choi discloses an upper electrode(Fig. 3 [182]) surrounding a sidewall and a top surface of a lower electrode(Fig. 3 [172]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to apply Choi’s capacitor structure to the device disclosed by Morito. One might have been motivated to apply the capacitor structure provided by Choi in order to improve the capacitance per area of the capacitor structure(See paragraph 0005), as well as a known property of capacitors in that capacitance will scale with the area of the plates of a capacitor. Performing this modification would have generated a predictable result in the creation of Morito’s device with an improved capacitor structure provided by Choi.
Regarding Claim 6,
Morito does not teach or disclose a first supporter pattern or a second supporter pattern or the limitations contained therein.
In the same field of endeavor, Choi discloses:
A first supporter pattern(Fig. 3 [131]) surrounding a portion of the sidewall of the lower electrode(Fig. 3 [172]) on the substrate(Fig. 3 [100]); and
A second supporter pattern(Fig. 3 [151]) surrounding another portion of the sidewall of the lower electrode(Fig. 3 [172]) on the first supporter pattern.
It would have been further obvious to modify the device disclosed by Morito along the lines of Choi. In the creation of Choi’s capacitor structure, one of ordinary skill in the art would take the teachings of Choi to produce this structure, which would necessarily require these support structures in order to provide the necessary structural support to produce Choi’s capacitor structure. Production of Choi’s capacitor structure(See Figs. 4A-4G of Choi) would necessarily require these supporter patterns to create this capacitor structure. Producing Morito’s device in this way would have generated a predictable result in the creation of Morito’s device with an improved capacitor structure as disclosed by Choi.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito and Ding, further in view of Choi.
Regarding Claim 10,
Ding discloses a second barrier layer(Fig. 2 [326]).
Ding does not teach or disclose the second barrier layer as being made of aluminum oxide or aluminum nitride.
In the same field of endeavor, Choi discloses a barrier layer(Fig. 2A [184]) comprising aluminum nitride(See Paragraph 0063).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Morito and Ding along the lines of Choi. While Ding does not disclose aluminum nitride as a suitable material, they do disclose a set of suitable materials as a number of conductive nitrides(See paragraph 0052 of Ding). As aluminum nitride is a conductive nitride, one might have been motivated to use aluminum nitride as it is a known conductive nitride used for the prevention of diffusion of chlorine ions into the electrode(See paragraph 0102). Producing this device would have generated a predictable result in the creation of Morito’s device with Ding’s capacitor structure and an aluminum nitride barrier layer surrounding the second wiring layer.
Regarding Claim 20,
A circuit board(See paragraph 0034) on which a first(Fig. 1 [520]) and second(Fig. 1 [510]) contact lead out of.
Morito does not teach or disclose:
a wiring pattern on the first contact;
A second barrier layer surrounding a sidewall of the wiring pattern on the first interlayer insulating layer; and
A second interlayer insulating layer surrounding the sidewall of the wiring pattern on the second barrier layer.
In the same field of endeavor, Ding discloses:
A wiring pattern(Fig. 2 [322]) on a first contact(Fig. 2 [270]);
A second barrier layer(Fig. 2 [326]) surrounding a sidewall of the wiring pattern(Fig. 2 [322]) on the first interlayer insulating layer(Fig. 2 [210]); and
A second interlayer insulating layer(Fig. 2 [312]) surrounding the sidewall of the wiring pattern(Fig. 2 [322]) on the second barrier layer(Fig. 2 [326]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Morito along the lines of Ding. One might have been motivated to apply the wiring pattern as to provide a circuitry with which to connect the capacitor to other components, a barrier layer in order to prevent diffusion of conductive particles into the insulating films, and an additional interlayer insulating layer to insulate and provide structural support for the wiring layers. Performing this modification would have generated a predictable result in the generation of Morito’s device with an additional wiring structure as disclosed by Ding.
Further, Neither Morito nor Ding teach or disclose the second barrier layer as being made of aluminum oxide or aluminum nitride.
In the same field of endeavor, Choi discloses a barrier layer(Fig. 2A [184]) comprising aluminum nitride(See Paragraph 0063).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Morito and Ding along the lines of Choi. While Ding does not disclose aluminum nitride as a suitable material, they do disclose a set of suitable materials as a number of conductive nitrides(See paragraph 0052 of Ding). As aluminum nitride is a conductive nitride, one might have been motivated to use aluminum nitride as it is a known conductive nitride used for the prevention of diffusion of chlorine ions into the electrode(See paragraph 0102). Producing this device would have generated a predictable result in the creation of Morito’s device with Ding’s capacitor structure and an aluminum nitride barrier layer surrounding the second wiring layer.
Claim(s) 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morito and Ding, further in view of Kim et al.(US 20190157214 A1, hereafter Kim).
Regarding Claim 9,
Morito does not teach or disclose:
a wiring pattern on the first contact;
A second barrier layer surrounding a sidewall of the wiring pattern on the first interlayer insulating layer; and
A second interlayer insulating layer surrounding the sidewall of the wiring pattern on the second barrier layer.
In the same field of endeavor, Kim discloses:
A wiring pattern(Fig. 10 [131]) on the first contact(fig. 10 [111]);
A second barrier layer(Fig. 10 [LE/SS2]) surrounding a sidewall of the wiring pattern(Fig. 10 [131]) on the first interlayer insulating layer(Fig. 10 [105]); and
A second interlayer insulating layer(Fig. 10 [LK1]) surrounding the sidewall of the wiring pattern(Fig. 10 [131]) on the second barrier layer(Fig. 10 [LE/SS2]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Morito along the lines of Kim. One might have been motivated to apply the wiring pattern as to provide a circuitry with which to connect the capacitor to other components, a barrier layer in order to prevent diffusion of conductive particles into the insulating films, and an additional interlayer insulating layer to insulate and provide structural support for the wiring layers. Performing this modification would have generated a predictable result in the generation of Morito’s device with an additional wiring structure as disclosed by Kim.
Regarding Claim 11,
Morito does not teach or disclose a second etch stop layer surrounding the sidewall of the wiring pattern between the second barrier layer and the second interlayer insulating layer, the second etch stop layer including a material different from a material of the second barrier layer.
In the same field of endeavor, Kim discloses:
A second etch stop layer(Fig. 10 [LE/SS1]) surrounding the sidewall of the wiring pattern(Fig. 10 [131]) between the second barrier layer(Fig. 10 [SS2]) and the second interlayer insulating layer(Fig. 10 [LK1]), the second etch stop layer(Fig. 10 [LE/SS1]) including a material different from a material of the second barrier layer(SS2 comprises Al2O3, See paragraph 0052, SS1 comprises SiCN, See paragraph 0051).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Morito and Ding along the lines of Kim. One might have been motivated to apply the second barrier layer and second etch stop layer as to direct hydrogen to a transistor on a lower level, as the purpose of Kim’s layer configuration is to guide hydrogen to transistors on a lower level in order to improve the data retention time(See paragraphs 0040-0042). Producing this device would have generated a predictable result in the creation of a capacitor device as disclosed by Morito and Ding, with a layer structure disclosed by Kim. While Kim may not explicitly disclose the SS2 layer as being an etch stop layer, the resulting structure, which as specified in paragraph 0034 of the application at hand can be comprised of SiCN, matches the structure disclosed by Kim.
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Above: Fig. 1 of Morito with cell region and peripheral region denoted by examiner.
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Above: Fig. 3 of Morito with Cell and peripheral regions denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zelner(US 20090121316 A1) discloses a capacitor structure with a contact that penetrates a barrier layer. Tong et al.(CN 112436007 A) discloses a capacitor structure with a contact that penetrates a barrier layer. Cho(US 8310026 B2) discloses a capacitor structure with a contact that penetrates a barrier layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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