DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 6 April 2026 of Applicants’ amendments in which claims 1, 11, 18, and 20 are amended.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue in the last paragraph of page 15 that Kim does not teach the subject matter of amended independent claims 18 and 20 because Kim’s upper surface of the alleged first contact (309) is positioned at a lower vertical level than an upper surface of the alleged bit line (BL). Claim 18 now recites (and claim 20 similarly recites) “an upper surface of the first contact is positioned at a higher vertical level than an upper surface of the bit line.” Amended claims 18 and 20 are rejected as being anticipated by Kim. During patent examination, the pending claims must be given their broadest reasonable interpretation consistent with the specification. MPEP §2111. As this principle applies to the present circumstance, Kim teaches in Fig. 3A an upper surface of the first contact (309) is positioned at a higher vertical level than an upper surface of the bit line (BL) {Fig. 3A; the illustration of Kim’s Fig. 3A may be rotated to achieve an appropriate orientation to meet this claim limitation}.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines , recites “the first conductive pad is provided in plural and disposed on the first and second active regions, and wherein the first conductive pad disposed on the first active region overlaps the first conductive pad disposed on the second active region in the second direction,” which is indefinite because it is unclear which of the plural first conductive pads, if any, is disposed on the first active region and which, if any, is disposed on the second active region. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the first conductive pad includes a primary first conductive pad and a secondary first conductive pad, the primary first conductive pad is disposed on the first active region and the secondary first conductive pad is disposed on the second active region, and the primary first conductive pad overlaps the secondary first conductive pad in the second direction.” Claims 2-17 are rejected due to their dependence from base claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim et al. (US20220406791A1).
Regarding claim 18, Kim teaches in Figs. 1A and 1B a semiconductor device comprising (see annotated copy of Kim’s Fig. 1A, below}:
a device isolation part (302) disposed on a substrate (301) to define an active region (ACT), the active region (ACT) being lengthwise in a first direction (X1) {Fig. 1A; [0031, 0032]};
first and second word lines (WL) crossing the active region (ACT) in a second direction (X2) intersecting the first direction (X1) and being adjacent to each other in a third direction (X3) intersecting the first and second directions (X1, X2) {Fig. 1A; [0034]};
a first impurity region (3d) disposed in the active region (ACT) between the first and second word lines (WL) {[0035]};
a second impurity region (3b) disposed in the active region (ACT) at one side of the first word line (WL) and spaced apart from the first impurity region (3d) {[0035]};
a first conductive pad (DC) in contact with the first impurity region (3d) {Fig. 2C; [0038]};
a second conductive pad (XP) in contact with the second impurity region (3b) {Fig. 2C; [0042]};
a bit line (BL) disposed on the first conductive pad (DC) and extending in the third direction (X3) {Fig. 2C; [0042]};
a storage node contact structure (BC and 309) on the second conductive pad (XP) {Fig. 1B; [0059]}; and
a landing pad (LP) on the storage node contact structure (BC and 309) {Fig. 1B; [0060]},
wherein the storage node contact structure (BC and 309) {Fig. 1B; [0060]} includes:
a first contact (309) contacting the second conductive pad (XP) and having a first width {Fig. 3A; [0059]}; and
a second contact (311) disposed on the first contact (309) and having a second width greater than the first width {Fig. 3A; [0056]}, and
wherein an upper surface of the first contact (309) is positioned at a higher vertical level than an upper surface of the bit line (BL) {Fig. 3A; the illustration of Kim’s Fig. 3A may be rotated to achieve an appropriate orientation to meet this claim limitation}.
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Regarding claim 19, Kim teaches the semiconductor device of claim 18, and Kim further teaches
further comprising a gate insulating layer (307) interposed between the first word line (WL) and the substrate (301) {Fig. 1B, cross-section B-B’; [0034]}.
wherein the second conductive pad (XP) overlaps the gate insulating layer (307) {the orientation of Fig. 1B may be oriented as necessary to achieve such overlap}, and
wherein the storage node contact structure (BC and 309) overlaps the first word line (WL) {the orientation of Fig. 1B may be oriented as necessary to achieve such overlap}.
Regarding claim 20, Kim teaches in Figs. 1A and 1B a semiconductor device comprising (see annotated copy of Kim’s Fig. 1A, below}:
a device isolation part (302) disposed on the substrate (301) to define first, second, third and fourth active regions (ACT) sequentially arranged in a clockwise direction, the first to fourth active regions (ACT) being lengthwise in a first direction (X1), and the device isolation part (302) extending a second direction (X2) intersecting the first direction (X1) and being interposed between the first and second active regions (ACT) and the third and fourth active regions (ACT) {Fig. 1A; [0031, 0032]};
first and second word lines (WL) crossing the first and second active regions (ACT) in the second direction (X2) and being adjacent to each other in a third direction (X3) intersecting the first and second directions (X1, X2) {Fig. 1A; [0034]};
a gate insulating layer (307) interposed between the first word line (WL) and the substrate (301) {Fig. 1B; [0034]};
a first impurity region (3d) disposed in the first active region (ACT) between the first and second word lines (WL) {[0035]};
a second impurity region (3b) disposed in the first active region (ACT) at one side of the first word line (WL) and spaced apart from the first impurity region (3d) {[0035]};
a first conductive pad (DC) in contact with the first impurity region (3d) {Fig. 2C; [0038]};
a second conductive pad (XP) in contact with the second impurity region (3b) {Fig. 2C; [0042]};
a bit line (BL) disposed on the first conductive pad (DC) and extending in the third direction (X3) {Fig. 2C; [0042]};
a bit line capping pattern (337) on the bit line (BL) {Fig. 1B; [0037]};
a first bit line spacer (321) covering sidewalls of the bit line capping pattern (337) and sidewalls of the bit line (BL) {Fig. 1B; [0048]};
a second bit line spacer (323) covering a lower sidewall of the first bit line spacer (321) and exposing an upper sidewall of the first bit line spacer (321) {Fig. 1B; [0048]};
a storage node contact structure (BC and 309) on the second conductive pad (XP) {Fig. 1B; [0059]}; and
a landing pad (LP) on the storage node contact structure (BC and 309) {Fig. 1B; [0060]},
wherein the storage node contact structure (BC and 309) includes:
a first contact (309) contacting the second conductive pad (XP) and having a first width {Fig. 3A; [0059]}; and
a second contact (311) disposed on the first contact (309) and having a second width greater than the first width {Fig. 3A; [0056]},
wherein the first contact (309) is spaced apart from the first bit line spacer (321) {Fig. 1B}, and
wherein the second contact (311) is in contact with an upper end of the second bit line spacer (323) and the first bit line spacer (321) {Fig. 1B; upper portion of 311 contacts upper portions of 321 and 323}, and
wherein an upper surface of the first contact (309) is positioned at a higher vertical level than an upper surface of the bit line (BL) {Fig. 3A; the illustration of Kim’s Fig. 3A may be rotated to achieve an appropriate orientation to meet this claim limitation}.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-7, 10, 11, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park et al. (US20100237394A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Kim teaches in Figs. 1A and 1B a semiconductor device comprising (see annotated copy of Kim’s Fig. 1A, below}:
a device isolation part (302) disposed on a substrate (301) to define first, second, third and fourth active regions (ACT) sequentially arranged in a clockwise direction, the first to fourth active regions (ACT) extending in a first direction (X1), and the device isolation part (302) extending in a second direction (X2) intersecting the first direction (X1) and being interposed between the first and second active regions (ACT) and the third and fourth active regions (ACT), wherein the first and second active regions (ACT) are disposed immediately next to each other in the second direction (X2) {Fig. 1A; [0031, 0032]; see Examiner’s Note below};
first and second word lines (WL) crossing the first and second active regions (ACT) in the second direction (X2) and being adjacent to each other in a third direction (X3) intersecting the first and second directions (X1, X2) {Fig. 1A; [0034]};
a first impurity region (3d) disposed in the first active region (ACT) between the first and second word lines (WL) {[0035]};
a second impurity region (3b) disposed in the first active region (ACT) at one side of the first word line (WL) and spaced apart from the first impurity region (3d) {[0035]};
a first conductive pad (DC) in contact with the first impurity region (3d) {Fig. 2C; [0038]};
a second conductive pad (XP) in contact with the second impurity region (3b) {Fig. 2C; [0042]};
a bit line (BL/332) disposed on the first conductive pad (DC) and extending in the third direction (X3) {Fig. 2C; [0042]};
a storage node contact structure (BC or {BC and 309}) disposed on the second conductive pad (XP) {Fig. 1B; [0059]}; and
a landing pad (LP) disposed on the storage node contact structure (BC or {BC and 309}) {Fig. 1B; [0060]},
wherein the first conductive pad (DC) includes a primary first conductive pad (DC) and a secondary first conductive pad (DC), the primary first conductive pad (DC) is disposed on the first active region (ACT) and the secondary first conductive pad (DC) is disposed on the second active region (ACT) {see annotated copy of Kim’s Fig. 1A, below}.
Kim does not teach the primary first conductive pad overlaps the secondary first conductive pad in the second direction.
In an analogous art, Park teaches in Fig. 4 and paragraph [0076] a primary first conductive pad (leftmost column, central row 310) overlaps a secondary first conductive pad (2nd leftmost column, central row 310) in a second direction (horizontal). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device based on the teachings of Park, to achieve the above-identified subject matter, because all the claimed elements (e.g., conductive pad) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Park) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
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Regarding claim 2, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches wherein the device isolation part (302) includes:
a first device isolation part (302) interposed between the first and second active regions (ACT) and extending in the first direction (X1) {Figs. 1A, 1B; [0031, 0032]}; and
a second device isolation part (302) interposed between the first and fourth active regions (ACT) and between the second and third active regions (ACT) and extending in the second direction (X2) {Figs. 1A, 1B; [0031, 0032]}.
Regarding claim 4, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches wherein the storage node contact structure (BC or {BC and 309}) includes:
a first contact (309) contacting the second conductive pad (XP) and having a first width {Fig. 3A; [0059]}; and
a second contact (311) disposed on the first contact (309) and having a second width greater than the first width {Fig. 3A; [0056]}.
Regarding claim 5, Kim as modified by Park teaches the semiconductor device of claim 4, and Kim further teaches further comprising:
a first interlayer insulating pattern (325) interposed (diagonally) between the bit line (BL) and the second conductive pad (XP) {Fig. 3A; [0048]};
a bit line capping pattern (337) on the bit line (BL) {Fig. 1B; [0037]};
a first bit line spacer (321) covering the bit line capping pattern (337) and sidewalls of the bit line (BL) {Fig. 1B; [0048]}; and
a second bit line spacer (323) covering a lower sidewall of the first bit line spacer (321) and exposing an upper sidewall of the first bit line spacer (321) {Fig. 1B; [0048]},
wherein the first contact (309) is spaced apart from the first bit line spacer (321) {Fig. 1B}, and
wherein the second contact (311) is in contact with an upper end of the second bit line spacer (323) and the first bit line spacer (321) {Fig. 1B; upper portion of 311 contacts upper portions of 321 and 323}.
Regarding claim 6, Kim as modified by Park teaches the semiconductor device of claim 5, and Kim further teaches wherein
the storage node contact structure (BC or {BC and 309}) is provided in plural {Figs. 1A, 1B},
wherein the semiconductor device further includes:
first, second and third storage node contact structures (BC or {BC and 309}) spaced apart from each other in the third direction (X3) {Figs. 1A, 1B};
a first contact separation pattern (38) interposed between the first and second storage node contact structures (BC or {BC and 309}) {Fig. 1B, cross-section A-A’; [0052]}; and
a second contact separation pattern (38) interposed between the second and third storage node contact structures (BC or {BC and 309}) {Fig. 1B, cross-section B-B’; [0052]}, and
wherein the second bit line spacer (323) is interposed (diagonally) between the first contact separation pattern (38) and the first storage node contact structure (BC or {BC and 309}), and is in contact (at upper end) with the first storage node contact structure (BC or {BC and 309}) {Fig. 1B, cross-section B-B’; [0048]}.
Regarding claim 7, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches further comprising
a gate insulating layer (307) interposed between the first word line (WL) and the substrate (301) {Fig. 1B; [0034]},
wherein the second conductive pad (XP) overlaps the gate insulating layer (307) {the orientation of Fig. 1B may be oriented as necessary to achieve such overlap}, and
wherein the storage node contact structure (BC or {BC and 309}) overlaps the first word line (WL) {the orientation of Fig. 1B may be oriented as necessary to achieve such overlap}.
Regarding claim 10, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches further comprising a bit line contact (331) disposed between the bit line (332) and the first conductive pad (DC),
wherein the bit line contact (331) has a first width in the third direction (X3), and
wherein the first conductive pad (DC) has a second width in the third direction (X3), the second width being smaller than the first width {Figs. 1A, 1B; Bit line (BL) in Figs. 1A and 1B includes both (331) and (332); bit line (BL) has a greater dimension/width in the third direction (X3) within Fig. 1A than does (DC)}.
Regarding claim 11, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches
wherein the semiconductor device further includes:
a first pad separation pattern (30r(1)) disposed between the first conductive pad (DC) and the second conductive pad (XP) {Fig. 1B, 30r(1) between rightmost (DC) and its right-side adjacent (XP) in cross-section A-A’; [0046]}; and
a second pad separation pattern (30r(1)) interposed between the first conductive pad (DC) on the first active region (DC) and the first conductive pad (DC) on the second active region (ACT) {Fig. 1B, 30r(1) between leftmost (DC) and its rightmost (DC) in cross-section A-A’; [0046]}.
Regarding claim 14, Kim as modified by Park teaches the semiconductor device of claim 11, and Kim further teaches
wherein an upper surface of the device isolation part (302) is lower than an upper surface of the substrate (301) to expose a first sidewall and a second sidewall of the substrate (301) {Fig. 1B, 3B},
wherein the first conductive pad (DC) is in contact with the first sidewall of the substrate (301) and surrounds the first impurity region (3d) when viewed in a plan view {Fig. 1B, 2C}, and
wherein the second conductive pad (XP) is in contact with the second sidewall of the substrate (301) and surrounds the second impurity region (3b) when viewed in a plan view {Fig. 1B, 2C}.
Regarding claim 15, Kim as modified by Park teaches the semiconductor device of claim 11, and Kim further teaches
wherein the first conductive pad (DC) is in contact with an upper surface of the first impurity region (3d) {Fig. 1B}, and
wherein the second conductive pad (XP) is in contact with an upper surface of the second impurity region (3b) {Fig. 1B}.
Regarding claim 16, Kim as modified by Park teaches the semiconductor device of claim 15, and Kim further teaches
wherein the first impurity region (3d) has a first width in the second direction (X2), the first conductive pad (DC) has a second width in the second direction (X2), the second width being greater than the first width {Fig. 2A}, and
wherein the second impurity region (3b) has a third width in the second direction (X2), and the second conductive pad (XP) has a fourth width in the second direction (X2), the fourth width being greater than the third width {Fig. 2A}.
Regarding claim 17, Kim as modified by Park teaches the semiconductor device of claim 11, and Kim further teaches wherein lower ends of the first conductive pad (DC) and the second conductive pad (XP) are disposed at the same level as each other {Fig. 3A}.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park as applied to claim 1 above, and further in view of Takesako (US20120049251A1) and Kuroki (US20120043642A1).
Regarding claim 3, Kim as modified by Park teaches the semiconductor device of claim 1, but Kim does not teach further comprising
a dummy word line disposed in the device isolation part between the first and fourth active regions and between the second and third active regions,
wherein the dummy word line is electrically grounded or floated.
In an analogous art, Takesako teaches in Fig. 3 and paragraph [0037] a dummy word line (22b) disposed in a device isolation part (5) between the first (bottom left) and fourth (bottom right) active regions (7) and between the second (top left) and third (top right) active regions (7) {orientation of Fig. 3 may be rotated 90 degrees clockwise to achieve compatible orientation with Kim’s Fig. 1A}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device as modified by Park based on the teachings of Takesako, to achieve the subject matter identified above, for maintaining the regularity of pattern arrangement when patterning the gate electrode … and thereby enhancing the precision of the patterning process. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, all the claimed elements (e.g., dummy word line, first, second, third, and fourth active regions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Takesako) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Kim and Takesako do not teach the dummy word line is electrically grounded or floated.
In an analogous art, Kuroki teaches in paragraph [0074] a dummy word line is electrically grounded. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device as modified by Park and Takesako based on the teachings of Kuroki, to achieve the subject matter identified above, to reduce the influence of undesirable environmental signals being capacitively coupled to an adjacent word line through the dummy word line. See, e.g., Kuroki ¶0075. Moreover, all the claimed elements (e.g., dummy word line, grounded) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kuroki) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park as applied to claim 1 above, and further in view of Luo (US20220059694A1).
Regarding claim 8, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches wherein, when viewed in a plan view, each of the first to fourth active regions (ACT) includes:
first and second sidewalls (left and right sidewalls) parallel to each other in the first direction (X1) {Fig. 1A};
a third sidewall (upper/lower sidewall) connecting the first and second sidewalls (left and right sidewalls) {Fig. 1A}.
Kim does not necessarily teach:
a first corner where the first sidewall and the third sidewall meet; and
a second corner where the second sidewall and the third sidewall meet,
wherein the first sidewall and the third sidewall form an acute angle with each other, and
wherein the second sidewall and the third sidewall form an obtuse angle with each other.
In an analogous art, Luo teaches in Fig. 1 and paragraph [0050] that each of multiple active regions (10) comprises a first corner where a first sidewall and a third sidewall meet; and a second corner where a second sidewall and the third sidewall meet, wherein the first sidewall and the third sidewall form an acute angle with each other, and wherein the second sidewall and the third sidewall form an obtuse angle with each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device as modified by Park based on the teachings of Luo, to achieve the above-identified features, because [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., first, second, third sidewalls of an active region; first and second corners of the active region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Luo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park as applied to claim 1 above, and further in view of Lim et al. (US20220085025A1).
Regarding claim 9, Kim as modified by Park teaches the semiconductor device of claim 1, and Kim further teaches wherein at least one of the first conductive pad and the second conductive pad includes:
a first silicon pattern in contact with the substrate; and
a first ohmic pattern on the first silicon pattern.
In an analogous art, Lim teaches in Fig. 1 and paragraphs [0024, 0025] a pad (25, 45) includes a first silicon pattern (25) in contact with a substrate (10) and a first ohmic pattern (45) on the first silicon pattern (25). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device as modified by Park based on the teachings of Lim – such that at least one of Kim’s first conductive pad and second conductive pad includes: a first silicon pattern in contact with the substrate; and a first ohmic pattern on the first silicon pattern –because [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., silicon pattern, ohmic pattern) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lim) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park as applied to claim 1 above, and further in view of Kim et al. (US20220384449A1).
Regarding claim 12, Kim as modified by Park teaches the semiconductor device of claim 11, and Kim further teaches
wherein the second conductive pad (XP) is in contact with a second sidewall of the substrate (301).
Kim does not teach the first pad separation pattern is in contact with a first sidewall of the substrate and wherein the first sidewall is spaced apart from the second sidewall.
In an analogous art, Kim ‘449 teaches in Fig. 34B:
wherein a first pad separation pattern (rightmost unlabeled 38 in A-A’) is in contact with a first sidewall of a substrate (301),
wherein a second conductive pad (XP) is in contact with a second sidewall of the substrate (301), and
wherein the first sidewall is spaced apart from the second sidewall.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s semiconductor device as modified by Park based on the teachings of Kim ‘449, to achieve the above-identified features, because [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., first pad separation pattern, second conductive pad, sidewalls of substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kim ‘449) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 13, Kim as modified by Park and Kim ‘449 teaches the semiconductor device of claim 12, and Kim further teaches wherein the substrate (301) further includes a third sidewall (left/right sidewall in contact with XP) adjacent to the second sidewall (right/left sidewall in contact with XP), and
wherein the second conductive pad (XP) is in contact with the third sidewall (left/right sidewall in contact with XP) {Fig. 1B}.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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