Prosecution Insights
Last updated: July 17, 2026
Application No. 18/378,444

TRANSISTOR CHARACTERISTIC SIMULATION DEVICE, TRANSISTOR CHARACTERISTIC SIMULATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING TRANSISTOR CHARACTERISTIC SIMULATION PROGRAM

Non-Final OA §102§103§112
Filed
Oct 10, 2023
Priority
Jun 01, 2021 — continuation of PCTJP2021020770
Examiner
BOWERS, BRANDON
Art Unit
Tech Center
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
466 granted / 542 resolved
+26.0% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
7 currently pending
Career history
549
Total Applications
across all art units

Statute-Specific Performance

§101
13.4%
-26.6% vs TC avg
§103
44.1%
+4.1% vs TC avg
§102
31.0%
-9.0% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 542 resolved cases

Office Action

§102 §103 §112
CTNF 18/378,444 CTNF 79266 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-12 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With regards to these claims, it is unclear what the transitional phrase is or if there is one at all. For example in claim 1, is “using” in line one the transition? Is “comprises” in line 3 the transitional phrase? Is “wherein” in line 2 the transitional phrase? Is there no transitional phrase? As written, it cannot be ascertained what defines the claim and what is preamble based upon the lack of a definite transitional phrase. Dependent claims 2-12 do not rectify this rejection and therefore are also rejected for the same reason. Independent claim 14 is rejected for same reason as claim 1. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-8, 13 and 14 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu, US Patent No. 7,016,819 . In reference to claim 1, Lui teaches a transistor characteristic simulation device (Title, simulator) using a transistor equivalent circuit model (Column 3, lines 26-67, simulation of semiconductor device, Column 1, line 48 – column 2, line 14, the device being a transistor), wherein the transistor equivalent circuit model comprises a trap equivalent circuit for modifying a level of a trap of a transistor by an electric field intensity, the trap equivalent circuit corresponding to a physical model of Poole-Frenkel effect (Column 3, lines 30-40, Column 4, lines 25 – Column 5, line 35, Figure 6, trap equivalent circuits modeling enhancement values vs electric fields). In reference to claim 2, Lui teaches wherein the trap equivalent circuit includes circuit parameters that have voltage dependence and temperature dependence and represent a time constant of the trap, and corresponds to the physical model of Poole-Frenkel effect by the time constant of the trap being modified depending on voltage and temperature (Column 4, lines 25 – Column 5, line 35, Dirac Coulombic Tunnelling Integral, Column 2, lines 46-57 This G-R model is consistently formulated for the entire range of electric fields and temperatures). In reference to claim 3, Lui teaches wherein the voltage dependence and the temperature dependence are expressed by one exponential function (Column 5, lines 46-54, each variable is reduced to a simple exponential function). In reference to claim 4, Lui teaches wherein the voltage dependence is a dependence on an output voltage proportional to an electric field strength of a channel, and the temperature dependence is a dependence on a channel temperature (Figure 9 Temperature T, voltage v). In reference to claims 5-8, Lui teaches wherein the trap equivalent circuit includes a circuit representing the time constant of the trap, and the circuit representing the time constant of the trap is provided between drain electrode and a source electrode, between a gate electrode and the source electrode, or between the gate electrode and the drain electrode (Figure 9, time t). In reference to claim 13, Liu teaches a transistor characteristic simulation method (Title, Simulation method) performed by a transistor characteristic simulation device (Title, Simulator), the transistor characteristic simulation method comprising: receiving setting values related to various parameters of a transistor circuit model (Column 3, lines 1, 8); performing a simulation using a transistor equivalent circuit model comprising a trap equivalent circuit for modifying a level of a trap of a transistor by an electric field intensity, the trap equivalent circuit corresponding to a physical model of Poole-Frenkel effect and the received setting values (Column 3, lines 9-25, Figure 9); and outputting a result of the simulation (Figures 5,6). In reference to claim 14, drawn to a non-transitory computer readable medium containing all of the same functional limitations as found in claim 1, the same rejection applies . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu, US Patent No. 7,016,819 in view of Otsuka, US PGPUB No. 2014/0019096 . In reference to claims 9-12, Liu teaches claim 1 and claims 5-8 respectively. Liu does not teach wherein the circuit representing the time constant of the trap comprises a resistor and a capacitor, and both the resistor and the capacitor have voltage dependence and temperature dependence. Otsuka teaches a transistor characteristic calculation apparatus comprising a circuit model having a resistor and capacitor. Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the circuit model having a resistor and capacitor as taught by Otsuka into the circuit representing the time constant of the trap as taught by Liu such that both the resistor and the capacitor of Otsuka have voltage dependence and temperature dependence ask taught by Liu to therefore teach claims 9-12 respectively because the accuracy of calculation in the characteristics of the transistor is improved, thereby improving design accuracy thereof and reducing the number of times in the trial manufacture (Otsuka, Paragraph [0021]) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.B/ Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851 Application/Control Number: 18/378,444 Page 2 Art Unit: 2851 Application/Control Number: 18/378,444 Page 3 Art Unit: 2851 Application/Control Number: 18/378,444 Page 4 Art Unit: 2851 Application/Control Number: 18/378,444 Page 5 Art Unit: 2851 Application/Control Number: 18/378,444 Page 6 Art Unit: 2851 Application/Control Number: 18/378,444 Page 7 Art Unit: 2851
Read full office action

Prosecution Timeline

Oct 10, 2023
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.6%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 542 resolved cases by this examiner. Grant probability derived from career allowance rate.

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