DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restriction Applicant’s election without traverse of Species (b) in the reply filed on 2/04/26 is acknowledged. This election corresponds to claims 1-7, 13-16, and 18-22 (claims 2-3, 15, and 19-21 in addition to those identified by Applicant). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-7 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Lu (U.S. PGPub 2024/0145482) . Regarding claim 1 , Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising a substrate ([0017]), an active layer disposed on the substrate (Fig. 3, 130”, [0033]), a first gate electrode disposed on the active layer (151, Fig. 2, [0040]), a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]), a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]), wherein the second gate electrode has a floating structure (152, [0034]). Regarding claim 2 , Lu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (first connection part 138c, second connection part 138b, channel part between, [0031]) and each of the first gate electrode and the second gate electrode does not overlap with the first connection part and the second connection part (Fig. 3). Regarding claim 3 , Lu does not explicitly teach wherein, when a voltage is applied to the first gate electrode, a voltage lower than that of the first gate electrode is applied to the second gate electrode. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01. The claimed and prior art device have the same gate electrode structure and therefore anticipate the claimed properties. Regarding claim 4 , Lu teaches wherein a direction in which the first gate electrode and the second gate electrode face each other is the same as a direction in which the source electrode and the drain electrode face each other (Fig. 4). Regarding claim 5 , Lu teaches wherein the first gate electrode and the second gate electrode are disposed on a same layer and do not overlap with each other, and the first gate electrode and the second gate electrode include the same material (Fig. 3, [0021]). Regarding claim 6 , Lu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (first connection part 138c, second connection part 138b, channel part between, [0031]), and a portion of the channel part does not overlap with the first gate electrode and the second gate electrode (Fig. 3). Regarding claim 7 , Lu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (first connection part 138c, second connection part 138b, channel part between, [0031]), and a portion of the channel part does not overlap with any one of the first gate electrode and the second gate electrode (Fig. 3). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 14-16, 18-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Sakakura (U.S. PGPub 2009/0261337) . Regarding claim 14 , Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising a substrate ([0017]), a first thin film transistor disposed on the substrate, wherein the first thin film transistor includes: an active layer disposed on the substrate (Fig. 3, 130”, [0033]), a first gate electrode disposed on the active layer (151, Fig. 2, [0040]), a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]), a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]), wherein the second gate electrode has a floating structure (152, [0034]). Lu does not explicitly teach a second thin film transistor disposed on the substrate and having a structure different from that of the first thin film transistor. Sakakura teaches a thin film transistor substrate comprising first and second thin film transistors (Fig. 7, 538, 537), where the transistors have different structures ([0172], switching TFT can be single gate, [0169], driving TFT can be multi gate). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Sakakura with Lu such that the substrate comprises a second thin film transistor disposed on the substrate and having a structure different from that of the first thin film transistor for the purpose of forming pixel TFTs ( Sakakura , [0126]; Lu, [0003]). Regarding claim 15 , the combination of Lu and Sakakura teaches wherein the second thin film transistor includes, a second active layer disposed on the substrate; a third gate electrode disposed on the second active layer; a second source electrode disposed on the second active layer and connected to one side of the second active layer; and a second drain electrode disposed on the second active layer and connected to another side of the second active layer, wherein the second thin film transistor has a smaller number of gate electrodes than the first thin film transistor has ( Sakakura , Fig. 7, 538, [0172], single gate TFT). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Sakakura for the reasons set forth in the rejection of claim 14. Regarding claim 16 , the combination of Lu and Sakakura teaches wherein the first gate electrode, the second gate electrode and the third gate electrode are disposed on a same layer ( Sakakura , Fig. 7). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Sakakura for the reasons set forth in the rejection of claim 14. Regarding claim 18 , the combination of Lu and Sakakura teaches wherein the first gate electrode and the second gate electrode do not overlap with each other (Lu, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Sakakura for the reasons set forth in the rejection of claim 14. Regarding claim 19 , the combination of Lu and Sakakura teaches wherein the substrate includes a pixel region where a pixel is defined, a plurality of driving thin film transistors and a plurality of switching thin film transistors are disposed in the pixel region, at least one of the plurality of driving thin film transistors includes the first thin film transistor, and at least one of the plurality of switching thin film transistors includes the second thin film transistor ( Sakakura , Fig. 7, pixel area, [0169], driving TFT 537 can be multi gate, [0172], switching TFT 538 can be single gate). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Sakakura for the reasons set forth in the rejection of claim 14. Regarding claim 20 , the combination of Lu and Sakakura teaches wherein the first gate electrode is electrically connected to one side of any one of the plurality of the switching thin film transistors ( Sakakura , Fig. 9, [0194], driving TFT 937, switching TFT 938). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Sakakura for the reasons set forth in the rejection of claim 14. Regarding claim 22 , Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising a substrate ([0017]), an active layer disposed on the substrate (Fig. 3, 130”, [0033]), a first gate electrode disposed on the active layer (151, Fig. 2, [0040]), a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]), a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]), wherein the second gate electrode has a floating structure (152, [0034]). Lu does not explicitly teach a display apparatus comprising the thin film transistor substrate. Sakakura teaches a multi gate TFT used as a driving TFT of a display apparatus ([0169]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Sakakura with Liu such that a display apparatus comprises the thin film transistor substrate for the purpose of providing the display apparatus of Sakakura with the improved TFT of Lu (Lu, [0003]-[0004]). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Liu (U.S. PGPub 2020/0243566) . Regarding claim 13 , Lu teaches a light shielding layer disposed under the active layer (110, [0017]) but does not explicitly teach wherein the light shielding layer is electrically connected to the source electrode. Lu teaches wherein the light shielding layer is electrically connected to the top gate and operates as a bottom gate ([0034]). Liu teaches wherein a light shielding layer disposed under the active layer of a TFT is electrically connected to the source electrode instead of operating as a bottom gate with the gate voltage applied ([0004]; [0132], 11, 17). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Lu such that the light shielding layer is electrically connected to the source electrode for the purpose of decreasing manufacturing complexity (Liu, [0004]). Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Sakakura (U.S. PGPub 2009/0261337) and Kim (U.S. PGPub 2019/0189723) . Regarding claim 21 , Liu and Sakakura do not explicitly teach a capacitor disposed in the pixel region, wherein the capacitor is provided by the first gate electrode of the first thin film transistor and the first source electrode of the first thin film transistor. Kim teaches a TFT comprising a capacitor in a pixel region, where the capacitor is provided by the gate electrode and source electrode of the driving TFT (Fig. 7, [0060], [0063]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Liu and Sakakura such that the device comprises a capacitor disposed in the pixel region, wherein the capacitor is provided by the first gate electrode of the first thin film transistor and the first source electrode of the first thin film transistor for the purpose of providing a storage capacitor (Kim, [0060]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ALIA SABUR whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7219 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9:30-5:30 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine S. Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALIA SABUR/ Primary Examiner, Art Unit 2812