DETAILED ACTION
Response to Arguments
Applicant's arguments filed 7/01/26 have been fully considered but they are not persuasive.
Applicant has amended the limitations of previous dependent claim 13 (“a light shielding layer disposed under the active layer… electrically connected to the source electrode”) into independent claims 1, 14, and 22. Applicant argues that the combination of Lu and Liu, previously cited, is invalid because it would “destroy the intended purpose and operation” of Lu (Remarks, p. 7-8).
As cited in the previous Office action, Lu teaches a thin-film transistor with improved electrical properties ([0003]) which comprises a light-shielding bottom gate layer ([0017]) and does not otherwise discuss the features or effects of the bottom gate. Liu teaches that this configuration is standard to improve electrical characteristics of a thin-film transistor but has specific drawbacks due to the required manufacturing processes ([0004]), and that providing the light-shielding layer electrically connected to the source electrode reduces these drawbacks while still providing improved electrical characteristics ([0082], [0131], [0067]). The purpose of Lu (forming a TFT with good electrical characteristics) is maintained, while reducing specific drawbacks by using a known alternative structure as taught by Liu. The rejection is maintained.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Liu (U.S. PGPub 2020/0243566).
Regarding claim 1, Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising
a substrate ([0017]),
an active layer disposed on the substrate (Fig. 3, 130”, [0033]),
a first gate electrode disposed on the active layer (151, Fig. 2, [0040]),
a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]),
a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]),
and a light shielding layer disposed under the active layer (110, [0017]), and
wherein the second gate electrode has a floating structure (152, [0034]).
Lu teaches but does not explicitly teach wherein the light shielding layer is electrically connected to the source electrode. Lu teaches wherein the light shielding layer is electrically connected to the top gate and operates as a bottom gate ([0034]).
Liu teaches wherein a light shielding layer disposed under the active layer of a TFT is electrically connected to the source electrode instead of operating as a bottom gate with the gate voltage applied ([0004]; [0132], 11, 17).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Lu such that the light shielding layer is electrically connected to the source electrode for the purpose of decreasing manufacturing complexity (Liu, [0004]).
Regarding claim 2, the combination of Lu and Liu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (Lu, first connection part 138c, second connection part 138b, channel part between, [0031]) and each of the first gate electrode and the second gate electrode does not overlap with the first connection part and the second connection part (Lu, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Liu for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Lu and Liu does not explicitly teach wherein, when a voltage is applied to the first gate electrode, a voltage lower than that of the first gate electrode is applied to the second gate electrode. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01. The claimed and prior art device have the same gate electrode structure and therefore anticipate the claimed properties.
Regarding claim 4, the combination of Lu and Liu teaches wherein a direction in which the first gate electrode and the second gate electrode face each other is the same as a direction in which the source electrode and the drain electrode face each other (Lu, Fig. 4). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Liu for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Lu and Liu teaches wherein the first gate electrode and the second gate electrode are disposed on a same layer and do not overlap with each other, and the first gate electrode and the second gate electrode include the same material (Lu, Fig. 3, [0021]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Liu for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Lu and Liu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (Lu, first connection part 138c, second connection part 138b, channel part between, [0031]), and a portion of the channel part does not overlap with the first gate electrode and the second gate electrode (Lu, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Liu for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Lu and Liu teaches wherein the active layer comprises a channel part, a first connection part disposed on one side of the channel part and a second connection part disposed on another side of the channel part (Lu, first connection part 138c, second connection part 138b, channel part between, [0031]), and a portion of the channel part does not overlap with any one of the first gate electrode and the second gate electrode (Lu, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu and Liu for the reasons set forth in the rejection of claim 1.
Claims 14-16, 18-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Liu (U.S. PGPub 2020/0243566) and Sakakura (U.S. PGPub 2009/0261337).
Regarding claim 14, Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising
a substrate ([0017]),
a first thin film transistor disposed on the substrate, wherein the first thin film transistor includes:
an active layer disposed on the substrate (Fig. 3, 130”, [0033]),
a first gate electrode disposed on the active layer (151, Fig. 2, [0040]),
a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]),
a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]),
and a light shielding layer disposed under the active layer (110, [0017]), and
wherein the second gate electrode has a floating structure (152, [0034]).
Lu teaches but does not explicitly teach wherein the light shielding layer is electrically connected to the source electrode. Lu teaches wherein the light shielding layer is electrically connected to the top gate and operates as a bottom gate ([0034]).
Liu teaches wherein a light shielding layer disposed under the active layer of a TFT is electrically connected to the source electrode instead of operating as a bottom gate with the gate voltage applied ([0004]; [0132], 11, 17).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Lu such that the light shielding layer is electrically connected to the source electrode for the purpose of decreasing manufacturing complexity (Liu, [0004]).
Lu further does not explicitly teach a second thin film transistor disposed on the substrate and having a structure different from that of the first thin film transistor.
Sakakura teaches a thin film transistor substrate comprising first and second thin film transistors (Fig. 7, 538, 537), where the transistors have different structures ([0172], switching TFT can be single gate, [0169], driving TFT can be multi gate).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Sakakura with Lu and Liu such that the substrate comprises a second thin film transistor disposed on the substrate and having a structure different from that of the first thin film transistor for the purpose of forming pixel TFTs (Sakakura, [0126]; Lu, [0003]).
Regarding claim 15, the combination of Lu, Liu, and Sakakura teaches wherein the second thin film transistor includes, a second active layer disposed on the substrate; a third gate electrode disposed on the second active layer; a second source electrode disposed on the second active layer and connected to one side of the second active layer; and a second drain electrode disposed on the second active layer and connected to another side of the second active layer, wherein the second thin film transistor has a smaller number of gate electrodes than the first thin film transistor has (Sakakura, Fig. 7, 538, [0172], single gate TFT). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu, Liu, and Sakakura for the reasons set forth in the rejection of claim 14.
Regarding claim 16, the combination of Lu, Liu, and Sakakura teaches wherein the first gate electrode, the second gate electrode and the third gate electrode are disposed on a same layer (Sakakura, Fig. 7). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu, Liu, and Sakakura for the reasons set forth in the rejection of claim 14.
Regarding claim 18, the combination of Lu, Liu, and Sakakura teaches wherein the first gate electrode and the second gate electrode do not overlap with each other (Lu, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu, Liu, and Sakakura for the reasons set forth in the rejection of claim 14.
Regarding claim 19, the combination of Lu, Liu, and Sakakura teaches wherein the substrate includes a pixel region where a pixel is defined, a plurality of driving thin film transistors and a plurality of switching thin film transistors are disposed in the pixel region, at least one of the plurality of driving thin film transistors includes the first thin film transistor, and at least one of the plurality of switching thin film transistors includes the second thin film transistor (Sakakura, Fig. 7, pixel area, [0169], driving TFT 537 can be multi gate, [0172], switching TFT 538 can be single gate). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu, Liu, and Sakakura for the reasons set forth in the rejection of claim 14.
Regarding claim 20, the combination of Lu, Liu, and Sakakura teaches wherein the first gate electrode is electrically connected to one side of any one of the plurality of the switching thin film transistors (Sakakura, Fig. 9, [0194], driving TFT 937, switching TFT 938). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lu, Liu, and Sakakura for the reasons set forth in the rejection of claim 14.
Regarding claim 22, Lu teaches a thin film transistor substrate (Fig. 3, [0045]-[0046]) comprising
a substrate ([0017]),
an active layer disposed on the substrate (Fig. 3, 130”, [0033]),
a first gate electrode disposed on the active layer (151, Fig. 2, [0040]),
a second gate electrode disposed on the active layer and spaced apart from the first gate electrode (152, [0034]),
a source electrode disposed over the active layer and connected to one side of the active layer and a drain electrode disposed over the active layer and connected to another side of the active layer (171/172, [0041]),
and a light shielding layer disposed under the active layer (110, [0017]), and
wherein the second gate electrode has a floating structure (152, [0034]).
Lu teaches but does not explicitly teach wherein the light shielding layer is electrically connected to the source electrode. Lu teaches wherein the light shielding layer is electrically connected to the top gate and operates as a bottom gate ([0034]).
Liu teaches wherein a light shielding layer disposed under the active layer of a TFT is electrically connected to the source electrode instead of operating as a bottom gate with the gate voltage applied ([0004]; [0132], 11, 17).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Lu such that the light shielding layer is electrically connected to the source electrode for the purpose of decreasing manufacturing complexity (Liu, [0004]).
Lu does not explicitly teach a display apparatus comprising the thin film transistor substrate.
Sakakura teaches a multi gate TFT used as a driving TFT of a display apparatus ([0169]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Sakakura with Lu and Liu such that a display apparatus comprises the thin film transistor substrate for the purpose of providing the display apparatus of Sakakura with the improved TFT of Lu (Lu, [0003]-[0004]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PGPub 2024/0145482) in view of Liu (U.S. PGPub 2020/0243566), Sakakura (U.S. PGPub 2009/0261337) and Kim (U.S. PGPub 2019/0189723).
Regarding claim 21, Lu, Liu, and Sakakura do not explicitly teach a capacitor disposed in the pixel region, wherein the capacitor is provided by the first gate electrode of the first thin film transistor and the first source electrode of the first thin film transistor.
Kim teaches a TFT comprising a capacitor in a pixel region, where the capacitor is provided by the gate electrode and source electrode of the driving TFT (Fig. 7, [0060], [0063]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Lu, Liu and Sakakura such that the device comprises a capacitor disposed in the pixel region, wherein the capacitor is provided by the first gate electrode of the first thin film transistor and the first source electrode of the first thin film transistor for the purpose of providing a storage capacitor (Kim, [0060]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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