DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Newly submitted claims 21-29 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: FIG. 12 and FIG 15 belong to different species. Moreover, there is combination/sub-combination restriction remains as well.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-29 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant's arguments filed on 07/10/2026 have been fully considered but they are not persuasive.
Applicant argues regarding claim 1 on “Applicant’s Arguments/Remarks Made in an Amendment” “REMARKS” section dated 07/10/2026 that "The claim recites "transistors in the first well region." The Office Action mapped pixels 541A- 541D-each of which includes a photodiode-to this limitation. However, numerous patents and published applications consistently recite photodiodes and transistors as separate, distinct elements. If "photodiode" were synonymous with or encompassed by "transistor," such claim drafting would be redundant and nonsensical. A POSITA reading the claim would not interpret "transistors in the first well region" as encompassing photodiodes.”.
However, the examiner disagrees. The examiner explained 539 is the photo sharing unit which contains (pixels 541A, 541B, 541C, and 541D), but remember pixel sharing units includes plurality of transistor as in Paragraph [0216]). Transistors are mapped to 539 as mentioned, not to the pixels. Hence, the applicant’s arguments are not persuasive.
Applicant argues regarding claim 10 that “In rejecting claim 10, the Office Action relied on paragraphs [0225] and [0228] of Nakazawa, mapped device 510A disclosed by Nakazawa to the claimed "memory array structure," and that "mapped device 510A is a memory device." Applicant respectfully disagrees and submits that such mapping is incorrect as a matter of both the express disclosure of Nakazawa and proper claim construction. A POSITA would understand that Nakazawa's input section 510A is not a memory device and does not contain a memory array structure.”
However, the examiner disagrees. However, the input section 510A may include a memory interface circuit that receives data from the external memory device. Examples of the external memory device include a flash memory, an SRAM, a DRAM, and the like. So, 510 can be considered section comprising memory device like SRAM, DRAM etc. Hence, the applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 20 are rejected under 35 U.S.C. 35 U.S.C. 103 as being unpatentable over NAKAZAWA et al. (US PGpub: 2022/0271070 A1), hereinafter NAKAZAWA, in view of NAKAZAWA.
Regarding claim 1, NAKAZAWA teaches a semiconductor device (Paragraphs [0240]-[0671], FIG. 1-145) , comprising:
a first semiconductor structure (100 which includes 100S, 100T) comprising:
a first well region (p-well layer region 115), and
transistors in the first well region (The first substrate 100 includes a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing units 539. As described in detail later with reference to FIG. 4, the pixel sharing unit 539 includes a plurality of transistors. [0216], Each of the pixels 541 includes a photodiode. Paragraph [0230], FIG. 2); and
a second semiconductor structure (200 which includes 200S, 200T) bonded with the first semiconductor structure and comprising:
a second well region (well region 211), and
fin field effect transistors (AMP, Paragraph [0302], Paragraph [0527 reveals that it is an FinFET) in the second well region, each fin field effect transistor comprising:
a gate oxide layer (212, Considered gate oxide layer in Paragraph [0279]), in contact with a top surface and side surfaces of the fin structure (is in contact with top and side surface of 200S, FIG. 6, 21), and
a gate layer (221 or 222) covering the gate oxide layer (212, FIG. 21C).
NAKAZAWA does not explicitly teach a fin structure in the same embodiment.
NAKAZAWA discloses a fin structure (AMP includes a Fin, paragraph [0302], FIG. 6 and FIG, 16A-16B, Paragraph [0304]) in a different embodiment.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use NAKAZAWA’s semiconductor device with other teaching from NAKAZAWA such that it is possible to increase an effective gate width in the transistor, as compared with the planar type transistor. Accordingly, a large amount of current passes through the transistor having the three-dimensional structure to increase transconductance gm. This makes it possible to improve operation speed in the transistor having the three-dimensional structure, as compared with the planar type transistor. In addition, it is possible to reduce RN (Random Noise). In addition, the transistor having the three-dimensional structure has a larger gate area, as compared with the planar type transistor, which reduces RTS (Random Telegraph Signal) noise.
Regarding claim 2, NAKAZAWA teach the semiconductor device of claim 1, wherein: the first semiconductor structure comprises a first insulating layer (123, FIG. 26A); and the second semiconductor structure comprises a second insulating layer (212); wherein: a first surface of the second insulating layer is bonded with the first insulating layer, a second surface of the second insulating layer opposite to the first surface comprises protruding portions, and each fin structure is located on a top surface of a corresponding protruding portion (Please see below annotated Figure).
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Regarding claim 3, NAKAZAWA teaches the semiconductor device of claim 1, wherein: the fin has a thickness between 30nm and 65nm in a vertical direction perpendicular to a bonding interface between the first semiconductor structure and the second semiconductor structure (If 120B has s hole diameter of 140nm Paragraph [0382], it is possible to have fin thickness to be less that 70nm or even less than 60nm if you look at the picture above. So, the fin thickness (as annotated in above Figure) to be manipulated to have thickness between 30nm-65nm).
Regarding claim 4, NAKAZAWA teaches the semiconductor device of claim 2, wherein: the gate oxide layer (221, Considered gate oxide layer (Paragraph [0279], and is in contact with top and side surface of 200S, FIG. 6, 21) is further in contact with portions of a bottom surface of the fin structure (FIG. 34, 214 contacts bottom and top portion of the FIN structure. Eventually, it also contacts side surface of FIN structure as well).
Regarding claim 5, NAKAZAWA teaches the semiconductor device of claim 2, wherein, a contact interface between the protruding portion and the fin structure is less (this language is unclear, the examiner is considering. Less in what? ) than a bottom surface of the fin structure (however, see attached annotated figure for contact interface).
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Regarding claim 6, NAKAZAWA teaches the semiconductor device of claim 1, wherein: a thickness of a gate oxide layer (117B) of the transistors in the first well region (115) is greater than a thickness of the gate oxide layer (212) of the fin field effect transistors in the second well region *as in below Figure 8A)..
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Regarding claim 7, NAKAZAWA teaches the semiconductor device of claim 1, wherein: the second well region comprises a first sub-well region and a second sub-well region.
NAKAZAWA does not explicitly teach a thickness of the gate oxide layer in the first sub-well region is greater than a thickness of the gate oxide layer in the second sub-well region.
Also, In below Figure 211 well region has different portions which have different thicknesses.
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However, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the etch through routine experimentation and optimization to obtain optimal or desired device performance because the etch is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding claim 8, NAKAZAWA teaches the semiconductor device of claim 2, wherein the second semiconductor structure further comprises: a first isolation structure (213, FIG. 28 or above annotated figure) configured to isolate two portions of the gate layer corresponding to two adjacent fin structures (as annotated in the figure).
Regarding claim 9, NAKAZAWA teaches the semiconductor device of claim 7, wherein the second semiconductor structure further comprises: a second isolation structure (as annotated below) configured to isolate two portions of the gate layer corresponding to the first sub-well region and the second sub-well region, respectively.
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Regarding claim 10, NAKAZAWA teaches the semiconductor device of claim 1, further comprising: a memory array structure bonded with the second semiconductor structure (FIG. 69, where device 510A is a memory device which might include SRAM, DRAM or any other memory in Paragraph [0225], [0228]).
Regarding claim 20, NAKAZAWA teaches a memory system, comprising: a memory device, comprising:
a first semiconductor structure (100S along with other layers) comprising a first well region (p-well layer region 115) and transistors (The first substrate 100 includes a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing units 539. Each of the pixels 541 includes a photodiode. Paragraph [0230], FIG. 2) in the first well region, and
a second semiconductor structure (200S along with other layers) bonded with the first semiconductor structure (Shown in FIG. 6 where 200 is situated above 100 and connected to each other) and comprising a second well region (well region 211), and fin field effect transistors (AMP, Paragraph [0302], Paragraph [0527 reveals that it is an FinFET) in the second well region;
wherein each fin field effect transistor (AMP, Paragraph [0302], Paragraph [0527 reveals that it is an FinFET) comprises a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer; and
a controller (520, FIG. 2, Paragraph [0217]-[0228]) coupled to the memory device to control the memory device to store data .
NAKAZAWA does not explicitly teach wherein each fin field effect transistor comprises a fin structure in the same embodiment.
NAKAZAWA discloses each fin field effect transistor (AMP, Paragraph [0302], Paragraph [0527] reveals that it is an FinFET) comprises a fin structure (AMP includes a Fin, paragraph [0302], FIG. 6 and FIG. 16A-16B, Paragraph [0304]) in a different embodiment.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use NAKAZAWA’s semiconductor device with other teaching from NAKAZAWA such that it is possible to increase an effective gate width in the transistor, as compared with the planar type transistor. Accordingly, a large amount of current passes through the transistor having the three-dimensional structure to increase transconductance gm. This makes it possible to improve operation speed in the transistor having the three-dimensional structure, as compared with the planar type transistor. In addition, it is possible to reduce RN (Random Noise). In addition, the transistor having the three-dimensional structure has a larger gate area, as compared with the planar type transistor, which reduces RTS (Random Telegraph Signal) noise.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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