DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s reply filed on 1/23/2026 is acknowledged. Claim(s) 18-27 are canceled. New claim(s) 28-37 are added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 9-10, 13, 15-16, and 28-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirler et al. (US publication 2010/0044788 A1), hereinafter referred to as Hirler788.
Regarding claim 1, Hirler788 teaches a semiconductor structure (fig. 1 and related text), comprising: a substrate (6, [0012], fig. 1), comprising a first surface (7, top surface of 6) and a second surface (8, bottom surface of 6) opposite to each other, and comprising a unit region (9, [0012], fig. 1) and a terminal region (12/30, [0015]) adjacent to each other in a top view of the substrate (fig. 1); a first electrode structure (19/28, [0023]) in the substrate and extending from the first surface toward the second surface (fig. 1), the first electrode structure being disposed in the unit region (fig. 1); a first trench structure (19/20 near boundary between 9 and 30) in the substrate and extending from the first surface toward the second surface (fig. 1), the first trench structure disposed in the unit region and adjoining the terminal region (fig. 1), and the first trench structure comprising a first semiconductor material layer (20(15), [0012 and 0027]) extending to the first surface; and a capacitive structure (15(20)/18/n layer (below 18), fig. 1) on the first surface of the substrate (fig. 1), the capacitive structure disposed in the terminal region and adjoining the first trench structure (fig. 1), wherein the capacitive structure has a material same as the first semiconductor material layer (fig. 1), the capacitive structure includes a first capacitive electrode (15) and a second capacitive electrode (n layer (below 18)), and the first capacitive electrode is connected to the first semiconductor material layer (fig. 1).
Regarding claim 2, Hirler788 teaches further comprising: a second trench structure (p columns, fig. 1) in the substrate and extending from the first surface toward the second surface (fig. 1), the second trench structure being disposed in the terminal region and comprising a second semiconductor material layer that extends to the first surface, and the second capacitive electrode being connected to the second semiconductor material layer (fig. 1).
Regarding claim 3, Hirler788 teaches wherein a bottom of the first electrode structure and a bottom of the first trench structure are at about a same horizontal level (fig. 1).
Regarding claim 9, Hirler788 teaches wherein, the first electrode structure comprises a first electrode material layer extending from the first surface toward the second surface, and a width of the first semiconductor material layer at the first surface is about same as a width of the first electrode material layer at the first surface (fig. 1).
Regarding claim 10, Hirler788 teaches wherein a bottom of the first electrode material layer and a bottom of the first semiconductor material layer are at about a same horizontal level (fig. 1).
Regarding claim 13, Hirler788 teaches further comprising: a conductive material layer (13, [0013]) above the capacitive structure, the conductive material layer overlapping at least one of the first capacitive electrode or the second capacitive electrode (fig. 1).
Regarding claim 15, Hirler788 teaches further comprising: a first conductive plug (13, [0013]) on the first capacitive electrode, the first conductive plug electrically connected to the first capacitive electrode (fig. 1); and a second conductive plug (connector for 33, [0013]) on the second capacitive electrode, the second conductive plug electrically connected to the second capacitive electrode (fig. 1)
Regarding claim 16, Hirler788 teaches further comprising: a third conductive plug (conductive plug over 27, fig. 1) extending from above the first surface toward the second surface, the third conductive plug disposed in the unit region and adjacent to the first electrode structure, and a top surface of the third conductive plug and a top surface of the first conductive plug or the second conductive plug being at about a same horizontal level (fig. 1).
Regarding claim 28, Hirler788 teaches a semiconductor structure (fig. 1 and related text), comprising: a first electrode structure (19/28, [0023]) in a unit region of a substrate (6, [0012], fig. 1) and extending from a surface (top or bottom surface of 6) of the substrate into the substrate (fig. 1), the first electrode structure comprising a shield electrode layer (28) surrounded by a dielectric layer (19); a first trench (19/20 near boundary between 9 and 30) structure in the unit region and extending from the surface of the substrate into the substrate (fig. 1), the first trench structure comprising a first semiconductor material layer (20(15), [0012 and 0027]) extending towards and above the surface of the substrate (fig. 1); and a capacitive structure (15(20)/18/n layer (below 18), fig. 1) disposed on the surface of the substrate and in a terminal region of the substrate adjacent to the unit region (fig. 1), the capacitive structure comprising a first capacitive electrode (15) and a second capacitive electrode (n layer (below 18)), and the first capacitive electrode being connected to the first semiconductor material layer (fig. 1).
Regarding claim 29, Hirler788 teaches further comprising: a second trench structure (p columns, fig. 1) in the terminal region and extending from the surface of the substrate into the substrate, the second trench structure comprising a second semiconductor material layer extending towards and above the surface of the substrate, and being connected to the second capacitive electrode (fig. 1).
Regarding claim 30, Hirler788 teaches further comprising: a conductive material layer (13, [0013]) on the capacitive structure partially covering the first capacitive electrode and the second capacitive electrode (fig. 1).
Allowable Subject Matter
Claims 4-8, 11-12, 14, 17, and 31-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The claims contain limitations that none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Claims 37 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 37 is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
“…the first electrode structure comprising a shield electrode layer surrounded by a dielectric layer, and a first gate electrode layer disposed over and separated from the shield electrode layer; a capacitive structure in the terminal region and on the first surface of the substrate, the capacitive structure comprising a first capacitive electrode and a second capacitive electrode disposed along the first surface of the substrate and separated from each other, wherein a top surface of the first capacitive electrode is flush with a top surface of the second capacitive electrode, and a bottom surface of the first capacitive electrode on the first surface is flush with a bottom surface of the second capacitive electrode on the first surface…”.
The Prior Arts of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: the limitations of claim 37 in its entirety (some limitations may be found (as explained above for claim 1 rejection) but not in combination with proper motivation). Hence, claim 37 is allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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