Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
6 pending office actions • 3 art units • 6 examiners • 0 of 6 (0%) have an AI response strategy ready • 26 patents granted in the last 365 days
Diodes Incorporated has 6 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are being handled by distinct examiners, ensuring that each pending case is under the review of a different individual. This distribution across the examiners means that no single examiner has a cumulative view of the current pending portfolio.
The active cases are spread across 3 distinct art units, which indicates that the 6 pending office actions fall into several different technical sub-categories within the semiconductor field. ZHANG, JUE is the busiest examiner for this portfolio, currently managing 1 pending office action. This single pending office action is the maximum number assigned to any one examiner for this company.
With 3 distinct art units involved, the prosecution strategy must account for the specific nuances of multiple examination groups. The fact that the examiners are assigned to only the pending office actions suggests a highly individualized approach to each application. Practitioners will interact with a new examiner for every pending action, as the busiest examiner, ZHANG, JUE, only holds one of the total actions. This variety of examiners ensures that the pending office actions are evaluated from multiple perspectives.
Based on the USPTO statutory response window for each pending office action. 3 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 3 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 1 (17%) |
| §102 only | 3 (50%) |
| Multi-statute (no §101) | 2 (33%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| ZHANG, JUE | 1 | 83.3% | +10.0% |
| MAI, ANH D | 1 | 37.7% | +9.6% |
| MAZUMDER, DIDARUL A | 1 | 86.5% | +7.8% |
| OZDEN, ILKER NMN | 1 | 84.6% | +23.1% |
| ALAM, MOHAMMED R | 1 | 89.5% | +6.0% |
| ARROYO, TERESA M | 1 | 71.9% | +23.2% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18378553 | Semiconductor Structure and Manufacturing Method Thereof | ALAM, MOHAMMED R | 41d |
| 18958586 | Bootstrap Capacitor Refresh Control Apparatus and Method | ZHANG, JUE | — |
| 18817110 | Semiconductor Chip Package and Manufacturing Method Thereof | MAZUMDER, DIDARUL A | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18952927 | TRENCHED SCHOTTKY STRUCTURE HAVING A DOPED REGION LOCATED AT A CENTRAL POSITION BETWEEN FIRST TRENCH AND SECOND TRENCH STRUCTURES | MAI, ANH D | 39d |
| 18787861 | TRENCH SEMICONDUCTOR POWER DEVICE | OZDEN, ILKER NMN | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18193598 | PACKAGING SUBSTRATE, GRID ARRAY PACKAGE, AND PREPARATION METHOD THEREFOR | ARROYO, TERESA M | 42d overdue |
| 18958586 | Bootstrap Capacitor Refresh Control Apparatus and Method | ZHANG, JUE | — |
| 18787861 | TRENCH SEMICONDUCTOR POWER DEVICE | OZDEN, ILKER NMN | — |
| Art Unit | Apps |
|---|---|
| 2893 | 2 |
| 2838 | 1 |
| 2897 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18958586 | Bootstrap Capacitor Refresh Control Apparatus and Method | ZHANG, JUE | 2838 | §102 | Final Rejection | — | Pending | Nov 25, 2024 |
| 18952927 | TRENCHED SCHOTTKY STRUCTURE HAVING A DOPED REGION LOCATED AT A CENTRAL POSITION BETWEEN FIRST TRENCH AND SECOND TRENCH STRUCTURES | MAI, ANH D | 2893 | §103§112 | Non-Final OA | 39d | Pending | Nov 19, 2024 |
| 18817110 | Semiconductor Chip Package and Manufacturing Method Thereof | MAZUMDER, DIDARUL A | — | §102Other | Non-Final OA | — | Pending | Aug 27, 2024 |
| 18787861 | TRENCH SEMICONDUCTOR POWER DEVICE | OZDEN, ILKER NMN | — | §102§103 | Non-Final OA | — | Pending | Jul 29, 2024 |
| 18378553 | Semiconductor Structure and Manufacturing Method Thereof | ALAM, MOHAMMED R | 2897 | §102 | Final Rejection | 41d | Pending | Oct 10, 2023 |
| 18193598 | PACKAGING SUBSTRATE, GRID ARRAY PACKAGE, AND PREPARATION METHOD THEREFOR | ARROYO, TERESA M | 2893 | §103 | Final Rejection | 42d overdue | Pending | Mar 30, 2023 |
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